201135466 六、發明說明： 【發明所屬之技術領域】 [麵]树明涉及-種時序控制電路，尤其涉及電腦前端匯流 排電源時序控制電路及具有該時序控制電路之前端匯流 排電源。 【先前技術】 [〇〇〇2]前端匯流排（Fron1: Side Bus，FSB)是用於將電腦中 央處理器（Central processing Unit，cpu)連接到 Q 北橋晶片之匯流排。一般來說，前端匯流排是CPU和外界 交換資料之最主要通道’因此前端匯流排之資料傳輸能 力對計异及整體性能作用很大。而前端匯流排電源工作 之穩定性對其資料傳輸能力真有極大溱響。 [0003] 習知之前端匯流排電源一般包括如下功能模組： [0004] —高級配置和電源管理介面（Advanced c〇nfigura_ tion and Power Management Interface, ACPI) 晶片 ; 〇 [0005] —ACPI供電電源模組：用於為ACPI晶片提供工作所需之 電源； [0006] 一時序控制電路：為前端匯流排電源提供一個時序控制 訊號； _7] - 5V雙重電源產生電路：為下述之記憶體電源產生電路 提供一個輸入電源； [0008] 一記憶體電源產生電路：為下述之前端匯流排電源產生 電路提供一工作電壓； 099111886 表單編號 A0101 « q έ/^l is έ 示 〇 只/穴 ίο 只 0992021020-0 201135466 [0009] [0010] [0011] [0012] [0013] [0014] [0015] [0016] 099111886 以及一前端匯流排電源產生電路：為前端匯流排提供工 作電壓。 然而，習知之前端匯流排電源之時序控制電路之設計一 般只適用於CPU負載電流較小之情況，當搭配有一些負載 較大之CPIJ(如四核CPU)之電腦系統需要作出開機或者睡 眠喚醒動作時，傳統之前端匯流排電源時序控制電路設 計就可能不適用了，可能會使電腦發生無法開機或者自 動重啟之故障。 【發明内容】 鑒於以上情況，有必要提供一種適用於負載較大之CPU之 前端匯流排電源時序控制電路。 還有必要提供一種具有上述時序控制電路之前端匯流排 電源。 一種時序控制電路，用於為電腦之前端匯流排電源提供 一時序控制訊號，所述時序控制電路包括一電子開關及 二分壓電阻，所述二分壓電阻串聯後分別接至一系統電 源及接地，所述二分壓電阻之間輸出一時序控制訊號， 所述電子開關第一端電性連接至該二分壓電阻之間，第 二端電性連接至一電腦之一控制訊號端，該控制訊號端 之電平與該時序控制訊號之電平同相設置。 一種前端匯流排電源，包括 一 ACPI晶片； 一上述之時序控制電路，該時序控制電路為前端匯流排 電源提供一個時序控制訊號； 表單編號A0101 第4頁/共18頁 201135466 [0017] 一電性連接至所述ACPI晶片之雙重電源產生電路，該雙 重電源產生電路輸出一輸入電壓訊號，該輸入電壓訊號 由ACPI晶片控制為一電腦之系統電源端電壓或者待機電 源端電壓之一； [0018] 〇 一記憶體電源產生電路，其分別電性連接至所述ACPI晶 片及雙重電源產生電路，該記憶體電源產生電路以所述 輸入電壓訊號為輸入電源，並輸出一工作電壓訊號，該 工作電壓訊號之輸出藉由所述ACPI晶片受所述時序控制 訊號之控制； [0019] 及一前端匯流排電源產生電路，其分別電性連接至所述 ACPI晶片及該記憶體電源產生電路，該前端匯流排電源 產生電路以所述工作電壓訊號為輸入電源，並輸出一工 作電源至前端匯流排，該工作電源之輸出受該時序控制 訊號之控制。 [0020] 與習知技術相比，所述之時序控制電路藉由將電腦之控 ❹ 制訊號端藉由一電子開關連接至所述二分壓電阻之間， 並輸出一時序控制訊號至該ACPI晶片，使該控制訊號端 藉由控制該時序控制訊號之電平變化，而可使該前端匯 流排電源在系統開機或者睡眠喚醒時使用負載能力較強 之系統電源端進行供電，該系統電源端之電壓不會被負 載拉低，從而可有效防止電腦系統出現無法開機或者自 動重啟之情況發生。 [0021] 【實施方式】 請參閱圖1，本發明較佳實施方式之前端匯流排電源100 099111886 包括一ACPI晶片10、一ACPI晶片電源20、一時序控制電 表單編號A0101 第5頁/共18頁 0992021020-0 201135466 路30、-雙重電源產生電路4〇、一記億體電源產生電路 50及一前端匯流排電源產生電路60。所述ACPI晶片電源 20、時序控制電路30、雙重電源產生電路4〇、記憶^電 源產生電路50及前端匯流排電源產生電路6〇均電性連接 至所述ACPI晶片1〇。所述Acp“％片電源2〇可將系統電源 (圖未示）提供之電壓轉換為所述ACPI晶片1〇所需之工 作電壓。所述時序控制電路3〇為所述Acpi晶片1〇提供一 時序控制訊號VCC3V。所述雙重電源產生電路4{)電性連接 至記憶體電源產生電路50，並為該記憶體電源產生電路 50提供一輸人電麼訊號5V_DUAL，以作為該記憶體電源 產生電路50之輸入電源。所述記憶體電源產生電路5〇電 性連接至所述前端匯流排電源產生電路6〇 ,並為該前端 匯流排電源產生電路60提供一工作電壓訊號1D5V_DUAL ，作為該前端匯流排電源產生電路6〇之輸入電源。所述 前端匯流排電源產生電路6〇將所述工作電壓工作電壓 1D5V—MAL轉換為一工作電澡詆號yTT_pwR，以供前端 匯流排使用。 [0022]所述ACPI晶片包括一PWOKIN引腳、一DUALGATE引腳、 一VCCGATE引腳及一VCC3V引腳《所述pw〇KIN引腳電性 連接至電腦之ATXPWRGD訊號端。ATXPWRGD訊號為電腦 系統電源（圖未示）發出之一表示系統電源正常之訊號 。所述ATXPWRGD訊號端在電腦正常工作時為高電平，在 電腦關機、睡眠及睡眠喚醒之瞬間為低電平。所述 DUALGATE引腳及VCCGATE引腳均電性連接至所述雙重電 源產生電路40 ’並分別對應輸出一DUAL_GATE訊號及一 099111886 表單編號A0101 第6頁/共18頁 0992021020-0 201135466 VCC_GATE訊號至雙重電源產生電路40。請一併參閱圖2 ，所述DUAL—GATE訊號及VCC—GATE訊號之電平狀態由所 述PWOKIN之電平狀態決定。當所述PWOKIN訊號為高電平 時，所述DUAL_GATE為低電平，VCC—GATE為高電平；當 所述PWOKIN訊號為低電平時，所述DUAL_GATE為高電平 ，VCC—GATE為低電平。所述VCC3V引腳電性連接至所述 時序控制電路30，以接受所述時序控制電路30輸出之時 序控制訊號VCC3V。在系統開機或睡眠喚醒時，當所述時 序控制訊號VCC3V達到2. 7V (高電平）時，在所述ACPI 〇 晶片内部會產生一個3V0K訊號’用於孩制記憶體電源產 生電路50及前端匯流排電源產生電路60之時序。 [0023] 所述時序控制電路30包括分壓電阻R31和R32及一電子開 關。所述分壓電阻R31和R32之一端相互串接，另一端分 別連接至電腦之系統電源端及接地。所述ACPI晶片之 VCC3V引腳電性連接至該分壓電晖R31和R32之間。該分 壓電阻R31和R32對系統電源進行分壓後輸出一電壓至該 0 VCC3V引腳。所述電子開關包括一第一端及一第二端，該 第一端電性連接至所述分壓電阻R31和R32之間，第二端 電性連接至電腦之ATXPWRGD訊號端。在本實施方式中， 所述電子開關為一二極體D31。所述二極體D31之陽極（相 當於上述電子開關之第一端）電性連接至所述分壓電阻 R31和R32之間，陰極（相當於上述電子開關之第二端） 電性連接至電腦之ATXPWRGD訊號端。當該ATXPWRGD訊 號端為高電平時，該二極體D31截止，該時序控制電路30 輸出之時序控制訊號VCC3V為分壓電阻R31和R32之間之 099111886 表單煸號A0101 第7頁/共18頁 0992021020-0 201135466 電壓；當該ATXPWRGD訊號端為低電平時，二極體D31導 通，該時序控制訊號VCC3V訊號為該ATXPWRGD訊號端之 電壓，即為低電平。 [〇〇24] 所述雙重電源產生電路40輸出一輸入電壓訊號5V_DUAL， 該輸入電壓訊號5V_DUAL由所述DUAL_GATE訊號及 VCC_GATE訊號之電平狀態決定，即當所述DUAL_GATE為 低電平，VCC_GATE為高電平時，輸入電壓訊號5V_DUAL 由系統電源端5V_SYS供電；當所述DUAL_GATE為高電平 ，VCC_GATE為低電平時，輪入電壓訊號5V_DUAL由待機 電源端5V_SB供電。換句話說，當電腦系統處於開機狀態 時，PWOKIN (ATXPWRGD)訊號為高電平，輸入電壓訊號 5V一DUAL由系統電源端5V—SYS供電；：當所述系統處於關 機、睡眠狀態或睡眠喚醒瞬間時，PWOKIN (ATXPWRGD) 訊號為低電平’輸入電壓訊號5V_DUAL由待機電源端 5V__SB供電。 [0025] 所述記憶體電源產生電路5〇以所遴輸入電壓訊號 5V 一 DUAL作為輸入電源’並將所述1D5V_STR訊號輸出至 所述前端匯流排電源產生電路6〇。所述1D5V_STR訊號在 時序控制訊號VCC3V超過2.7V (高電平），即3V0K訊號 變為高電平之後即會產生。 [0026] 所述前端匯流排電源產生電路60以1D5V_STR訊號作為輸 入電源，其輸出之工作電源VTT_pwR訊號也在該時序控制 訊號VCC3V超過2. 7V (高電平），即3V〇K訊號變為高電 ip·之後即會產生。 099111886 表單編號A0101 第8頁/共18頁 0992021020-0 201135466 [0027] 由於該前端匯流排電源產生電路60之輸入電源由該記憶 體電源產生電路50之l])5V_STR訊號作為輸入電源，而該 記憶體電源產生電路5〇又由該輸入電壓訊號5V_DUAL作 為輸入電源’使得系統在開機上電或者睡眠喚醒時會使 用該輸入電壓訊號5 V_DUAL提供之電流，該電流在開機上 電瞬間或者睡眠喚醒瞬間較大，這就需要輸入電壓訊號 5V_DUAL具有較大之負載能力，以防該輸入電壓訊號 5V—DUAL之電壓被拉低，造成電腦系統無法開機或者自動 重啟之情況。 Ο [0028] Ο 當系統在開機上電瞬間或者睡眠喚醒瞬間時，所述 ATXPWRGD訊號為低電平，輸入電壓訊號5V_DUAL由待機 電源端5V_SB供電。此時該VCC3V也為低電平，則前端匯 流排電源產生電路60不會產生工作電源VTT_PWR訊號， 從而不會使用負載能力較小之待機電源端5V_SB向前端匯 流排電源產生電路60進行供電，從而可避免出現因輸入 電壓訊號5V_SB之負载能力較小而導致無法開機或者自動 重啟之情況。當所述ATXPWRGD訊號為上升為高電平時， 輸入電壓訊號5V_DUAL由系統電源端5V_SYS供電；而此 時時序控制訊號VCC3V也為高電平，前端匯流排電源產生 電路60產生工作電源VTT一PWR訊號，此時該前端匯流排 電源產生電路60使用負載能力較強之系統電源端5V_SYS 進行供電，該系統電源端5V一SYS之電壓不會被負載拉低 ，從而可有效防止電腦系統出現無法開機或者自動重啟 之情況發生。 [0029] 請一併參閱圖3，圖3所示為本發明時序控制電路3〇另一 099111886 表單編號A0101 第9頁/共18頁 0992021020-0 201135466 較佳實施方式之電路圖。在本實施方式中，所述電子開 關由一第一N溝道MOS型場效應電晶體q3i、一第二N溝道 M0S型場效應電晶體Q32及一上拉電阻R33構成。所述第 一 N溝道M0S型場效應電晶體Q31和第二N溝道M0S型場效 應電晶體Q32之源極均接地，該第一 N溝道M0S型場效應電 晶體Q31之漏極電性連接至該第二N溝道M0S型場效應電晶 體Q32之柵極後，並藉由所述上拉電阻R33連接至系統電 源5V_SYS ;該第二N溝道M0S型場效應電晶體Q32之漏極 (相當於上述電子開關之第一端）電性連接至所述電阻 R31及R32之間；該第一N溝道M0S型場效應電晶體Q31之 栅極（相當於電子開關之第二端）藉由一電阻R34電性連 接至該ATXPWRGD訊號端。調節該電阻R34之阻值，可以 調節該N溝道M0S型場效應電晶體Q31之漏極之輸出相對於 該ATXPWRGD訊號之延遲時間。當ATXPWRGD訊號端為高 電平時，該N溝道M0S型場效應電晶體Q31導通，該N溝道 M0S型場效應電晶體Q32截至，該時序控制訊號VCC3V為 高電平；當該ATXPWRGD訊號端為低電平時，該N溝道M0S 型場效應電晶體Q31截至，該N溝道M0S型場效應電晶體 Q32導通，該時序控制訊號VCC3V為低電平。 [0030] 可以理解，所述第一N溝道MOS型場效應電晶體Q31及第二 N溝道MOS型場效應電晶體Q32可以分別由一第一NPN型三 極管及一第二NPN型三極管代替，其中第一N溝道M0S型場 效應電晶體Q31及第二N溝道MOS型場效應電晶體Q32之柵 極、源極和漏極分別對應所述第一NPN型三極管及第二 NPN塑三極管之基極，發射極和集電極。 099111886 表單編號A0101 第10頁/共18頁 0992021020-0 201135466 [0031] 本發明所述之時序控制電路30藉由將電腦之ATXPWRGD訊 號端藉由一電子開關連接至該VCC3V引腳，使該時序控制 訊號VCC3V之電平變化受該ATXPWRGD訊號端控制，從而 可使該前端匯流排電源100在系統開機或者睡眠喚醒時使 用負載能力較強之系統電源端5V_SYS進行供電，該系統 電源端5V_SYS之電壓不會被負載拉低，從而可有效防止 電腦系統出現無法開機或者自動重啟之情況發生。 [0032] 綜上所述，本發明符合發明專利要件，爰依法提出專利 ^ 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 ❹ 熟悉本案技藝之人士，於爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 _ 【圖式簡單說明】 [0033] 圖1係具有本發明一較佳實施方式之時序控制電路之前端 匯流排電源之電路圖。 [0034] 圖2係本發明時序控制電路之時序圖。 [0035] 圖3係本發明時序控制電路另一較佳實施方式之電路圖。 〇 【主要元件符號說明】 [0036] 前端匯流排電源：100 [0037] ACPI 晶片：10 [0038] ACPI 晶片電源：20 [0039] 時序控制電路：30 [0040] 雙重電源產生電路：40 [0041] 記憶體電源產生電路：50 099111886 表單編號A0101 第11頁/共18頁 0992021020-0 201135466 [0042] 前端匯流排電源產生電路 60 099111886 表單編號A0101 第12頁/共18頁 0992021020-0201135466 VI. Description of the Invention: [Technical Fields of the Invention] [Face] A tree-related timing control circuit is involved, in particular, a computer front-end bus power supply timing control circuit and a front-end bus power supply having the timing control circuit. [Prior Art] [〇〇〇2] The front-end bus (Fron1: Side Bus, FSB) is a bus used to connect a central processing unit (cpu) to a Q-North Bridge chip. In general, the front-end bus is the most important channel for the CPU to exchange data with the outside world. Therefore, the data transmission capability of the front-end bus has a great effect on the calculation and overall performance. The stability of the front-end bus power supply is really great for its data transmission capability. [0003] Conventional front-end bus power supplies generally include the following functional modules: [0004] - Advanced configuration and power management interface (ACPI) chip; 〇 [0005] - ACPI power supply mode Group: used to supply power to the ACPI chip; [0006] A timing control circuit: provides a timing control signal for the front-end bus power; _7] - 5V dual power generation circuit: for the following memory power generation The circuit provides an input power; [0008] a memory power generating circuit: provides an operating voltage for the following front bus power generating circuit; 099111886 Form number A0101 « q έ / ^l is έ 〇 only / ίο only [0010] [0015] [0016] [0016] [0016] 099111886 and a front-end bus power generation circuit: provide operating voltage for the front-end bus. However, the design of the timing control circuit of the prior-side bus power supply is generally only applicable to the case where the CPU load current is small. When a computer system with a large load of CPIJ (such as a quad-core CPU) needs to be turned on or sleep awakened, During the operation, the traditional front-end bus power supply timing control circuit design may not be applicable, which may cause the computer to fail to boot or automatically restart. SUMMARY OF THE INVENTION In view of the above circumstances, it is necessary to provide a front-end bus power supply timing control circuit suitable for a CPU with a large load. It is also necessary to provide a front-side bus power supply having the above-described timing control circuit. A timing control circuit is configured to provide a timing control signal for the front-end bus power supply of the computer, the timing control circuit includes an electronic switch and a two-dividing resistor, wherein the two-divided resistors are connected in series to a system power supply and Grounding, a timing control signal is outputted between the two voltage dividing resistors, a first end of the electronic switch is electrically connected between the two voltage dividing resistors, and a second end is electrically connected to a control signal end of a computer. The level of the control signal terminal is set in phase with the level of the timing control signal. A front-end bus power supply, comprising an ACPI chip; a timing control circuit, the timing control circuit provides a timing control signal for the front-end bus power; Form No. A0101 Page 4 / 18 pages 201135466 [0017] a dual power generating circuit connected to the ACPI chip, the dual power generating circuit outputting an input voltage signal controlled by the ACPI chip as one of a system power terminal voltage or a standby power terminal voltage of a computer; [0018] a memory power generating circuit electrically connected to the ACPI chip and the dual power generating circuit, wherein the memory power generating circuit uses the input voltage signal as an input power source and outputs a working voltage signal, the working voltage The output of the signal is controlled by the timing control signal by the ACPI chip; [0019] and a front-end bus power generation circuit electrically connected to the ACPI chip and the memory power generation circuit, respectively. The bus power generation circuit uses the working voltage signal as an input power source and outputs a work The power is supplied to the front-end bus, and the output of the working power is controlled by the timing control signal. [0020] Compared with the prior art, the timing control circuit connects the control signal terminal of the computer to the two voltage dividing resistors through an electronic switch, and outputs a timing control signal to the The ACPI chip enables the control signal terminal to control the level change of the timing control signal, so that the front-end bus power supply can be powered by the system power supply with strong load capability when the system is powered on or wakes up. The voltage of the terminal will not be pulled down by the load, which can effectively prevent the computer system from being unable to boot or automatically restart. [0021] Referring to FIG. 1, a front end bus power supply 100 099111886 includes an ACPI chip 10, an ACPI chip power supply 20, a timing control electric form number A0101, page 5 of 18, in a preferred embodiment of the present invention. Page 0992021020-0 201135466 Road 30, a dual power generating circuit 4, a billiard power generating circuit 50 and a front bus power generating circuit 60. The ACPI chip power supply 20, the timing control circuit 30, the dual power generation circuit 4, the memory power generation circuit 50, and the front-end bus power generation circuit 6 are all electrically connected to the ACPI wafer 1A. The Acp "% chip power supply 2" converts the voltage provided by the system power supply (not shown) into the operating voltage required by the ACPI chip 1. The timing control circuit 3 provides the Acpi chip 1 a timing control signal VCC3V. The dual power generating circuit 4{) is electrically connected to the memory power generating circuit 50, and provides a power input signal 5V_DUAL for the memory power generating circuit 50 to serve as the memory power source. The input power source of the circuit 50 is generated. The memory power generating circuit 5 is electrically connected to the front-end bus power generating circuit 6〇, and provides a working voltage signal 1D5V_DUAL for the front-end bus power generating circuit 60. The front-end bus power generation circuit generates an input power of the circuit 6. The front-end bus power generation circuit 6 converts the working voltage working voltage 1D5V-MAL into a working electric bath number yTT_pwR for use in the front-end bus. 0022] The ACPI chip includes a PWOKIN pin, a DUALGATE pin, a VCCGATE pin, and a VCC3V pin. The pw〇KIN pin is electrically connected to the ATXPWRGD of the computer. The ATXPWRGD signal is a signal indicating that the system power is normal when the computer system power supply (not shown) is sent. The ATXPWRGD signal terminal is high when the computer is working normally, and is low at the moment when the computer is shut down, sleep and sleep wake up. The DUALGATE pin and the VCCGATE pin are electrically connected to the dual power generating circuit 40' and respectively output a DUAL_GATE signal and a 099111886 form number A0101 page 6 / 18 pages 0992021020-0 201135466 VCC_GATE Signal to the dual power generating circuit 40. Please refer to FIG. 2 together, the level states of the DUAL-GATE signal and the VCC-GATE signal are determined by the level state of the PWOKIN. When the PWOKIN signal is high, The DUAL_GATE is low level, VCC_GATE is high level; when the PWOKIN signal is low level, the DUAL_GATE is high level, and VCC_GATE is low level. The VCC3V pin is electrically connected. Up to the timing control circuit 30 to receive the timing control signal VCC3V output by the timing control circuit 30. When the system is powered on or wake-up wake up, when the timing control signal VCC3V When it is 2. 7V (high level), a 3V0K signal is generated inside the ACPI 〇 chip for the timing of the child memory power generation circuit 50 and the front side bus power generation circuit 60. [0023] The timing control circuit 30 includes voltage dividing resistors R31 and R32 and an electronic switch. One ends of the voltage dividing resistors R31 and R32 are connected in series, and the other ends are respectively connected to the system power terminal of the computer and the ground. The VCC3V pin of the ACPI chip is electrically connected between the sub-piezoelectric R31 and R32. The voltage dividing resistors R31 and R32 divide the system power supply and output a voltage to the 0 VCC3V pin. The electronic switch includes a first end and a second end. The first end is electrically connected to the voltage dividing resistors R31 and R32, and the second end is electrically connected to the ATXPWRGD signal end of the computer. In this embodiment, the electronic switch is a diode D31. The anode of the diode D31 (corresponding to the first end of the electronic switch) is electrically connected between the voltage dividing resistors R31 and R32, and the cathode (corresponding to the second end of the electronic switch) is electrically connected to The ATXPWRGD signal end of the computer. When the ATXPWRGD signal terminal is at a high level, the diode D31 is turned off, and the timing control signal VCC3V outputted by the timing control circuit 30 is 099111886 between the voltage dividing resistors R31 and R32. Form number A0101 Page 7 of 18 0992021020-0 201135466 Voltage; when the ATXPWRGD signal terminal is low level, the diode D31 is turned on, and the timing control signal VCC3V signal is the voltage of the ATXPWRGD signal terminal, that is, low level. [〇〇24] The dual power generating circuit 40 outputs an input voltage signal 5V_DUAL, and the input voltage signal 5V_DUAL is determined by the level state of the DUAL_GATE signal and the VCC_GATE signal, that is, when the DUAL_GATE is low, VCC_GATE is When the level is high, the input voltage signal 5V_DUAL is powered by the system power terminal 5V_SYS; when the DUAL_GATE is high level and VCC_GATE is low level, the wheeled voltage signal 5V_DUAL is powered by the standby power terminal 5V_SB. In other words, when the computer system is powered on, the PWOKIN (ATXPWRGD) signal is high, and the input voltage signal 5V-DUAL is powered by the system power terminal 5V-SYS; when the system is in shutdown, sleep state or sleep wake-up At the moment, the PWOKIN (ATXPWRGD) signal is low. The input voltage signal 5V_DUAL is powered by the standby power terminal 5V__SB. [0025] The memory power generating circuit 5 outputs the 1D5V_STR signal to the front-end bus power generating circuit 6A by using the input voltage signal 5V_DUAL as the input power source'. The 1D5V_STR signal is generated after the timing control signal VCC3V exceeds 2.7V (high level), that is, after the 3V0K signal goes high. [0026] The front-end bus power generation circuit 60 uses the 1D5V_STR signal as the input power source, and the output of the operating power supply VTT_pwR signal is also greater than 2. 7V (high level), that is, the 3V〇K signal is changed to the timing control signal VCC3V. It will be generated after high power ip·. 099111886 Form No. A0101 Page 8 of 18 0992021020-0 201135466 [0027] Since the input power of the front-end bus power generating circuit 60 is used as the input power by the memory power generating circuit 50, the 5V_STR signal is used as the input power source. The memory power generating circuit 5 is further configured to use the input voltage signal 5V_DUAL as the input power source to make the system use the current provided by the input voltage signal 5 V_DUAL when the system is powered on or wake up, and the current is awakened at the power-on or wake-up sleep. The moment is large, which requires the input voltage signal 5V_DUAL to have a large load capacity, in case the voltage of the input voltage signal 5V-DUAL is pulled down, causing the computer system to fail to boot or automatically restart. Ο [0028] Ο When the system is powered on or the sleep wakes up, the ATXPWRGD signal is low, and the input voltage signal 5V_DUAL is powered by the standby power terminal 5V_SB. At this time, the VCC3V is also at a low level, and the front-end bus power generation circuit 60 does not generate the working power VTT_PWR signal, so that the standby power supply terminal 5V_SB with a small load capacity is not used to supply power to the front-end bus power generation circuit 60. Therefore, the situation that the input voltage signal 5V_SB has a small load capacity and cannot be turned on or automatically restarted can be avoided. When the ATXPWRGD signal is rising to a high level, the input voltage signal 5V_DUAL is powered by the system power terminal 5V_SYS; and at this time, the timing control signal VCC3V is also high, and the front-end bus power generation circuit 60 generates the working power VTT-PWR signal. At this time, the front-end bus power generation circuit 60 is powered by the system power terminal 5V_SYS with a strong load capacity, and the voltage of the system 5V-SYS is not pulled down by the load, thereby effectively preventing the computer system from being turned on or An automatic restart occurs. Please refer to FIG. 3 together. FIG. 3 is a circuit diagram of a preferred embodiment of the timing control circuit 3 of the present invention, another 099111886 form number A0101, page 9 / page 18 0992021020-0 201135466. In this embodiment, the electronic switch is composed of a first N-channel MOS type field effect transistor q3i, a second N-channel MOS type field effect transistor Q32, and a pull-up resistor R33. The sources of the first N-channel MOS type field effect transistor Q31 and the second N-channel MOS type field effect transistor Q32 are grounded, and the drain of the first N-channel MOS type field effect transistor Q31 is electrically Connected to the gate of the second N-channel MOS type field effect transistor Q32, and connected to the system power supply 5V_SYS by the pull-up resistor R33; the second N-channel MOS type field effect transistor Q32 a drain (corresponding to the first end of the electronic switch) is electrically connected between the resistors R31 and R32; a gate of the first N-channel MOS type field effect transistor Q31 (corresponding to the second of the electronic switch) The terminal is electrically connected to the ATXPWRGD signal terminal by a resistor R34. Adjusting the resistance of the resistor R34 can adjust the delay time of the output of the drain of the N-channel MOS field effect transistor Q31 with respect to the ATXPWRGD signal. When the ATXPWRGD signal terminal is at a high level, the N-channel MOS type field effect transistor Q31 is turned on, the N-channel MOS type field effect transistor Q32 is turned off, the timing control signal VCC3V is at a high level; when the ATXPWRGD signal end When the level is low, the N-channel MOSFET type field effect transistor Q31 is turned off, and the N-channel MOS type field effect transistor Q32 is turned on, and the timing control signal VCC3V is at a low level. [0030] It can be understood that the first N-channel MOS type field effect transistor Q31 and the second N-channel MOS type field effect transistor Q32 can be replaced by a first NPN type transistor and a second NPN type transistor respectively. The gate, the source and the drain of the first N-channel MOSFET type field effect transistor Q31 and the second N-channel MOS type field effect transistor Q32 respectively correspond to the first NPN type transistor and the second NPN plastic The base, emitter and collector of the triode. 099111886 Form No. A0101 Page 10 of 18 0992021020-0 201135466 [0031] The timing control circuit 30 of the present invention makes the timing by connecting the ATXPWRGD signal terminal of the computer to the VCC3V pin through an electronic switch. The level change of the control signal VCC3V is controlled by the ATXPWRGD signal end, so that the front-end bus power supply 100 can be powered by the system power terminal 5V_SYS with strong load capability when the system is powered on or wake-up, and the voltage of the system power terminal 5V_SYS It will not be pulled down by the load, which can effectively prevent the computer system from being unable to boot or automatically restart. [0032] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art in the spirit of the present invention are intended to be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0033] FIG. 1 is a circuit diagram of a busbar power supply having a front end of a timing control circuit according to a preferred embodiment of the present invention. 2 is a timing diagram of a timing control circuit of the present invention. 3 is a circuit diagram of another preferred embodiment of the timing control circuit of the present invention. 〇 [Main component symbol description] [0036] Front-end bus power supply: 100 [0037] ACPI chip: 10 [0038] ACPI chip power supply: 20 [0039] Timing control circuit: 30 [0040] Dual power generation circuit: 40 [0041 ] Memory Power Generation Circuit: 50 099111886 Form No. A0101 Page 11 / Total 18 Page 0992021020-0 201135466 [0042] Front Side Bus Power Generation Circuit 60 099111886 Form No. A0101 Page 12 of 18 0992021020-0