201134089 六、發明說明： 【發明所屬之技術領域】 本發明内容是有關於一種電子元件，且特別是有關於 一種運算放大器。 【先前技術】 一般在電路中所稱軌對軌(rail_t〇_rail)的電路特性，主 要是指當輸人電壓值在—限定範圍内，經過㈣執輸出級 電路之後’其輸出與輸人之電壓值會相依地進行同少變 化，因此其輸出電壓之振幅可以達到非常接近輸入電源電 壓之振巾胃’例如.當輸人電源是5V，理想轨對軌輸出值< 以達到0—5V。 ，以轨對軌運算放大器電路而言，通常在其輸入級中會 =用/、模輪入電壓來操作相互並聯的N型電晶體與p蜇電201134089 VI. Description of the Invention: [Technical Field] The present invention relates to an electronic component, and more particularly to an operational amplifier. [Prior Art] Generally speaking, the circuit characteristics of rail-to-rail (rail_t〇_rail) in the circuit mainly refer to when the input voltage value is within the limited range, after (4) executing the output stage circuit, its output and input are The voltage value will change with the same amount, so the amplitude of the output voltage can reach the vibrating stomach very close to the input power supply voltage. For example, when the input power is 5V, the ideal rail-to-rail output value is < 5V. In the case of a rail-to-rail operational amplifier circuit, it is usually used in its input stage to operate the N-type transistor and p-electrode in parallel with the /, mode-in voltage.
BB體使得兩電晶體互補地進行操作。然而，當並聯的NThe BB body allows the two transistors to operate complementarily. However, when connected in parallel
型電晶體與P型電晶體互補地進行操作時，通常會由於N =電晶體及P型電晶體其中一者關閉，因而缺少一路的電 肌供應。如此一來，輸出的電流便會據此而有所變化，且 相對應輸出電流的轉導(transconductance)也會跟著改變， 由於玫大器的單位增益頻率（unity-gain frequency)或是 皁位增益頻寬(unity-gain bandwidth)是隨著轉導變化，所以 也會影響頻率的補償。為此，如何避免電流受到共模輸入 電壓影響’並使輸出電流盡量維持一定的狀態，便顯得非 常重要。 201134089 【發明内容】 本發明内容之一目的是在提供一種軌對執運算放大 器，藉以使其轉導在共模輸入電壓變化的情況下，盡量維 持一定的狀態。 本發明内容之一技術樣態係關於一種軌對軌運算放大 器，其包令—第一差動輸入單元、一第二差動輸入單元、 一第一電晶體開關、一第一電流鏡電路、一第二電晶體開 關以及一第二電流鏡電路。第一差動輸入單元包含一第一 Φ 差動輸入對電路以及一第一尾端電流源。第二差動輸入單 元包含一第二差動輸入對電路以及一第二尾端電流源，其 中第一差動輸入對電路與第二差動輸入對電路互補地進行 操作。第一電晶體開關耦接第一尾端電流源，並於第一差 動輸入對電路操作於截止狀態時導通。第一電流鏡電路用 以於第一電晶體開關導通時，經由第一電晶體開關將第一 尾端電流源之電流鏡射至第二差動輸入單元。第二電晶體 開關耦接第二尾端電流源，並於第二差動輸入對電路操作 Φ 於截止狀態時導通。第二電流鏡電路用以於第二電晶體開 關導通時，經由第二電晶體開關將第二尾端電流源之電流 鏡射至第一差動輸入單元。 本發明内容之另一技術樣態係關於一種軌對軌運算放 大器，其包含一 N型差動輸入對電路、一第一尾端電流源、 一 N型電晶體、一 P型差動輸入對電路、一第二尾端電流 源、一 P型電晶體、一第一電流鏡電路以及一第二電流鏡 電路。第一尾端電流源耦接N型差動輸入對電路。N型電 晶體與N型差動輸入對電路並聯耦接，且串疊耦接第一尾 201134089 端電流源。P型差動輸入對電路與N型差動輸入對電路互 補地進行操作。第二尾端電流源耦接P型差動輸入對電 路。P型電晶體與P型差動輸入對電路並聯粞接，且串疊 耦接第二尾端電流源。第一電流鏡電路耦接於N型電晶體 和第二尾端電流源之間，並於N型電晶體導通時對第一尾 端電流源之電流進行鏡射，使得第一尾端電流源之電流疊 加於第二尾端電流源之電流。第二電流鏡電路耦接於P型 電晶體和第一尾端電流源之間，並於P型電晶體導通時對 第二尾端電流源之電流進行鏡射，使得第二尾端電流源之 電流疊加於第一尾端電流源之電流。 本發明内容之又一技術樣態係關於一種執對軌運算放 大器，其包含一 N型差動輸入對電路、一第一尾端電流源、 一 N型電晶體、一 P型電流鏡電路、一第二尾端電流源、 一 P型差動輸入對電路、一 P型電晶體、一 N型電流鏡電 路。第一尾端電流源串疊耦接N型差動輸入對電路。N型 電晶體與N型差動輸入對電路並聯地串疊耦接第一尾端電 流源。P型電流鏡電路之電流源端耦接N型電晶體。第二 尾端電流源耦接P型電流鏡電路之電流鏡射端。P型差動 輸入對電路串疊耦接第二尾端電流源。P型電晶體與P型 差動輸入對電路並聯地_疊耦接第二尾端電流源。N型電 流鏡電路之電流源端耦接P型電晶體，N型電流鏡電路之 電流鏡射端耦接第一尾端電流源。 根據本發明之技術内容，應用前述執對執運算放大器 不僅可以維持一定的輸出電流，使得轉導相對應地呈現一 定值，而且更可藉此穩定單位增益頻寬或頻率，並讓頻率 201134089 的補償達到最佳化β 【實施方式】When the transistor is operated complementarily with the P-type transistor, it usually lacks one of the supply of the muscles due to the fact that one of the N = transistor and the P-type transistor is turned off. As a result, the output current will change accordingly, and the transconductance of the corresponding output current will also change, due to the unity-gain frequency or soap level of the rose unit. The unity-gain bandwidth is a function of transduction and therefore affects the frequency compensation. For this reason, it is very important to prevent the current from being affected by the common-mode input voltage and to keep the output current as constant as possible. SUMMARY OF THE INVENTION One object of the present invention is to provide a rail-to-end operation amplifier that allows a transconductor to maintain a certain state as much as possible in the case of a common mode input voltage change. One aspect of the present invention relates to a rail-to-rail operational amplifier, which includes a first differential input unit, a second differential input unit, a first transistor switch, a first current mirror circuit, A second transistor switch and a second current mirror circuit. The first differential input unit includes a first Φ differential input pair circuit and a first tail current source. The second differential input unit includes a second differential input pair circuit and a second tail current source, wherein the first differential input pair circuit and the second differential input pair circuit operate complementarily. The first transistor switch is coupled to the first tail current source and is turned on when the first differential input operates in the off state. The first current mirror circuit is configured to mirror the current of the first tail current source to the second differential input unit via the first transistor switch when the first transistor switch is turned on. The second transistor switch is coupled to the second tail current source and is turned on when the second differential input operates the circuit Φ in the off state. The second current mirror circuit is configured to mirror the current of the second tail current source to the first differential input unit via the second transistor switch when the second transistor switch is turned on. Another aspect of the present invention relates to a rail-to-rail operational amplifier including an N-type differential input pair circuit, a first tail current source, an N-type transistor, and a P-type differential input pair. a circuit, a second tail current source, a P-type transistor, a first current mirror circuit, and a second current mirror circuit. The first tail current source is coupled to the N-type differential input pair circuit. The N-type transistor and the N-type differential input are coupled in parallel to the circuit, and are coupled in series to the first tail of the 201134089 terminal current source. The P-type differential input pair circuit and the N-type differential input pair circuit operate complementarily. The second tail current source is coupled to the P-type differential input pair circuit. The P-type transistor and the P-type differential input are connected in parallel to the circuit, and are coupled in series to the second tail current source. The first current mirror circuit is coupled between the N-type transistor and the second tail current source, and mirrors the current of the first tail current source when the N-type transistor is turned on, so that the first tail current source The current is superimposed on the current of the second tail current source. The second current mirror circuit is coupled between the P-type transistor and the first tail current source, and mirrors the current of the second tail current source when the P-type transistor is turned on, so that the second tail current source The current is superimposed on the current of the first tail current source. Yet another aspect of the present invention relates to a rail-operated operational amplifier including an N-type differential input pair circuit, a first tail current source, an N-type transistor, a P-type current mirror circuit, A second tail current source, a P-type differential input pair circuit, a P-type transistor, and an N-type current mirror circuit. The first tail current source is coupled in series with the N-type differential input pair circuit. The N-type transistor and the N-type differential input are coupled in parallel to the circuit in parallel with the first tail current source. The current source end of the P-type current mirror circuit is coupled to the N-type transistor. The second tail current source is coupled to the current mirror end of the P-type current mirror circuit. The P-type differential input pair circuit is coupled to the second tail current source. The P-type transistor and the P-type differential input pair circuit are connected in parallel to the second tail current source. The current source end of the N-type current mirror circuit is coupled to the P-type transistor, and the current mirror end of the N-type current mirror circuit is coupled to the first tail current source. According to the technical content of the present invention, the application of the aforementioned operational amplifier can not only maintain a certain output current, so that the transduction correspondingly exhibits a certain value, and can thereby stabilize the unity gain bandwidth or frequency, and let the frequency of 201134089 Compensation is optimized β [Embodiment]
需瞭解下列說明為提供不同的實施例，藉以實施本發 明的不同特徵。下列描述元件及配置的特定實施例係用以 簡化本發明說明，其當然僅為例示說明，而非用以限制。 此外，本發明說明可能在不同實施例重複編號及/或字母。 此重複使用為簡化及清楚的目的，並非指定其在討論的不 同實施例及/或結構間之關係。 第1圖係依照本發明一實施例繪示一種ΑΒ類軌對軌 (iaiMo-raii)運算放大器的示意圖。運算放大器1〇〇包含輸 入級、第一電晶體開關130、第二電晶體開關14〇、第一電 流鏡電路150以及第二電流鏡電路16〇 ,其中輸入級更包 3第一差動輸入單元110以及第二差動輸入單元12〇。 第一差動輸入單元110包含第一差動輸入對電路以及 第一尾端電流源(tail current) 114 ’其中第一差動輸入對電 路於本實施例中係為N型差動輸入對電路112,由NM〇s 電晶體Ml和M2所組成，並串疊耦接第一尾端電流源114。 第二差動輸入單元！20包含第二差動輪入對電路以及 電流源'…’其中第二差動輸人對電路於本實施 =係為p型差動輸入對電路122，自PM〇s電晶體切 4所組成’並串疊耦接第二尾端電流源。 N型差動輸人對電路112與p型差動輪人對電路⑵ 係由相同的共模（common-mode)輪入電壓VN和vp所控 制，使得N S電晶體和P㈣晶體相賴且地進行^ 201134089 _ °當共模輸入電壓VN和VP位於低位準狀態 Γ雷邀νΓ差動輸人對電路122相對應地操作；當共模輸 4 VP位於高位準狀態時，僅Ν型差動輸入對 中應地操作；而當共模輸入電麼VN和vp位於 中間位準狀態時，則 铪m則動輸入對電路112和P型差動 輸入對電路122會同時進行操作。 n认電曰曰體開㈣130輕接第一尾端電流源114,並於N ^ 认對電路112操作於截止狀n(eut_Gf⑽導通。在 施例中’第-電晶體開關13〇可為一綱電晶體 MN卜其閘_較電壓VL()W，其源_接第一尾端電 流源114和N型差動輸人對電路112，而與n型差動輸入 對^路112並聯輕接，並串疊輕接於第—尾端電流源ιΐ4。 此外’定電壓VLOW可由電流源12(12可由另外的電流鏡 電路產生）與電阻R2搭配操作而產生。 另外’第二電晶體關140搞接第二尾端電流源124, 並於p型差動輸入對料m操作於截止狀態㈣。酬導 通。在本實施例中，第二電晶體開關14〇可為一 ]3河〇8電 晶體MM，其閘_接定電壓VHIGH，其源_接第二尾 端電流源型差動輸入對電路122，而與p型差動 輸入對料122並聯耦接，並φ疊—第二尾端電⑽ m。此外’定電麗VHIGH可由電流源11(11可由另外的 電流鏡電路產生）與電阻R1搭配操作而產生。 第一電飢鏡電路=0係用以於第—電晶Μ關130導 通時’經由第一電晶體開關130將第一尾 ⑴之 電流鏡射至第二差動輸入單元120。具體而言，第一電流 201134089 鏡電路150耦接於NM〇s電晶體MN1和第二尾端電流源 124之間，並於電晶體河1^1導通時對第一尾端電流源^'4 之電流進行鏡射，使得第一尾端電流源1U之電流疊加於 第二尾端電流源124之電流。在本實施例中，第一電流鏡 電路150係為P型電流鏡電路，由pM〇s電晶體 * MP3所組成，且p型電流鏡電路中之電流源端（亦即以二極 體方式連接的電晶體MP2)係耦接於電晶體MN1的汲極， 而p型電流鏡電路中之電流鏡射端（亦即電晶體MP3)則耦 φ 接第二尾端電流源丨24。 另一方面’第二電流鏡電路160係用以於第二電晶體 開關140導通時，經由第二電晶體開關M〇將第二尾端電 流源124之電流鏡射至第一差動輸入單元110。具體而言， 第二電流鏡電路160耦接於PMOS電晶體MP1和第一尾端 電流源114之間，並於電晶體MP1導通時對第二尾端電流 源124之電流進行鏡射，使得第二尾端電流源124之電流 疊加於第一尾端電流源114之電流。在本實施例中，第二 • 電流鏡電路16〇係為N型電流鏡電路，由NMOS電晶體 MN2和MN3所組成’且n型電流鏡電路中之電流源端（亦 即以二極體方式連接的電晶體MN2)係耦接於電晶體MP1 的汲極，而N型電流鏡電路申之電流鏡射端（亦即電晶體 MN3)則耦接第一尾端電流源114。 在操作上，當共模輸入電壓VN和VP為極高電壓(接 近電壓源VDD)時，N型差動輸入對電路112中的電晶體 Ml和M2於飽和狀態下進行操作，此時由於電晶體mN1 的閘極電壓VLOW與源極電壓NTAIL差（VGS)不足以使電 201134089 晶體MN1導通，因此電晶體MN1仍是關閉的狀態。相反 地，P型差動輸入對電路122中的電晶體M3和M4進入截 止狀態操作，使得電晶體MP1的源極電壓PTAIL拉升，進 而使得電晶體MP1的閘極電壓VHIGH與源極電壓PTAIL 差（VGS)足夠使電晶體MP1導通。因此，第二尾端電流源 124的電流會轉而流向電晶體MP1，並經由電晶體MN2和 MN3所組成的電流鏡電路鏡射，而與第一尾端電流源114 之電流疊加，使得流經第一差動輸入單元110的總電流成 為第二尾端電流源124與第一尾端電流源114的加總電 流。如此一來，即便在共模輸入電壓VN和VP為極高電壓 的情形下，仍然可以利用上述電流補償的方式，將第二差 動輸入單元120中的電流補償至第一差動輸入單元110, 使得輸入級的電流並未實質減少。 另一方面，當共模輸入電壓VN和VP為極低電壓（接 近電壓VSS)時，P型差動輸入對電路122中的電晶體M3 和M4於飽和狀態下進行操作，此時由於電晶體MP1的閘 極電壓VHIGH與源極電壓PTAIL差（VGS)不足以使電晶體 MP1導通，因此電晶體MP1仍是關閉的狀態。相反地，N 型差動輸入對電路112中的電晶體Ml和M2進入截止狀態 操作，使得電晶體MN1的源極電壓NTAIL拉升，進而使 得電晶體MN1的閘極電壓VLOW與源極電壓NTAIL差 (VGS)足夠使電晶體MN1導通。因此，第一尾端電流源114 的電流會形同由電晶體MN1流出，並經由電晶體MP2和 MP3所組成的電流鏡電路鏡射，而與第二尾端電流源124 之電流疊加，使得流經第二差動輸入單元120的總電流成 201134089 為第一尾端電流源114與第二尾端電流源124的加總電 流。如此一來’即便在共模輸入電壓VN和VP為極低電壓 的情形下，仍然可以利用上述電流補償的方式，將第一差 動輸入單元110中的電流補償至第二差動輸入單元120, 使得輸入級的電流並未實質減少。 • 上述電晶體MN1的閘極電壓VLOW和電晶體MP1的 閘極電壓VHIGH均具一定值，且可依照實際狀況調整為輸 入級中的第一差動輸入單元110和第二差動輸入單元 φ 120，其各別在接收極高電壓或極低電壓而即將進入截止狀 態時的電壓值。 由於在一般軌對軌運算放大器電路中’輸入級的N型 和P型差動輸入對電路會根據共模輸入電壓具有極高或極 低值而互補地進行操作，因此當其中一者關閉時，其所對 應的電流也會隨之消失，使得輸入級缺少一路的電流供 應’進而影響相對應於電流的轉導(transconductance)。為 此，採用本發明上述實施例，不僅可避免輸入級的電流受 φ 到共模輸入電壓的影響，並維持一定值，使得相對應於電 流的轉導呈現穩定的狀態，進而讓隨著轉導變化的放大器 的單位增益頻率（unity-gain frequency)或是單位增益頻寬 (unity-gain bandwidth)呈現穩定，也讓頻率的補償達到最佳 化0 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明，任何本領域具通常知識者，在不脫離本發明之 精神和範圍内，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 201134089 【圖式簡單說明】 第1圖係依照本發明一實施例繪示一種AB類軌對軌 運算放大器的示意圖。 【主要元件符號說明】 100 :運算放大器 110 :第一差動輸入單元 112 : N型差動輸入對電路 114 :第一尾端電流源 120 :第二差動輸入單元 122 : P型差動輸入對電路 124 :第二尾端電流源 130 :第一電晶體開關 140 :第二電晶體開關 150 :第一電流鏡電路 160 :第二電流鏡電路 12It is to be understood that the following description is provided to provide a different embodiment of the various features of the invention. The following description of the specific embodiments of the present invention is intended to be illustrative of the invention and is not intended to be limiting. Furthermore, the description of the invention may repeat the numbering and/or the letters in different embodiments. This repetitive use is for the purpose of simplicity and clarity and is not intended to identify the various embodiments and/ FIG. 1 is a schematic diagram showing a 轨i-track-to-rail (iaiMo-raii) operational amplifier according to an embodiment of the invention. The operational amplifier 1A includes an input stage, a first transistor switch 130, a second transistor switch 14A, a first current mirror circuit 150, and a second current mirror circuit 16A, wherein the input stage further includes a first differential input The unit 110 and the second differential input unit 12A. The first differential input unit 110 includes a first differential input pair circuit and a first tail current source 114 ' wherein the first differential input pair circuit is an N-type differential input pair circuit in this embodiment 112, consisting of NM〇s transistors M1 and M2, and coupled in series to the first tail current source 114. Second differential input unit! 20 includes a second differential wheel-in pair circuit and a current source '...' wherein the second differential input pair is in the present embodiment = is a p-type differential input pair circuit 122, which consists of a PM 〇s transistor cut 4 The second tail current source is coupled in series. The N-type differential input pair circuit 112 and the p-type differential wheel pair circuit (2) are controlled by the same common-mode wheel-in voltages VN and vp, so that the NS transistor and the P(tetra) crystal are placed in parallel ^ 201134089 _ ° When the common mode input voltages VN and VP are in the low level state, the 邀 邀 Γ differential input operates corresponding to the circuit 122; when the common mode input 4 VP is in the high level state, only the Ν type differential input The operation is performed in the middle; and when the common mode input voltages VN and vp are in the intermediate level state, then the 输入m dynamic input pair circuit 112 and the P type differential input pair circuit 122 operate simultaneously. The n-th power-on body (four) 130 is connected to the first-end current source 114, and operates in the N-type circuit 112 in the cut-off state n (eut_Gf(10) is turned on. In the embodiment, the 'first-transistor switch 13' can be one. The transistor MN is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Connected and cascaded to the first-end current source ιΐ4. In addition, the constant voltage VLOW can be generated by the current source 12 (12 can be generated by another current mirror circuit) and the resistor R2. In addition, the 'second transistor off The second transistor current source 124 is connected to the second tail current source 124, and operates on the p-type differential input material m in the off state (4). In this embodiment, the second transistor switch 14〇 can be a 8 transistor MM, its gate_stationary voltage VHIGH, its source_ is connected to the second tail current source type differential input pair circuit 122, and is coupled in parallel with the p-type differential input material 122, and φ stack- The two end terminals are electrically (10) m. In addition, the 'definite current VHIGH can be generated by the current source 11 (11 can be generated by another current mirror circuit) in combination with the resistor R1. The electric hunger circuit =0 is used to mirror the current of the first tail (1) to the second differential input unit 120 via the first transistor switch 130 when the first transistor switch 130 is turned on. Specifically, A current 201134089 mirror circuit 150 is coupled between the NM〇s transistor MN1 and the second tail current source 124, and mirrors the current of the first tail current source ^'4 when the transistor river 1 is turned on. The current is caused by the current of the first tail current source 1U being superimposed on the current of the second tail current source 124. In this embodiment, the first current mirror circuit 150 is a P-type current mirror circuit, which is composed of a pM〇s transistor. * MP3, and the current source terminal (that is, the transistor MP2 connected in a diode mode) in the p-type current mirror circuit is coupled to the drain of the transistor MN1, and the current in the p-type current mirror circuit The mirror end (ie, the transistor MP3) is coupled to the second tail current source 丨24. On the other hand, the second current mirror circuit 160 is configured to be used when the second transistor switch 140 is turned on. The crystal switch M〇 mirrors the current of the second tail current source 124 to the first differential input unit 110. Specifically, the second The flow mirror circuit 160 is coupled between the PMOS transistor MP1 and the first tail current source 114, and mirrors the current of the second tail current source 124 when the transistor MP1 is turned on, so that the second tail current source The current of 124 is superimposed on the current of the first tail current source 114. In this embodiment, the second current mirror circuit 16 is an N-type current mirror circuit composed of NMOS transistors MN2 and MN3 'and n-type The current source terminal (that is, the diode MN2 connected in a diode manner) in the current mirror circuit is coupled to the drain of the transistor MP1, and the N-type current mirror circuit is applied to the current mirror end (ie, the transistor). MN3) is coupled to the first tail current source 114. In operation, when the common mode input voltages VN and VP are extremely high voltages (close to the voltage source VDD), the N-type differential input operates in the saturation state of the transistors M1 and M2 in the circuit 112, at this time due to the power The gate voltage VLOW of the crystal mN1 is not sufficiently different from the source voltage NTAIL (VGS) to turn on the electric 201134089 crystal MN1, and thus the transistor MN1 is still in a closed state. Conversely, the transistors M3 and M4 in the P-type differential input pair circuit 122 enter an off-state operation, so that the source voltage PTAIL of the transistor MP1 is pulled up, thereby causing the gate voltage VHIGH and the source voltage PTAIL of the transistor MP1. The difference (VGS) is sufficient to turn on the transistor MP1. Therefore, the current of the second tail current source 124 will flow to the transistor MP1 and be mirrored by the current mirror circuit composed of the transistors MN2 and MN3, and superimposed with the current of the first tail current source 114, so that the flow The total current through the first differential input unit 110 becomes the summed current of the second tail current source 124 and the first tail current source 114. In this way, even in the case where the common mode input voltages VN and VP are extremely high voltages, the current in the second differential input unit 120 can be compensated to the first differential input unit 110 by using the current compensation method described above. , so that the current of the input stage is not substantially reduced. On the other hand, when the common mode input voltages VN and VP are extremely low voltages (close to voltage VSS), the P-type differential input operates in the saturation state of the transistors M3 and M4 in the circuit 122, at this time due to the transistor The difference between the gate voltage VHIGH of the MP1 and the source voltage PTAIL (VGS) is insufficient to turn on the transistor MP1, and thus the transistor MP1 is still in a closed state. Conversely, the transistors M1 and M2 in the N-type differential input pair circuit 112 enter an off-state operation, causing the source voltage NTAIL of the transistor MN1 to rise, thereby causing the gate voltage VLOW and the source voltage NTAIL of the transistor MN1. The difference (VGS) is sufficient to turn on the transistor MN1. Therefore, the current of the first tail current source 114 is similarly flowed out by the transistor MN1, and is mirrored by the current mirror circuit composed of the transistors MP2 and MP3, and superimposed with the current of the second tail current source 124, so that The total current flowing through the second differential input unit 120 is 201134089, which is the summing current of the first tail current source 114 and the second tail current source 124. In this way, even in the case where the common mode input voltages VN and VP are extremely low voltages, the current in the first differential input unit 110 can be compensated to the second differential input unit 120 by the above-described current compensation. , so that the current of the input stage is not substantially reduced. • The gate voltage VLOW of the transistor MN1 and the gate voltage VHIGH of the transistor MP1 have a certain value, and can be adjusted to the first differential input unit 110 and the second differential input unit φ in the input stage according to actual conditions. 120, the voltage value of each of which is about to enter an off state when receiving a very high voltage or a very low voltage. Since the N-type and P-type differential input pair circuits of the input stage in the general rail-to-rail operational amplifier circuit are complementarily operated according to the common mode input voltage having a very high or low value, when one of them is turned off The corresponding current will also disappear, so that the input stage lacks a current supply 'and thus affects the transconductance corresponding to the current. Therefore, according to the above embodiment of the present invention, not only the current of the input stage is prevented from being affected by the common mode input voltage, but also a certain value is maintained, so that the transduction corresponding to the current exhibits a stable state, thereby allowing the turn The unity gain frequency or the unity-gain bandwidth of the pilot-changing amplifier is stable, and the frequency compensation is optimized. Although the present invention has been disclosed in the above embodiments, It is not intended to limit the scope of the invention, and the scope of the present invention is intended to be limited by the scope of the invention. The definition is final. 201134089 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing an AB-type rail-to-rail operational amplifier according to an embodiment of the invention. [Main component symbol description] 100: Operational amplifier 110: First differential input unit 112: N-type differential input pair circuit 114: First tail current source 120: Second differential input unit 122: P-type differential input Pair circuit 124: second tail current source 130: first transistor switch 140: second transistor switch 150: first current mirror circuit 160: second current mirror circuit 12