201131359 六、發明說明： 【發明領域】 本發明-般係關於固態儲存展置(SSD)中的資料管理，且體 而言，侧於㈣SSD中的資術轉與抹除程序的方法與設備。 【先前技術】 口 i儲存祕利用電子電路(―般係積體電路)*非習知磁 如光碟或，），儲存資料的非揮發記憶體。如 I置的SSD目前正革命性地改變資料儲存領域。相 ^於省知儲存裝置’此等裝置因為缺少移動元件而較穩定，且 相比，此等裝置因提供更大的頻寬、更省電的 力此以及更好的隨機1/0(輸入/輸出）效能。 在SSD巾，儲存器有許多儲存區或「儲存塊」，每區 ^-組可寫人資料的儲存位置。以下將參照nand為主的 Ϊ置來描述SSD的許多運作特性。'然而，熟此技藝者當知， 類似原則亦義於其他_的SSD。舉_言，快閃記 =許多包含減寫人位置的儲存塊組合而成，稱作「頁η 十、閃頁的大小係4 kB ’且-般快閃塊係由64個快閃資料頁組二 而成(因此為256 kB)。讀取與寫人作業係逐f運作 ^ f僅可以逐塊運作。僅可在成功抹除_塊後才能寫入資^。 自快閃胞將—個資料頁讀進快閃晶粒中的資料缓衝器—般 到25微秒。將資料頁寫入快閃胞需要約200微秒，而抹二 :塊士常需要約2毫秒。由於抹除-個儲存塊所需的時間 或舄入一個資料頁的時間來的長，因此會利用稱為「寫入 到位」的寫入方案來改進寫入的生產率與延遲。使用此方案時，201131359 VI. INSTRUCTIONS: FIELD OF THE INVENTION The present invention relates generally to data management in solid state storage deployment (SSD) and, in general, to methods and apparatus for asset transfer and erasure procedures in (4) SSDs. [Prior Art] Port i storage secret uses electronic circuits ("general integrated circuit" * non-formal magnetic such as optical disc or,), non-volatile memory for storing data. SSDs such as I are currently revolutionizing the field of data storage. Compared to known storage devices, these devices are more stable due to the lack of moving components, and compared to these devices due to the provision of greater bandwidth, more power saving, and better random 1/0 (input) /output) performance. In the SSD towel, the storage has a lot of storage areas or "storage blocks", and each area ^-group can store the storage location of the person data. A number of operational characteristics of the SSD will be described below with reference to the nand-based device. 'However, those skilled in the art know that similar principles are also valid for other SSDs. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Two (so 256 kB). The reading and writing operations are performed by f. ^ f can only be operated block by block. Only after successfully erasing the _ block can you write the ^^. The data page is read into the data buffer in the flash die—up to 25 microseconds. It takes about 200 microseconds to write the data page to the fast flash, and wipe 2: the block often takes about 2 milliseconds. - The time required to store a block or the length of time it takes to break into a data page, so a write scheme called "write in place" is used to improve the productivity and latency of the write. When using this scenario,
4 S 201131359 已儲存的資料頁不會到位地更新於快閃儲存器，反而是將已更 新的資料頁寫入另-個可用的快閃頁，並在儲存為每個資料頁 份的元資料中’設定-個有效性旗幟’以將相關的舊快 閃頁& §己為無效。 寫入非到位方案以及其他快閃儲存的特徵需要運作某些 「清掃」作業，以作快閃儲存器的内部管理。舉例而言，在； 新資料頁並讓舊資料頁無效時，需要後續程序消除益二資料， 並釋放儲存位置給新輸入資料。此内部管理程 為「 相⑽」。垃圾收集程序包含選擇=用的 復所有仍有效的資料ό有效資料頁會 t ==_含的無效資料頁的數量選擇儲存塊。 部'二抹除ί可當作其他内部管理程序的一 程序的1Φ y 匕3在固悲儲存器内移動資料。内部管理 閃=體此程序解決快 不快閃塊間平均分佈寫入抹除週期，= 根據寫=週=長=命。，言，耗損平均功能 及在快閃記憶體内敕私旱擇新貝料應寫入的儲存塊，以 數的儲存塊，並平贿时料’以職具餘低週期計 閃控制器)運= :理：業:般係由專屬控制設備(稱為快 、卫制為係伴隨快閃儲存器。快閃控制器— 201131359 般係管理快閃記憶體内的資料、控制所有内部管理作業、r 維護控制器記憶體内的位址元資料，以追蹤快閃儲存哭中資料 的位置。具體而言，快閃控制器執行一中間軟體°層（^二 iLBA-PBA(邏輯塊位址-實體塊位址）」映射)(亦稱為「快 譯層(FTL)」或「LPN-FPN(邏輯頁碼-快閃頁碼)位址映射」）。 此層以位址映射的方式維護元資料，將與上層(例如儲存系」統中 的檔案系統或主機)的輸入資料塊相關聯的邏輯位址，映射到快 閃上的實體位址(快閃頁碼)。此軟體層隱藏快閃抹除前寫入的複 雜性，並支援透明資料寫入與更新而無需抹除作業的介入。 SSD中所運作的内部管理功能導致所謂的「寫入放大」。寫 入放大的發生是因為資料在儲存器内部移動，導致資料寫」入作 業的數量比SSD所收到的原始資料寫入請求的數量來的大。寫 入放大係限制固態儲存裝置的隨機寫入效能與寫入持久壽命的 其中一個重要課題。另一個重要課題是錯誤效能。錯誤校正戌C) 編碼在SSD中係在寫人單元層增加冗餘的方式運作。具體而 言’ EC碼係替寫入每一頁的輸入資料或一頁内的每個區段的輸 入=貝料進行運算’且此EC碼係與該輸入資料一同紀錄於該頁或 該區段内。此編碼得以在各個資料頁内從錯誤作回復。然而， 固態儲存系統可_額外的EC編碼保護裝置層的失效。此編碼 係透過以RAID (獨立裝置的冗餘陣列）陣列的方式管理許多裝 置的集合’通ί HDD儲存系統皆係使用此方式。利用類似 保護的SSD系、統’係揭露於美國專利申請公開號讥 2008/0320214A1 „ 以 及 http://www.storagenewsletter.com/news/flash/sandforce-ssd-contro4 S 201131359 The saved data page will not be updated in the flash memory. Instead, the updated data page will be written to another available flash page and stored as metadata for each data page. In the 'Settings - Validity Flag' to invalidate the relevant old flash page & §. Features written to non-placement schemes and other flash storages require the operation of certain "cleanup" jobs for internal management of the flash memory. For example, when a new data page is used and the old data page is invalidated, a follow-up procedure is required to eliminate the benefit data and release the storage location for the new input data. This internal management process is "phase (10)". The garbage collector includes the selection = used. All the still valid data. The valid data page will t ==_ the number of invalid data pages included to select the storage block. The section '2 erasing ί can be used as a program of other internal management programs. 1Φ y 匕3 moves data in the solid memory. Internal management Flash = body This program solves fast Uneven flash block average distribution write erase cycle, = according to write = week = long = life. , words, the average function of wear and loss, and the storage block that should be written in the fresh memory of the flash memory, the number of storage blocks, and the time of the bribe = : Reason: Industry: The general control equipment (called fast, Wei system is accompanied by flash memory. Flash controller - 201131359) manages the data in the flash memory, controls all internal management operations, r Maintain the location metadata of the controller memory to track the location of the data stored in the flash memory. Specifically, the flash controller performs an intermediate software layer (^2 iLBA-PBA (Logical Block Address - Physical block address) mapping (also known as "Fast Translation Layer (FTL)" or "LPN-FPN (Logical Page Number - Flash Page Number) Address Mapping"). This layer maintains metadata in the form of address mapping. Map the logical address associated with the input block of the upper layer (for example, the file system or host in the storage system) to the physical address (flash page number) on the flash. This soft layer hides the flash eraser. In addition to the complexity of pre-write, and support transparent data writing and updating without the need to erase the job Intervention. The internal management functions operated in the SSD cause so-called "write amplification." Write amplification occurs because the data moves inside the memory, causing the number of data writes to be entered into the job than the original data received by the SSD. The number of incoming requests is large. Write amplification is one of the important issues that limit the random write performance and write endurance of solid-state storage devices. Another important issue is error performance. Error correction 戌C) coding in SSD It works in a way that adds redundancy to the write unit layer. Specifically, the 'EC code is used to calculate the input data of each page written in each page or the input of each segment in a page' and the EC code is recorded on the page or the area together with the input data. Within the paragraph. This code is able to reply from the error in each data page. However, the solid state storage system can _ additional EC code protection device layer failure. This code manages the collection of many devices by means of a RAID (Redundant Array of Independent Devices) array. This is the way the HDD storage system is used. A similarly protected SSD system is disclosed in U.S. Patent Application Publication No. 2008/0320214A1 and http://www.storagenewsletter.com/news/flash/sandforce-ssd-contro
Uers中的「啟動Sandf〇rce的SSD控制器」。在一情況下，儲存 201131359 糸統可使❹個SSD，每個SSD與管理其本身的邏輯儲存的控 制器-同運作，如上述。SSD的組合可接著簡似謂〇陣列 的方式作較高層的管理。此系統的基本作業原騎參照圖 陆圓夫七姑七十[。 【發明内容】 圖i係-範例類似RAID α SSD為主的儲存祕的方塊 圖。在此系統中，多個SSD 2在儲存控制器3下運作，負責處 理來自主機的讀/寫請求。每個SSD2管理其内部儲存器4中的 資料’已如上述一般而言’儲存器4可包含 個 道，每個通道具有-或多個晶片或許多晶片封裝，其中每= 片可包含一或多個固態儲存晶粒。在儲存控制器3申，主機[BA (邏輯塊概这間係關輯㈣方式作分區，且每轉輯塊的一 區段會配給各個SSD 2。此階段加增冗餘，進而得以增加^仍 同位檢查。具體而言，儲存控器3 EC對每個輸入主機^料塊(對 應-既定主機（「全局」）LBA)進行編碼，且產生的同位 檢查會新增到域㈣塊。編有同位檢查的_塊接著被控制 器3區分為「單元資料塊」。每個單元資料塊係在一個配置^元 LBA(uLBA)下供應給各個SSd 2，作儲存之用。SSD組合中， 全局LBA(gLBA)到uLBA的映射係由控制器3紀錄於 gLBA-uLBA映射表。每個SSD儲存其個別的單元資料塊/，'並 像在常一般將實體儲存位置紀錄在ulba_pba映射表。此程序 的結果使RAID碼字分佈在SSD 2陣列間，如圖中虛線區^所 示。這提供了另一層的EC編碼，以避免SSD層的失效。在每 個SSD2内，本區控制器運作儲存器4的内部管理，已如上述， 但在此架構中，此功能及uLBA到PBa隨後的重新映射對^存"Start Sand controller for Sandf〇rce" in Uers. In one case, storing 201131359 ❹ can make one SSD, each SSD operating with a controller that manages its own logical storage, as described above. The combination of SSDs can then be managed at a higher level in a manner similar to the array. The basic operation of this system is the original riding reference map Lu Yuanfu seven auspicious seven [. SUMMARY OF THE INVENTION Figure i is a block diagram similar to a RAID α SSD-based storage secret. In this system, a plurality of SSDs 2 operate under the storage controller 3 and are responsible for processing read/write requests from the host. Each SSD 2 manages the data in its internal storage 4 'as has been generally described above'. The storage 4 may contain tracks, each channel having - or multiple wafers or a plurality of wafer packages, each of which may contain one or Multiple solid state storage grains. In the storage controller 3, the host [BA (Logical Blocks) is divided into sections, and a section of each block is allocated to each SSD 2. This stage adds redundancy, which is increased by ^ The parity check is still performed. Specifically, the storage controller 3 EC encodes each input host block (corresponding-established host ("global") LBA), and the generated parity check is added to the domain (four) block. The _ block with parity check is then divided into "unit data blocks" by the controller 3. Each unit data block is supplied to each SSd 2 under a configuration element LBA (uLBA) for storage. In the SSD combination, The global LBA (gLBA) to uLBA mapping is recorded by the controller 3 in the gLBA-uLBA mapping table. Each SSD stores its individual unit data block /, 'and records the physical storage location in the ulba_pba mapping table as usual. The result of this program is that the RAID codewords are distributed between the SSD 2 arrays as shown by the dotted area in the figure. This provides another layer of EC coding to avoid failure of the SSD layer. Within each SSD2, the local area controller The internal management of the operational storage 4 has been as described above, but in this architecture , this function and subsequent remapping of uLBA to PBa
7 S 201131359 控制器3而言是透明的。 多個=Γ謂的「外部咖」組態，其中咖碼字橫跨 外，本紐跨多健㈣。除了外部或#代隨〕以 :於==利用一個「内部咖」系統。内部_係實 區，、日卷制内。在此控制器中，麗空間會作邏輯性的分 =2個邏輯塊的1段會分配給整個儲存空財不同的子 上二新在增子，r同位檢查，以將内 RAm玉-/ 匚並刀佈在子早疋的集合中。具體而言，内部 健分為子單元㈣塊，且每鮮單元資料塊在各個 子=的位址空間中配有一個子單元服(suLba)。腿到 suLB，的映射係由控制器紀錄在lba_suLba位址映射中。每 ，子單元雜塊接著_存麻於實_存位置的各個儲存子 早凡’其位置係紀錄在該單元的suLBA_pBA映射中。此程序提 供EC編碼’以避免SSD中子單元層的失效。如外部RAE)系 統’控制器在每個儲存子單元内獨立運作内部管理(垃圾收集、 耗損平均等），使此功能與suLBA到pBA隨後的重新映射得以 在比RAH)編碼的邏輯塊層更低階的一層運作。 :本發明之一面向提供固態儲存裝置的控制設備，其中固態 儲存盗包含可抹除塊，每個可抹除塊包含複數個資料寫入位 置。控制設備包含記憶體與控制邏輯，適合運作： ^將輸入資料儲存在資料寫入位置的連續群組，每個群組包 3寫入位置，係位於固態儲存器的複數個邏輯子區中每個子區 中的一組可抹除塊内； 對輸入貝料編錯誤校正碼，使每個群組包含該群組中該輸 201131359 入資料的錯誤校正碼； 在記憶體中維護元資料，該元資料表示輸入資料在固態儲 存器中的位置； 心 維護儲存於每個資料寫入位置的資料的有效性表示；以及 在抹除一儲存塊前，先自每個群組回復有效輸入資料，該 群組包含該資料塊的寫入位置，並將回復的資料重新儲存為^ 因此，在本發明之實施例中，控制設備所管理的儲存空間 被邏輯性地區分成複數個邏輯子區，而輸入資料會被寫入 入，置的許多群組，此等群組係分佈在此等邏輯子區中。具體 而言>’在每個邏輯子區中，每個群組包含一或多個寫入位^， 係在》亥子區的組(一或多個)可抹除塊。本發明替每個群組中 輸入貝料運算一 Ec碼，並替該輸入資料將該碼儲存於群組中、。 再者本發明採用儲存塊抹除程序，以替每個群組回復有效資 ^田备要抹除儲存塊時，例如在垃圾收集或其他内部管理功 =期間’本發明會在抹除—儲存塊前，先自包含該儲存塊中的 二4置的4群組或母個群組回復有效資料。如此回復的有效 =入f料接著在編有新Ec碼的群組巾，錄贿為新輸入資 二=此，本發明之實施例提供另—層的Ec編碼(即在類似先 :=之頁内編碼的寫入位置内所運作的任何習知ec編碼之 ’、同時允許儲存器整體運作内部管理功能。因此，不同於類 =上述RAID系統係實施於LBA到pBA映射之上額外的此 於實卿ΒΑ)層，而不是邏輯塊(lba)層，且整個 ▲於内部官理目的作整體管理。透過在實體塊層運作 扁碼以及主要内部㈣功能，本發明之實施_高效能效率 201131359 的方法避免儲存子區的失效。且辦而_ 序之間的共同作用提供較古的;’EC編碼與内部管理程 能。舉例而> 太心/円的錯决权正率，並大量改善整體效 月匕舉例而δ本發明能改善錯誤 在:加寫入放大與降低持久性等方= 備在固態齡似巾提實财㈣的控制設 輸入二=:r::::r碼(其中編碼程序的 非系統性編碼(其中編碼一曰以取得輸出碼字)或 字情施。細，理相^序;料會由編碼嵌於輸出碼 輯在每個群組中所儲存…用系統性編碼，利用控制邏 的輸入炱料中增加該輸入資料的EC碼。 頁：儲=入位置可為快閃記憶體裝置中的快閃 存器中的任-區域、中資料可寫入整個儲 儲存物品，從單一物σ ^ 般可包含以任何方式組態的 般的咖具^數或晶粒)到多組物品。然而，一 站，係包含-i多，每個通道提供一儲存庫或儲存 多個固態晶粒。基於Eit曰曰片的多個封裝’每個封裝具有一或 區，可為整體儲存區、柄目的在可用儲存器中所作的邏輯分 具有複數_存通道，^組° ’在_儲存裳置 中每個單元一般可包含:::通=有：組固態儲存單元(其 區）的實施例中，每個3、裝、曰曰片、晶粒或任何其他储存 (―妒 母们璉輯子區在各通道中可包含一植單 個除非另有說明，在此所指的物品 :: 個物。口 )。或者’舉例而言’每個邏輯子區可包含個別响^ 201131359 元0 基於EC編碼目的，輸入資料係儲存於寫入位置的許多群 組’其中每個群組在每個邏輯子區中包含一或多個寫入位置， 係位於該子區的一組可抹除塊中。在較佳實施例中，一群組包 含複數個寫入資料’位於每個子區的每個儲存塊中，每個儲存 塊内的寫入位置係連續的（即，具有連續的實體位置）。一般而 言，在任一子區中，—群組的寫入位置組合可包含大於或小於 一可抹除塊内寫入位置的數量。然而，為了實作方便，每個子 區中寫入位置的數量較佳為一儲存塊内寫入位置的數量的積分 因數或倍數。在每個子區卜群組的寫人位置數量係小於儲存 塊大小的情況’-個以上的群組可分享相觸儲存塊。在此情 若在—邏輯子區中分享-朗儲存塊的任一群組亦在每 個邏輯子區中分享—共同儲存塊，即可簡化内部管理作業。 群5群Ϊ中輸人資料的EC碼係與該輸人資料— 丨T存在該群財。_， 於每個群組的寫入位置_从户J群·入貝枓儲存 入資料運算-個暫時1個連，，階段，本發明會替該輸 時EC碼可在需要的日1 純正碼，並將之儲存於該群組。此暫 設備可有效部分完成轉組。再者，控制 存器内，糾在f源失效^暫時錯雜正碼儲存於固態儲 儲存子區同時失效。以保存暫時碼。藉此避免電源與 本發明之第二^ 置以及本發明之第―D係提供包含111態料it的HI態儲存裝 面向的控制設備’其儲存器包含可抹除 201131359 塊’每個可抹除塊包含一組資料寫入位置。 本發明之第三面提供控制固態儲存裝置的方法，其中固態 儲存器包含可抹除塊，每個可抹除塊包含複數個資料寫入位 置。本方法包含： 在資料寫入位置的連續群組中儲存輸入資料，每個群組包 s寫入位置，係位於固態儲存器的複數個邏輯子區的每個子區 中的一組可抹除塊内； 將輸入資料編有錯誤校正碼，使每個群組包含該群組中該 輸入資料的錯誤校正碼； / ▲在固態儲存裝置的記憶體中維護元資料，該元資料表示固 態儲存器中輸入資料的位置； 維護每個資料寫入位置中所儲存的資料的有效表示；以及 在抹除-儲存塊前，先自該每個群_復有效輸入資料， 為存塊的寫入位置，並將回復後的資料重新儲存 導致電 發明之第二面向的方法。熟此技藝者當知，1電腦- 般的使用，其包含具有實 狀 理功能的任何裝置、構件或系 枓處 式可具右—i ,、—·財貝加本發明的電腦程 ^發明亦提供電職式’其包含電腦程式碼手段， 式可具有一個獨立 —只娜个I明的電用 :提供r實施丄 二表二= 語言、代碼錢釋及/或⑼難為成另一 12 201131359 【實施方式】 圖2係實施本發明的範例挪5的方塊圖， 所述之資料管理作業所涉及社要元件。哪5具扣綠3 益6與控制設備(-般係以7表示）。在此範例中 6子 含:個儲存通道Ch⑴到Ch⑻，每個通道提供許多 的-個儲存庫8，即快閃儲存晶粒9。每個 :曰曰粒組9 -般可設置於-或多個晶片或晶片封震， 層資料胞)晶粒、ML。(多層資料胞)晶:、2 = 者°舉_言一或多個通道可提供M =餘^ 道可提供SLC儲存。 ㈣❿剩餘的通 輯：: = ==型態的_ _ 11、以及負責求的讀/寫_)介面 ^ i, ；〇：ΓΓί^ 料的讀寫以回應收到的請求、並^閃5的作業的二: 部管理功能。快閃控制写10亦齡=閃議6的所有内 施於硬體、軟體或其結合°者。1G的㈣邏輯可實 部分由軟體實施，其軟 A j ’控制邏輯可完全或 功能。孰士姑蓺土：制设備7的處理器運作所述 編碼/解碼功能HI自在此的描述中了解適用的軟體。e c 受快閃控制、gb硬接線邏輯電路實施，其電路運作-般係 設備7;包二’熟此技藝者當知適用的電路。控制 詳述。制111G運作中許多元資料的儲存，如下 〜旦 I可包含一或多個記憶體元件，其可包含 201131359 態隨機存取記 類型的雜體，包含例如SDRAM(同步動 或由較高階的控制器作其接/、主^通机負責讀/寫請求、 複數個襄置的^機二7 ’其南階㈣11負責儲存系統+ 陣列的嗜=求。舉例而言’裝置5可形成類似励 抑，其中儲存控繼管理多個咖，如 不。，此，與輸入讀/寫請求中所指定的資料相關聯的、羅輯 ==:機)位址空間、或某些邏輯‘== 1間此等位址爾後將稱作LBA。 而11 起始LBA與清求大小的資料寫入請求，透過R/W介 非同步地料蝴設備7。在寫人 . f運作一層比編碼。第一個EC編碼層（爾後稱作「C1編 =位於寫人單福的習知編碼。隨著輸人資料被寫人儲存器6 的各個快閃頁，EC編碼會對輸人t料進行運作，而結果碼^ 碼)將成為該頁所儲存的元資料的一部分。此元資料亦包 無效(αΗ)旗幟型態的有效性標示符。資料頁的PI旗職係快閃 控，器10正常控制作業的—部分’若基於某些原因，該頁中 的資料被視為無效時(例如基於資料更新，如下詳述），則可由 ，制器設定此旗幟。資料頁元資料一般包含壞頁(ΒΡ)旗幟， 若一資料頁被認定為無法使用時(例如顯示太多C1錯誤），快 閃控制斋10弓設定此旗幡。此程序亦係以快閃控制器1〇正 常控制功能的一部份運作。 201131359 快閃控制器10所運作 _ 編碼。實施C2編碼時，SSD 一 θ EC編碼爾後將稱為「C2」 子區對應』個通道組合上中固邏輯 入資料塊的串流寫人快閃頁的連續群透過將輸 施例中，每個群組的資^ ' 式運作。在此實 ^ 貝科頁了分佈於儲存器0的所有遴鈸； 每條資料頁-般包含預定數量料頁。 頁），位於通道儲存區8的一或個決 由、—、只6八的 儲存區8中具有獨特的頁心為^^塊各中身料頁在 頁的PBA。 為了方便，條ID可為條中第一 輸入資料的儲存係透過將資料寫入每個步距， c2 冗餘。圖3描述目前有效步距的寫入程序。 頁中(Qf)中）的-組資料頁係保留給該步距的C2碼。ίΡ ^ 於:既定步距中的輸人資料而言，快閃控㈣ig會運算該輸 入資料的EC碼’並將此C2竭儲存於該步距的最後一頁中。 C2編碼所制的特定EC演算法並非本發明之重點。缺而， 在此範例中，C2碼係假設為X〇R同位檢查碼。（在此可使用 的另-個C2編碼系統係揭露於與此案—同中請的歐洲專利 申請案，其f請人編號為⑽⑽㈣㈣，相_容包含在此 供參考）。在該系統中’加人上述步距的C2碼包含複數個Ο 碼字的集體同位檢查碼，散佈在儲存子區8中。在一既定步 距的寫入程序中，若快閃控制器丨M貞測到—個壞頁（即設^ 201131359 BP旗職）’則會跳過此頁，並繼續寫入步距的下—頁。當運算 C2同位檢查時’控制器1〇所認定的任何壞頁全部為零。 为又而έ，根據系統架構，一個既定步距的資料條可以 連續或平行的方式被填滿。在本實施例中，儲存器6由通道 作邏輯性分區，資料條可以平行方式寫入η個通遒。在此情 况丨夬閃控制器10在將輸入資料分配到資料條，並運算該步 距的C2同位檢查之前，會先檢測有效步距中的壞頁。在任二 情況下，資料寫入程序的影響是，將輸入資料分佈到步道裝 置5的儲存通道中編有〇2碼的步距。將資料條分配到特定^ 距二以及寫入作業中步距順序的選擇，係可以許多不同方式 實施於控制器1〇，且熟此技藝者當知如實作。 ^ 非”明之重點，且無需在此贊述。然而，一般而㊁特= #疋通道中’每個資料條包含位於—或多個快閃塊中的資料 小為^與5 ΐ示二個可能的步距組態。圖4中，C2條的大 閃塊的大步距係由圖中的箭頭作表示。假設一個快 資料体。I、4胃，則每個儲存塊將包含16個不同步距的 享通用16個f料條在所有通道中分享姻的儲存塊。分 不二此組步距爾後稱為步距群組。附註， 圖5频亍# 1中相同步距群_儲存塊無須實體對齊。 個步^在^—關，其中條的大小為二個儲存塊。因此，每 群存通道中包ί二個儲存塊’且在此-個步： 儲存塊無須實：連附5主，母個通道儲存區8中相同步距的 儲存控制器 10透過位址元資料將輸入資料的位置紀錄在 201131359 儲存器6，其元資料係由控制器ι〇保留在記憶體丨3。在此位 址元貧料包含LBA/PBA位址映射，表示與輸入資料塊相關聯 的邏輯位址(LBA)及儲存器6中的實體位址(PBA)之間的映 射。此一位址映射一般包含一或多個列表或其他資料結構， =結構係可用以決定儲存輸入資料塊的步距(以及其所包含的 貝料條)的實體位置。舉例而言，位址映射可在一列表中指明 LBA到步距ID的映射，以及在另—列表+指明步距仍到資 料條ID的映射’其中另—列表表示在—㈣條中可找到每個 LBA的PBA。然而，實際運作上，為了方便起見，較適合使 用包含所有位址元資料的單一搜尋表。 技藝者當知’透過將輸入資料分佈於編有EC碼的步 碼之外進!^1程序得以在資料頁層作保護的C1編 常每個次保護，避免各個通道中發生錯誤。通 掌期η = ，以及在回應讀取請求後或在内部管理作 菓期間項出資料後，才會進 料條包含紐透過C1 _^錯$制如下科。母當資 誤時，快閃控制器正程序作校正的資料頁或塊錯 同的儲存區8,作為包序。新的資料條會選自相 題的步距中的「壞資料條日、的貧料條。此貢料條將替代有問 13中的位址元資料作辨^步f中其他的㈣條係、自記憶體 料條的内容會被讀取牛，^取此等資料條的内容。壞資 編碼演算法，重建壞資其他㈣㈣时會透過C2 後）的資料接著被寫人替換^ #錯誤㈣。重建後(錯誤校正 後的步距結構。接著，* I亚更新位址元㈣以反映修改 資料頁無效(P1)旗幡，以、壤資料條的每個#料頁中會設定 衣不此等資料頁的内容無效。此等資 201131359 料頁將在隨後垃圾收集程序期間被回收，如下述。 ㈣除了將C2顺存為儲存器6中步 = 入期間運算部分的丄二 進行運^，Si圭:個步距的資料條期間，在連續階段中 而言，在每個資個=每個資料頁後。具體 的輸入資料實施㈡編碼，以取本得發一月/主對目前步距中所儲存 存於圖2的記憶體13十 w -係由控㈣10储 可為硬接線 器會在設備7的電源情，則控制 元資料，包^目^時錯誤校正碼(以及記憶體υ中的其他 區。藉此，得以複製到快閃儲存器6的可用 避免㈣源失檢查，- 更新麻方案在快_扣6中進行 設定資料頁無效(ΡΙ°^ 透過LBA覆寫而更新的任-頁， 利用類似方式設包含主機刪除的資料的資料頁亦可 組維持-計數，表示敕^織。儲存控制器10亦替每個步距群 距群組的此等Ρί；:數文資料頁的數量。步 間，如下述。、工制时丨0所運作的内部管理作業期 201131359 οσ雖然儲存器6替C2編碼作邏輯區分，已如上 益的内部管理功能係整體運作。即，就 而二旦儲存 控制器10將所有的分區(n個儲存通 =^，快閃 十勺)係負貝作跨區的C2編碼。具 ，、耗知 =資料的回復係以步距群組為主（而非儲;塊)的方2間’有 中作回復，其中4:;;:==”個步矩 參照圖6的垃圾收集程序作進—步描述^ 此作業將 圖6的方塊圖顯示SSD 5中斛播从& ^步驟。當初始化垃圾收集(如圖令步驟Γ戶程序的主 首先選擇欲抹除的儲存塊‘驟2^ 係根據記憶體13中替步距群組儲存的Π |^乍的此選揮， 言，在步距群組中具有最高 料$ :具體而 收。選擇-步距群組後，於步驟選作回 =頁回復所有仍有效的資料。因此;鮮 此程序可根據需求運作錯誤校二、、:=C1與C2碼， 接著反餽為欲重新儲存 壬子”的有敦資料可 已_村重新儲二=料。因此’ 資更新記憶體13中的㈣映二=7 S 201131359 Controller 3 is transparent. Multiple = Γ "external coffee" configuration, in which the coffee code word spans the outside, the New Zealand cross is more healthy (four). In addition to the external or #代随] to: === use an "internal coffee" system. Internal _ system real area, within the daily volume system. In this controller, Li space will be logically divided = 1 logical block of 1 segment will be allocated to the entire storage of empty money, the second sub-new in the Zengzi, r parity check, to the inner RAm jade - / Knife and knife in the collection of the early morning. Specifically, the internal key is divided into sub-unit (four) blocks, and each fresh-cell data block is provided with a sub-unit service (suLba) in each sub-address space. The mapping from the leg to the suLB is recorded by the controller in the lba_suLba address map. Each subunit block is then stored in the storage location of the real_previous location. The location is recorded in the suLBA_pBA map of the unit. This procedure provides EC coding' to avoid failure of the subunit layer in the SSD. For example, the external RAE) system's controller operates independently in each storage subunit (garbage collection, wear leveling, etc.), enabling subsequent remapping of this function with suLBA to pBA to be more logical than the RAH) coded block layer The lower level of the layer operates. One of the present inventions is directed to a control device that provides a solid state storage device, wherein the solid state storage pirate includes erasable blocks, each erasable block containing a plurality of data writing locations. The control device contains memory and control logic and is suitable for operation: ^ The input data is stored in a continuous group of data writing locations, and each group packet 3 is written in a plurality of logical sub-regions of the solid-state storage. One of the sub-areas can be erased in the block; the error correction code is coded for the input bead, so that each group contains the error correction code of the input data in the group 201131359; the metadata is maintained in the memory, Metadata indicates the location of the input data in the solid state storage; the heart maintains the validity representation of the data stored in each data write location; and returns valid input data from each group before erasing a storage block, The group includes the write location of the data block, and the restored data is re-stored as. Therefore, in the embodiment of the present invention, the storage space managed by the control device is logically divided into a plurality of logical sub-areas, and The input data will be written into, and many groups will be placed, and these groups will be distributed in these logical sub-areas. Specifically, >' In each logical sub-area, each group contains one or more write bits ^, which are group (one or more) erasable blocks in the "Hai sub-area". The present invention inputs an Ec code for the bedding operation for each group, and stores the code in the group for the input data. Furthermore, the present invention employs a memory block erasing procedure to restore valid data for each group. When the storage block is to be erased, for example, during garbage collection or other internal management work = the present invention is erased-storage Before the block, the valid data is returned from the 4 groups or the parent group including the two of the storage blocks. The validity of such a reply = the incoming material is then in the group towel with the new Ec code, and the bribe is newly entered. In this case, the embodiment of the present invention provides another layer of Ec encoding (ie, similar to the first:= Any conventional ec-coded operation within the in-page encoded write location, while allowing the memory to operate as an internal management function. Therefore, unlike the class = the above RAID system is implemented on the LBA to pBA map. Yu Shiqing ΒΑ layer, rather than the logic block (lba) layer, and the entire ▲ internal management of the purpose of the overall purpose. The implementation of the present invention _ efficient efficiency 201131359 avoids the failure of the storage sub-area by operating the flat code and the main internal (four) functions at the physical block level. And the interaction between the _ order provides an ancient; 'EC coding and internal management capabilities. For example, > too heart / 円 错 正 , , , , , , , , , , , , , δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ The control of the real wealth (four) is input two =: r::::r code (where the non-systematic coding of the coding program (where the code is coded to obtain the output codeword) or the word affection. Fine, rational phase; The code is embedded in the output code series and stored in each group... The system code is used to increase the EC code of the input data by using the input data of the control logic. Page: The storage location can be a flash memory. Any-area, medium data in the flash memory in the device can be written to the entire storage and storage item, and can include any type of coffee bean or crystal in any way from a single object σ ^ to a plurality of groups of items . However, one station contains more than -i, each channel providing a repository or storing multiple solid-state dies. Multiple packages based on Eit ' 'Each package has one or two zones, which can be used for the overall storage area, the logical branch of the handle in the available memory has a complex _ memory channel, ^ group ° 'in the _ store Each unit in the unit may generally comprise::: pass = there are: groups of solid state storage units (its areas) in the embodiment, each 3, loaded, smashed, die or any other storage ("妒母琏琏The sub-areas may include a single item in each channel, unless otherwise stated, the item referred to herein:: item. Or 'for example' each logical sub-area may contain an individual ring ^ 201131359 yuan 0 based on EC coding purposes, the input data is stored in a number of groups of write locations 'where each group contains in each logical sub-region One or more write locations are located in a set of erasable blocks of the sub-region. In the preferred embodiment, a group contains a plurality of write data 'located in each of the storage blocks of each sub-area, and the write locations within each of the storage blocks are contiguous (i.e., have consecutive physical locations). In general, in any sub-area, the combination of write locations of the groups may include a number greater or less than the number of write locations within a erasable block. However, for practical convenience, the number of write locations in each sub-area is preferably an integral factor or multiple of the number of write locations within the memory block. In the case where the number of writer positions in each sub-group is smaller than the size of the storage block, more than one group can share the touch storage block. In this case, if you share in the - logical sub-area - any group of the Lang block is also shared in each logical sub-area - a common storage block, which simplifies internal management operations. The EC code system of the input data of the group 5 group and the input data - 丨T exist in the group. _, in the write position of each group _ from the household J group · into the shell 枓 stored data operation - a temporary 1 connection, the stage, the invention will replace the time when the EC code can be needed on the day 1 Code and store it in the group. This temporary device can effectively complete the transfer. Furthermore, in the control register, the f source fails. The temporary mismatch code is stored in the solid state storage subzone and fails at the same time. To save the temporary code. Thereby, the power supply and the second embodiment of the present invention and the first aspect of the present invention provide a control device for the HI state storage device including the 111 state material it's memory containing the erasable 201131359 block each of which can be wiped out The block contains a set of data write locations. A third aspect of the invention provides a method of controlling a solid state storage device, wherein the solid state storage comprises erasable blocks, each erasable block comprising a plurality of data writing locations. The method comprises: storing input data in a continuous group of data writing locations, each group packet s writing location, a set of erasable in each sub-region of the plurality of logical sub-regions of the solid-state storage Within the block; the input data is coded with an error correction code so that each group contains an error correction code for the input data in the group; / ▲ maintains metadata in the memory of the solid state storage device, the metadata indicates solid state storage The location of the input data in the device; maintain a valid representation of the data stored in each data write location; and before the erase-storage block, the input data from the respective group _ complex is written for the memory block The location and the re-storing of the replied data results in a second aspect of the invention. It is known to those skilled in the art that a computer-like use, including any device, component or system having a real function, can have a right-i, - - - - - - - - - - - - It also provides an electric job type which contains computer code means, which can have an independent - only one I use the electricity: provide r implementation, second table 2 = language, code money release and / or (9) difficult to become another 12 [Embodiment] FIG. 2 is a block diagram of an exemplary embodiment 5 of the present invention, and the material management component involved in the data management operation. Which 5 buckle green 3 benefit 6 and control equipment (--like the system is indicated by 7). In this example, the six sub-ranges contain: storage channels Ch(1) through Ch(8), each of which provides a plurality of banks 8, i.e., flash storage dies 9. Each: the enamel group 9 can be set to - or a plurality of wafers or wafers to seal, layer data, crystal grains, ML. (Multilayer data cell) Crystal:, 2 = The person ̄ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (4) The remaining general series:: = == type _ _ 11, and the read/write _) interface for the request ^ i, ; 〇: ΓΓ ^ ^ Read and write in response to the received request, and ^ flash 5 The second of the assignment: Department management functions. Flash control writes 10 ages = all of the flashes of 6 are applied to hardware, software or their combination. The (4) logic real part of 1G is implemented by software, and its soft A j ' control logic can be fully or functional. The processor of the device 7 operates the encoding/decoding function HI to understand the applicable software from the description herein. e c is controlled by flash control, gb hard-wired logic circuit, and its circuit operation-like device 7; package 2 'killed by the skilled person knows the applicable circuit. Control details. The storage of a plurality of metadata in the operation of the 111G, as follows, may include one or more memory elements, which may include a 201131359 random access type of miscellaneous, including, for example, SDRAM (synchronous or higher order control) The device is connected to /, the main ^ machine is responsible for the read / write request, the plurality of devices ^ 2 2 'the south stage (four) 11 is responsible for the storage system + array of the desire. For example, 'device 5 can form a similar excitation In the case where the storage control manages multiple coffees, if not, this, associated with the data specified in the input read/write request, is a ==: machine) address space, or some logic '== One such address will be referred to as the LBA. The 11 initial LBA and the clear size data write request are sent to the device 7 asynchronously through the R/W. In writing people. f operates a layer of coding. The first EC coding layer (hereinafter referred to as "C1 code = a conventional code located in the writer's memory. As the input data is written to each flash page of the memory 6, the EC code will be used to input the material." Operation, and the result code ^ code) will become part of the metadata stored on the page. This metadata also contains invalid (αΗ) flag type validity identifier. The PI flag of the data page is fast flash control. 10 - Part of the normal control operation If, for some reason, the information on the page is considered invalid (for example, based on the data update, as detailed below), the flag can be set by the controller. The data page metadata generally includes Bad page (ΒΡ) flag, if a data page is deemed to be unusable (for example, too many C1 errors are displayed), the flash control is set to set this flag. This program is also controlled by the flash controller. A part of the function operates. 201131359 The flash controller 10 operates _ coding. When implementing C2 encoding, the SSD-θ EC encoding will be referred to as the “C2” sub-region corresponding to the channel combination on the medium-solid logic input block. Streaming a continuous group of people flashing pages through Each group owned ^ 'type operations. In this case, the Bebe page has all the files distributed in the storage 0; each data page generally contains a predetermined number of materials. Page), one or one in the channel storage area 8, -, only 6 eight in the storage area 8 has a unique page center for the ^B block of the body page in the page of the PBA. For convenience, the bar ID can be the storage of the first input data in the bar by writing the data to each step, c2 redundant. Figure 3 depicts the write procedure for the current effective step size. The -group data page in the page (Qf) is reserved for the C2 code of the step. Ρ ^ In: In the case of the input data in the established step, the fast flash control (four) ig will calculate the EC code of the input data and store the C2 in the last page of the step. The specific EC algorithm made by C2 coding is not the focus of the present invention. In the absence of this, in this example, the C2 code is assumed to be an X〇R parity check code. (Another C2 encoding system that can be used here is disclosed in the European patent application filed with this case. The number of the applicants is (10)(10)(4)(4), which is incorporated herein by reference). In the system, the C2 code of the above-mentioned step size includes a collective parity check code of a plurality of code words, which are scattered in the storage sub-area 8. In a writing procedure with a predetermined step, if the flash controller 丨M贞 detects a bad page (ie, set ^201131359 BP flag), the page will be skipped and the writing step will continue. -page. When the C2 parity check is performed, any bad pages identified by the controller 1 are all zero. To be awkward, according to the system architecture, a strip of a predetermined step can be filled in a continuous or parallel manner. In this embodiment, the memory 6 is logically partitioned by channels, and the data strips can be written in n ways in a parallel manner. In this case, the flash controller 10 detects the bad page in the effective step before assigning the input data to the data strip and calculating the C2 parity check of the step. In either case, the effect of the data writing procedure is that the input data is distributed to the storage path of the trail device 5 with a step size of 〇2 codes. The choice of assigning a strip to a specific interval and the order of the steps in the write job can be implemented in the controller 1 in a number of different ways, and the skilled artisan is aware of the facts. ^ is not the focus of the Ming, and does not need to be praised here. However, in general, the second special = #疋 channel in the 'each data strip contains information located in - or multiple flash blocks small ^ and 5 Possible step configuration. In Figure 4, the large step size of the large flash block of C2 is represented by the arrow in the figure. Suppose a fast data body. I, 4 stomach, each storage block will contain 16 The common 16 f-strips of the non-synchronized distance share the storage blocks of the marriage in all the channels. The group of steps is called the step group. Note, Figure 5 Frequency 亍 # 1 phase synchronization group _ The storage block does not need to be physically aligned. The steps are in ^-off, where the size of the bar is two storage blocks. Therefore, each storage channel contains two storage blocks 'and in this step: the storage block does not need to be: The storage controller 10 with the 5 main, parent phase channel storage area 8 records the position of the input data in the 201131359 memory 6 through the address element metadata, and the metadata is retained by the controller in the memory.丨 3. In this address, the poor material contains the LBA/PBA address map, indicating the logical address associated with the input data block ( Mapping between LBAs and physical addresses (PBAs) in storage 6. This address mapping typically contains one or more lists or other data structures, and the = structure can be used to determine the step size at which the input data blocks are stored ( And the physical location of the included strips. For example, the address map can indicate the mapping of the LBA to the step ID in a list, and the mapping of the step size to the strip ID in the other list + 'The other--list indicates that each LBA's PBA can be found in the -(d). However, in practice, for the sake of convenience, it is more appropriate to use a single search table containing all the address metadata. The input data is distributed outside the step code with the EC code! ^1 program can be protected every time in the data page layer protection C1, avoiding errors in each channel. 通 = , and After responding to the read request or after the internal management of the fruiting period, the feed bar will contain the following information through the C1 _^ error$ system. When the parent is in error, the flash controller is correcting the program. Page or block the same storage area 8, as an order The new data strip will be selected from the "bad data strip day" in the step distance of the title. This tribute strip will replace the address material in question 13 to identify the other (4) in step f. The content of the system and self-memory strips will be read by the cattle, and the contents of these data strips will be taken. The bad capital coding algorithm will be used to reconstruct the other assets (4) and (4) and then the data will be replaced by the writers. Error (4). After reconstruction (error-corrected step structure. Then, *I sub-updated address element (4) to reflect the invalidation of the data page (P1) flag, and each material page of the soil data bar will be set. The contents of this information page are not valid. The materials of this 201131359 material will be recycled during the subsequent garbage collection process, as described below. (4) In addition to the storage of C2 as the storage unit 6 step = the second part of the calculation period Yun ^, Si Gui: During the data strip of the step, in the continuous phase, after each resource = each data page. The specific input data is implemented (2) coded to obtain the memory stored in Figure 1 in the current month/main vs. current step. The memory is stored in Fig. 2, and the memory is stored in the device. In the case of power supply, the metadata is controlled, and the error correction code (and other areas in the memory port) are included. Thereby, the available memory can be copied to the flash memory 6 (4) source loss check, - update the hemp program in Quick_Button 6 is not valid for setting the data page (ΡΙ°^ Any page updated by LBA overwriting, using a similar method to set the data page containing the data deleted by the host can also be grouped to maintain - count, indicating 敕 ^ weave. The controller 10 also replaces the number of data pages of each group of distance groups: the number of data pages. The steps are as follows. The internal management operation period of the operation system 2011 0 201131359 οσ although the storage 6 for the C2 code for logical distinction, the internal management functions have been operating as a whole. That is, just the storage controller 10 will all the partitions (n storage pass = ^, flash ten spoons) is negative Cross-regional C2 coding. The group 2 (but not the storage; block) of the square 2 'has a reply, 4:;;:==" step by reference to the garbage collection program of Figure 6 - step description ^ This operation will be Figure 6 The block diagram shows the SSD 5 broadcast from the & ^ step. When the garbage collection is initialized (as shown in the figure, the owner of the step-by-step procedure first selects the storage block to be erased).群组 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍Therefore, the program can be operated according to the requirements of the second school, :==C1 and C2 code, and then the feedback is that you want to re-storage the scorpion". The information is already _ village re-storage 2 = material. Therefore (four) in the memory 13
控制㈣的㈣塊可接著被C 作儲存塊抹^，以釋放此等^工制☆ 1G可立即或隨後運 手又此寻儲存塊供新資料儲存。 义 201131359 如上所示，缝收錢間會回收-步驟群組 仏。相同原财、適用於在儲存塊抹除前需 ^二資 奸程序，例如耗損平均程序。 控功能的-部分，顯示持久問題(太多C1錯誤) 被辨識並標示為「壞儲存塊」。此標示旗 幟動作可根據㈣控 1G所維護的儲存塊錯誤計數，作為 13内所儲存的元資料的—部分。藉此，控制器隨後的 貝料放置將不會使用被標記為壞的儲存塊。 熟此技藝者當知，與習知類似RAID系統不同的是，C2 編碼係在SSD 5的實體儲存塊層運作，就内部管理而言，其 整個儲存區係以一個體作管理。對LBA/pBA映射而言，在 PBA層運作的C2編碼作業是透明的，且可避免資料頁σ、塊、 晶片、資料庫及通道層發生完全失效。上述暫時（^碼的使用 可避免同步電源與單位失效。透過以協同内部管理功能的方 式運作C2編碼，如上述，SSD 5得以改進錯誤率並具有極優 良的整體效能。具體而言，本發明改善錯誤效能卻不犧牲高 階編碼的寫入放大與持久性。舉例而言，假設在每個情況會 使用一個通道作冗餘，則SSD 5可與上述類似RAID以SSD 為主的系統相比較。在SSD 5中，假設通道η是全部分配給 C2碼’定義w]為内部管理所導致的寫入放大(垃圾收集與耗 損平均）。若為了方便，假設每條僅包含一頁，則每個資料頁 寫入將會有（l+(l/(n-l))Wl個資料頁寫入，因為控制器替(n_1；) 個資料頁運算一個同位檢查頁，每個通道皆有一個同位檢查 頁。相反地，類似RAID的系統，讓w2表示垃圾收集與耗損 £ 20 201131359 平均所導致的寫入放大，則每個資料頁寫入會有2w2個資料 頁寫入、一個資料頁與一個RAID同位檢查頁。再者，w i <W2， 因為内部管理係「全局」地運作，所以會將所有的儲存通道 視為一個統一儲存區。 在任一既定情況，透過適當選擇C2步距與資料條大小以 及負料條大小與LBA大小的關’可進一步改善效率。此考量 類似RAID應用所碰到的情況，如熟此技藝者所知。在本發 明的某些實施例中，快閃控制器可用來動態調整作業中的C2 資料條與步距大小。舉例而言，快閃控制器可根據預定標準(例 如根據寫入請求的大小）’在不同的資料條/步距大小間作交 ，。步距長度亦可a著儲存塊變的越純不穩定(例如因為耗 損與老化)而減短。熟此技藝者t知本發明可作適當的潤飾。 飾。述實施例當可作進一步的改變與潤 飾„ ’雖然用作C2編碼的儲存 中的儲存通道對齊，但一般而言此等子區可=用“ 益的任何子組。例如，子F 打1· α可用储存 粒9。C2瑪當可健存於包且含―圖2牛中的各快閃晶 再去，々m 1省俘子Q ’且母個步距盔須相同。 t, 步距可替代地橫跨 牡戒置τ 集合係分料财騎。在;數個料，步距的整體 通道、或不包含柏同+新貝枓條可選自相同的儲存 :長度亦可減短，藉:當儲:::::的任何其他通道。步 跨較少的通道，已如上述。鬼又的不穩足時，步距得以橫 201131359 雖然本發明之實施例並不一定需要Cl編碼，但有C】編 碼較為理想。再者，雖然本發明具體描述NAND快閃裝置， 但本發明當可採用其他類型的SSD。 义 热此技藝者當可對上述範例實施例作其他修 不偏離本發明之範嘴。 而 【圖式簡單說明】 一般而言，在此所述之特徵係參照本發明之一面向的一 實施例，本發明之另一面向的實施例中亦可提供對應^徵。 本發明之較佳實施例將以範例方式伴隨圖式作描^，其 圖1係習知具有類似RAID編碼以SSD為主的儲存系統的 示意圖； 圖2係實施本發明的固態儲存裝置的示意圖； 圖3繪示將輸入資料寫入分佈於圖2實施例中的儲 的一寫入位置群組； °° 圖4繪示一群組中寫入位置的一範例組態； 圖5繪示一群組中寫入位置的另一範例組態；以及 圖6繪示圖2的SSD中所運作的内部管理程序。 【主要元件符號說明】 1 儲存系統 2 固態儲存裝置 3 儲存控制器 儲存器 固態儲存裝置 固態儲存器 控制設備 儲存庫 快閃晶粒組 快閃控制器 讀/寫介面 快閃鏈結介面 記憶體The (four) block of control (4) can then be erased by C as a storage block to release the system. ☆ 1G can be used immediately or later to find the storage block for new data storage. Yi 201131359 As shown above, the sewing money collection will be recycled - step group 仏. The same original wealth, applicable to the need for a second rape program before the block is erased, such as the wear and tear average program. The - part of the control function, showing that the persistent problem (too many C1 errors) is recognized and marked as "bad storage block". This flag flag action can be used as part of the metadata stored in 13 according to the memory block error count maintained by (4) Control 1G. Thereby, the subsequent bead placement of the controller will not use the storage block marked as bad. It is known to those skilled in the art that, unlike conventional RAID systems, C2 encoding operates at the physical storage block level of SSD 5, and for internal management, the entire storage area is managed by a single body. For LBA/pBA mapping, the C2 encoding operation operating at the PBA layer is transparent and avoids complete failure of the data page σ, block, wafer, database, and channel layers. The above temporary use of the ^ code can avoid synchronous power supply and unit failure. By operating the C2 code in a cooperative internal management function, as described above, the SSD 5 can improve the error rate and has excellent overall performance. Specifically, the present invention Improve error performance without sacrificing write amplification and persistence for higher-order encoding. For example, assuming that one channel is used for redundancy in each case, SSD 5 can be compared to a RAID-like SSD-based system as described above. In SSD 5, it is assumed that the channel η is all allocated to the C2 code 'definition w' for internal management caused by write amplification (garbage collection and wear leveling). For convenience, suppose each strip contains only one page, then each The data page write will have (l + (l / (nl)) Wl data page write, because the controller operates a parity check page for (n_1;) data pages, each channel has a parity check page. Conversely, for a RAID-like system, let w2 denote garbage collection and wear loss. The write amplification caused by the average of 20 201131359, then each data page write will have 2w2 data page writes, one data page and one RAI. D is a check mark page. Furthermore, wi <W2, because the internal management system operates "globally", all storage channels are treated as a unified storage area. In any given situation, the C2 step and data are appropriately selected. Strip size and negative strip size versus LBA size can further improve efficiency. This consideration is similar to what is encountered with RAID applications, as is known to those skilled in the art. In some embodiments of the invention, flash control The device can be used to dynamically adjust the C2 strip and step size in the job. For example, the flash controller can be used to work between different strips/step sizes according to predetermined criteria (eg, depending on the size of the write request). The step length can also be shortened as the storage block becomes more purely unstable (for example, because of wear and aging). Those skilled in the art know that the present invention can be suitably retouched. Further changes and retouchings „ 'Although they are used as storage channels in C2 coded storage, in general these sub-areas can be used with any subgroup of benefits. For example, sub-F 1·α can be used to store particles 9 C2 Madang The flash crystals that are stored in the package and contain the cows in Fig. 2 go again, 々m 1 provinces have the same Q' and the mother's step helmets must be the same. t, the step can alternately span the dam ring set τ It is divided into several materials, the overall channel of the step, or does not contain the same + new shells can be selected from the same storage: the length can also be shortened, by: when the storage::::: Any other channel. The step spans fewer channels, as described above. When the ghost is unstable, the step size is traversable 201131359. Although the embodiment of the present invention does not necessarily require Cl coding, C code is preferred. Although the present invention specifically describes a NAND flash device, the present invention can employ other types of SSDs. Those skilled in the art can make other modifications to the above exemplary embodiments without departing from the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS In general, the features described herein are directed to an embodiment of one aspect of the present invention, and another embodiment of the present invention may also provide a corresponding feature. The preferred embodiment of the present invention will be described by way of example with reference to the accompanying drawings. FIG. 1 is a schematic diagram of a conventional storage system with RAID-like SSD-based storage; FIG. 2 is a schematic diagram of a solid-state storage device embodying the present invention. FIG. 3 illustrates a write location of a write location group stored in the embodiment of FIG. 2; °° FIG. 4 illustrates an example configuration of a write location in a group; FIG. Another example configuration of a write location in a group; and Figure 6 illustrates an internal hypervisor operating in the SSD of Figure 2. [Main component symbol description] 1 Storage system 2 Solid state storage device 3 Storage controller Storage Solid state storage device Solid state storage Control device Storage library Flash chip group Flash controller Read/write interface Flash link interface Memory