201128712 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種製作金氧半導體_s)電晶體的方 法’特収-㈣作具纽良之短料效叙金氧半導體 電晶體的方法。 ^ 【先前技術】 在積體電路的製造過程中’場效電晶體（fiddeffect t麵istor，FET)是一種極重要的電子元件，而隨著半導體 元件的尺寸越來越小，電晶體的製程步驟也有許多的改 進’以製造出體積小而高品質的電晶體。 習知的電晶體製程是在基底上形成閘極結構之後，再 於閘極結構相對兩側的基底中形成輕摻雜波極結構⑴钟办 doped drain，LDD)。接著於閘極結構側邊形成側壁子 (spacer)，並以此閘極結構及側壁子做為遮罩，進行離子植 入步驟，以於基底中形成源極/汲極區，最後，進行回火製 程。 請參照第1圖，第1圖為習知場效電晶體的結構示意 圖。如第1圖所示，在基底100上形成由閘極介電層1〇2 與閘極電極1〇4所構成的閘極結構1〇6之後，接著進行一 201128712 離子植入步驟，以於基底100中形成輕摻雜汲極結構110。 隨後於閘極結構106的側壁形成側壁子1〇8,並進行另一離 子植入步驟’以於側壁子108兩侧的基底1〇〇中形成源極/ 汲極112 ’然後進行一回火製程，完成場效電晶體之製作。 隨著裝置尺寸的縮小，更加難以控制接合深度（Xj)及減 少接入電阻（access resistance)。短通道效應（sh〇rt channel effects ’ SCE)顯然依接合深度而定，為了避免電晶體的設 計因元件積極度的增加而縮小之後所衍生的]V10S短通道 效應’必須縮小電晶體之源極與沒極的接合深度(junction depth)。曾有許多方法被提出以改善pFET的短通道效應， 但是對於65nm以下尺寸的製程而言，習知的As佈植與瞬 間快速熱處理（spike rapid thermal treatment)很難符合 nFET 的短通道效應的需求。 鑑於上述，為解決短通道效應的問題，需要重離子或 是擴散力較小的活化機台進行摻質植入，使摻質停留在植 入時之位置，如此，其深度較淺。但是此種先進的活化機 台，例如閃燃回火（flash anneal)或是雷射回火（laser anneal)，尚未開發成熟。 曾有揭示一種製造PM0S電晶體的方法，將氟佈植於 源極/没極延長區或源/沒極區，與此區的換質一起存在，然 201128712 後進行回火製程，如此可改善摻質的擴散，緩和短通 應。 但是’由於不斷的追求體積更小而品質更高的電晶 因此，對於能夠改善短通道效應及具有良好接合輪廊 的場效電晶體及其製法仍有需要。 【發明内容】 本發明的目的是提供一種製作金氧半導體電晶體的方 法，此種方法可改善短通道效應。 ㈣ 本發明之製作金氧半導體電晶體的方法包括下列步 驟。首先，提供-基底，其具有一閘極位於其上，一源極 區及-W分別位於問極兩側，及一通道區位於閉極下 方。接者，進行-預非晶化製程以於源極區及没極區各形 成一非晶化區域。然後’進行一第一離子植入製程，以於 源極區及沒極區植入一第一摻質而形成一第-掺雜區。於 閘極之側壁上形成-側壁子。進行—第二離子植入製程， 以於源極區及祕區植人—第二#質而形成—第二推雜 區。對該源極區及該沒極區進行—回火製程，藉以 第一摻質、使非晶化區域再長成結晶、及形成一接合於； —錢）。其中’於進行預非晶化製程之後及= 订回火製程之前’進行一共植入(——at—製程以於 201128712 源極區及汲極區植入一碳共植入物（co_implant)，碳共植入 物係來自一包括一氧化碳（CO)或二氧化碳（c〇2)的前驅物 (precursor) ° 依據本發明之製作金氧半導體(M0S)電晶體的方法， 其中包括一共植入製程之步驟，以於輕摻雜汲極區或源極 區、源極區、汲極區、或是環形佈植區大致相同的位置植 入一碳共植入物，此碳共植入物係來自一包括C〇或c〇2 的前驅物，因此，於進行快速熱處理製程後，例如使用習 知的佈植機及瞬間回火（spike annealing)機台進行製程後， 可減少與碳共植入物處於相同位置的摻質擴散，即，能有 效控制輕#雜〉及極區及源極區、源極區及沒極區、或是環 形佈植區的摻質的擴散，獲得良好的接合輪廓，改善短通 道效應。 【實施方式] 下文中參照第2至6圖說明依據本發明之一具體實施 例。第2圖$依據本發明之製作金氧半導體電晶體的方法 流程圖。如第2圖所示之依據本發明之製作金氧半導體電 晶體的方法之—具體實施例’包括下列步驟。提供-基底， 其具有閘極、源極區及汲極區、及一通道區。進行一預非 晶化製程301，以於源極區及汲極區各形成一非晶化區域。 進行共植入製程3〇2,以於源極區及汲極區植入一碳共植 201128712 入物1進行輕摻雜離子植入製程303,以於源極區 形成摻雜區。於閘極之側壁上各形成—側壁子。進行源上 及極植入製程3〇4 ’以形成摻雜區。進行— ’、 以活化摻質、使非曰化『祕 製程305 ’ 形成所欲之接再長成實質上的結晶形式、及 ^至6圖顯示依據本發明之製作金氧半導體電晶體 的方法之過程剖面圖。如第3圖所示，首先，提供一基底 2〇〇 °基底200上具有一由閉極介電層2〇2與開極電極綱 構成的閘極結構206。閘極介電層2〇2係由例如二氧 介電材料所構成，而間極電極2〇4係由經摻雜的多晶矽 咖㈣P°lySiH⑽)等導電材料所構成一源極區及-沒極 區分別位於間極結構寫兩側，及一通道區2〇u立於閘極 結構2〇6下方。接著，進行預非晶化製程3〇1以於源極區 f汲極區各形成-非晶化區域212,以將此處之矽晶格由單 系（ystalline)結構破壞為非晶系（am〇rph〇us)結構。預非 曰曰化製私可藉由—離子植人21()於源極區及沒極區植入一 播質而進行’摻質可舉例但不限於♦ (Si)、錄（Sb)、錯(Ge)、 及砷（As)。例如可使用植入能量約為4〇匕乂及佈植劑量約 = ίο14個原子/cm2^ Ge做為植入物，或是使用植入 月b里、力為40keV及佈植劑量約為3 〇 χ 1〇15個原子/cm2的 s做為植入物。佈植的角度可依所需垂直於佈植面或是具 傾斜角度。具有傾斜的角度，例如約3至10度，可使非晶 201128712 化區延伸至閘極下方。 進行共植入製程302以於源極區及汲極區植入一碳共 植入物。例如第4圖所示，進行一離子植入214做為共植 入製程，以於輕摻雜型源極/汲極預定區形成一共摻雜區 216。但是碳共植入物植入位置並不限為與後續的LDD植 入製程所植入摻質的位置大致上相同，亦可使其與後續的 源/汲極摻雜製程所植入摻質的位置大致上相同。如此，可 降低此處之後續製程所植入的摻質於進行快速熱處理製程 (rapid thermal process，RTp)回火後，因過度擴散而產生的 ^通道效應。於本發明中’碳共植入物係來一前驅物，此 前驅物包括CO或C〇2。此前驅物在植入機中先解離為包 括碳正離子的混合物，再經過分離程序，獲得碳正離子， 以做為碳共植人物。碳共植人物的植人能#可依植入位置 而定，例如，i KeV至20 KeV，較佳為5 Kev。劑量 ,1:至lx’個原子較佳為ΐχΐ〇Μ至ΐχΐ〇ΐ5個原 。較佳使用四道佈植(quadimpiam)，其進行四個佈 直步驟1植的傾角⑼t angle)，相對於法線方向（n_ai dlreCtl〇n)’可為〇至6〇度，及較佳為扣度。 =姉轉子植4们G3，例如第5_示4 :=2。4做為一遮罩，進行一離子植入218，以㈣ 5 2的部分區域植人_輕劑量摻質而形成輕換雜 201128712 源極/汲極區（LDD) 220。於此具體實施例中，LDD 22〇中 有共植入製程之碳共植入物存在。輕摻雜離子植入製程所 使用之摻質可為如下述。於製造NLDD (即，n型ldd)時， 可使用例如As或p做為源極/汲極區的輕劑量摻質。於製 造PLDD (即，p型LDD)時，可使用例如B、bf2、BwHz+、 或（BWHZ):(其中w為2至3〇的數，較佳為i8，冗為2至 40的數，較佳為22，及m為1〇至1〇〇〇的數較佳為_) 做為源極/汲極區的輕劑量摻質。輕劑量的摻質之劑 例如1〇17至1〇20個原子/cm3。 · 卢g^DD的植人製程完成後，可進—步進行—瞬間快速敎 ^製程(spikeRTP)，以活化摻質。或者，不進行此步驟、: 而於源極/沒極佈植完成後，—併進行回火處理。 接著，進行源極/沒極植入製程3〇4，如 於閘極結構206之側壁上形成一側不， 層或多層_層結構。例如，可靡子可為單 及氮梦化合物層所構成’或由氧化“層’ 以及氮化㈣壁子所構成。然後， spacer) =極區及_直入一重劑量摻質而形成摻:：： ==重劑量的摻〜劑量可為= 201128712 最後，進行回火（annealing)製程305，例如快速熱處理 製程（rapid thermal process)，或是瞬間回火製程，以利用 1000至1050°C的高溫來活化基底200内的摻質，形成所欲 之接合輪廓，並同時修補在各離子植入製程中受損之基底 200表面的晶格結構，以再長成為實質上的結晶形式。 上述第2圖所示之流程圖中，共植入製程302係於預 非晶化製程301之後及輕摻雜離子植入製程303之前進 行，但是值得注意的是，只要共植入製程302於回火製程 305之前完成，即可達成控制基底内各摻質良好擴散之效 果。因此，共植入製程302可於進行預非晶化製程301之 後及進行輕摻雜離子植入製程303之前進行；或是如第12 圖所示於進行輕摻雜離子植入製程303之後及進行源極/汲 極植入製程304之前進行；或是如第13圖所示於進行源極 /汲極植入製程304之後及進行回火製程305之前進行。因 此，碳共植入物植入於基底200中之位置可與輕摻雜離子 佈植區的摻質位置大致相同，或與源極/汲極的重劑量摻質 位置大致上相同。 請參閱第7圖，其顯示依據本發明之另一具體實施例， 與上述之具體實施例相同步驟，但進一步包括一環狀植入 製程(halo implantation) 306。環狀植入製程亦稱為「口袋佈 植（pocket implant)」，用以減緩「衝穿（punch through)」現 10 201128712 象 ’即’可限制源極/沒極摻f的橫向擴散。 界定後及源極/汲極擴散之前進行。由於_之極 邊緣的閘極下方 =佈㈣尖峰濃㈣接近源極/祕區。在遠離源極/沒極 環形佈植的尖峰濃度之深度快速下降。 ，如第7圖所示，此環狀植人製程规係於進行共植入 製程302之後及進行輕摻雜離子植入製程3〇3之前進行。 鲁但是，其亦可於進行預非晶化製程301之後及進行共植入 製，302之前進行，如第u圖所示。環形佈植所使用之推 質是與源極/汲極電性相反的物種，例如，於製造ηρΕτ時， LDD使用As摻質，而環狀植入製程可使用B或Bp〗做為 摻質。於製造PFET時，LDD使用b或卵2摻質，而環狀 植入製程可使用As或P做為摻質。環形佈植區的植入物濃 度依裝置尺寸而定，尺寸越大，濃度越高，可舉例為在 lxlO17與lx10i8個原子/cm3之間。可使用相對於基底法線 (垂直線）0至約30度或更高的佈植角度，以使環型植入物 稍微延伸至閘極下方。 於包括環狀植入製程的情形下，碳共植入物植入於基 底200中之位置除了可與輕摻雜離子佈植區的摻質位置大 致相同’或與源極/汲極的重劑量摻質位置大致上相同之 外，亦可與環狀植入製程之摻質位置大致相同。如第8圖 所示’環狀佈植區230除了環狀植入製程所植入之摻質之 201128712 外，尚包括共植入的碳共植入物，如此可對環形佈植的摻 質擴散有良好控制，以形成較佳之接面輪廓。 使用碳共植入物與摻質一起存在於佈植區時，因為碳 共植入物存在於石夕晶體之間隙（interstitials)，可抑制摻質 (例如硼或磷）的擴散，而達成控制摻質擴散的效果，獲得良 好的接合輪廓。 第9圖顯示依據本發明之金氧半導體電晶體的製法之 * 一具體實施例使用碳共植入物所製得之PLDD，與習知之 製法不使用共植入製程所製得之PLDD，對於B濃度之二 次離子質譜術（secondary ion mass spectroscopy，SIMS)測試 之比較圖。二者均使用3 KeV之BF2做為摻質進行PLDD 佈植，但是於依據本發明之具體實施例中，進一步使用碳 共植入物進行共植入製程。由第9圖可知，使用碳做為B 的共植入物，可減少B的擴散，以製得更淺及更陡之接面。修 與習知之使用氟共植入相較之，本發明之方法對於減少B 擴散，有更佳之功效。 第10圖顯示依據本發明之金氧半導體電晶體的製法之 一具體實施例使用碳共植入物所製得之NLDD，與習知之 製法不使用共植入製程所製得之NLDD，對於As濃度之二 次離子質譜術測試之比較圖。二者均使用能量4 KeV及劑 12 .201128712 量1·5χ1015個原子/cm3之入8做為摻質進行NLDD佈植，但 是於依據本發明之具體實施例中，進一步使用碳共植入物 進行共植入製程，佈植能量為3 Kev。由第10圖可知，使 用碳做為As的共植入物，亦有減少As擴散的功效，以製 得更淺及更陡之接面。 以上所述僅為本發明之較佳實施例，凡依本發明申請 •專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖為習知場效電晶體的結構示意圖。 第2圖為依據本發明之製作金氧半導體電晶體的方法的 一實施例的流程圖。 第3至6圖顯示依據本發明之製作金氧半導體電晶體的 方法之過程剖面圖。 圖，其顯示依據本發明之另—具體實施例之流程圖。 第8圖顯示-依據本發明之一具體實施例之結構剖面 圖，其中環狀佈植區包括摻質及植入物。 =圖顯示依據本發明之金氧半導體電晶體的製法之一 ==施例與習知之製法對於pld_b濃度之 子質譜術測試之比較圖。 雕 第1〇圖顯示依據本發明之金氧半導體電晶體的製法之 201128712 一具體實施例與習知之製法對於NLDD中As濃卢之_ 次離子質譜術測試之比較圖。 — 第11至13圖顯示依據本發明之金氧半導體電晶體的掣 法的若干實施例的流程圖。 、 【主要元件符號說明】 100、200 基底 102、202閘極介電層 104、204閘極電極 106、206 閘極結構 108 側壁子 110 輕摻雜汲極結 構 112、226源極/汲極 201 通道區 212 非晶化區域 216 共摻雜區 210、214、218、224 離子植入 220 輕摻雜型源極/汲極區 222 側壁子 230 環狀佈植區 3〇1 預非晶化製程 302 共植入製程 303 輕摻雜離子植入製程 304 源極/汲極植入製程 305 回火製程 306 環狀植入製程201128712 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for producing a oxy-semiconductor (s) transistor, and a method for producing a short-effect gold-oxide semiconductor transistor of New Zealand . ^ [Prior Art] In the manufacturing process of integrated circuits, 'fiddeffect t-surface is the most important electronic component, and as the size of semiconductor components becomes smaller, the process of transistors There are also many improvements in the steps to make small, high quality transistors. The conventional transistor process is to form a lightly doped wave structure in a substrate on opposite sides of the gate structure after forming a gate structure on the substrate (1) doped drain (LDD). Then forming a spacer on the side of the gate structure, and using the gate structure and the sidewall as a mask, performing an ion implantation step to form a source/drain region in the substrate, and finally, returning Fire process. Please refer to Fig. 1. Fig. 1 is a schematic structural view of a conventional field effect transistor. As shown in FIG. 1, after the gate structure 1〇6 composed of the gate dielectric layer 1〇2 and the gate electrode 1〇4 is formed on the substrate 100, a 201128712 ion implantation step is performed. A lightly doped gate structure 110 is formed in the substrate 100. Subsequently, sidewalls 1〇8 are formed on the sidewalls of the gate structure 106, and another ion implantation step is performed to form the source/drain 112' in the substrate 1〇〇 on both sides of the sidewall spacer 108 and then tempered. Process, complete the production of field effect transistor. As the size of the device shrinks, it is more difficult to control the joint depth (Xj) and reduce the access resistance. The short channel effect (SCE) is obviously determined by the depth of the joint. In order to avoid the transistor design being reduced due to the increase in component positivity, the V10S short channel effect must reduce the source of the transistor. Junction depth with immersion. There have been many methods proposed to improve the short channel effect of pFETs, but for processes below 65 nm, conventional As implants and spike rapid thermal treatments are difficult to meet the short channel effects of nFETs. . In view of the above, in order to solve the problem of the short channel effect, it is necessary to carry out dopant implantation by a heavy ion or an activation machine having a small diffusion force, so that the dopant stays at the position at the time of implantation, and thus, the depth is shallow. However, such advanced activation machines, such as flash anneal or laser anneal, have not yet matured. A method for fabricating a PM0S transistor has been disclosed. The fluorine is implanted in the source/no-polar extension region or the source/no-polar region, together with the reformation in this region, and the tempering process is performed after 201128712, which can be improved. The diffusion of the dopants eases the short pass. However, due to the continuous pursuit of smaller and higher quality electro-crystals, there is still a need for field-effect transistors that can improve short-channel effects and have good joint lands. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of fabricating a MOS transistor which can improve short channel effects. (4) The method of producing a MOS transistor of the present invention comprises the following steps. First, a substrate is provided having a gate thereon, a source region and -W are respectively located on both sides of the gate, and a channel region is located below the gate. In addition, a pre-amorphization process is performed to form an amorphized region in each of the source region and the gate region. Then, a first ion implantation process is performed to implant a first dopant in the source region and the gate region to form a first doped region. A sidewall is formed on the sidewall of the gate. Performing a second ion implantation process to implant the source region and the secret region - the second #质# - the second push region. The source region and the non-polar region are subjected to a tempering process, whereby the first dopant is used, the amorphized region is further crystallized, and a bond is formed; In the 'after the pre-amorphization process and before the tempering process', a total of implantations were carried out (-at-process to implant a carbon co-implant in the source and bungee regions of 201128712, The carbon co-implant is derived from a precursor comprising carbon monoxide (CO) or carbon dioxide (c〇2). A method of fabricating a metal oxide semiconductor (MOS) transistor according to the present invention, including a co-implantation process a step of implanting a carbon co-implant at a substantially doped position of the lightly doped bungee or source region, the source region, the drain region, or the annular implant region, the carbon co-implant from A precursor comprising C〇 or c〇2, therefore, after the rapid thermal processing process, for example, using a conventional implanter and a spike annealing machine, the co-implantation with carbon can be reduced. The dopants in the same position are diffused, that is, the diffusion of the dopants in the light region and the source region, the source region and the non-polar region, or the annular implant region can be effectively controlled, and good bonding is obtained. Contour, improve short channel effect. [Embodiment] An embodiment of the present invention is illustrated in Figures 2 through 6. Figure 2 is a flow chart of a method of fabricating a MOS transistor in accordance with the present invention. A MOS device fabricated in accordance with the present invention as shown in Figure 2 The method of the transistor - the specific embodiment 'includes the following steps. Providing a substrate having a gate, a source region and a drain region, and a channel region. Performing a pre-amorphization process 301 for the source region And forming an amorphization region in each of the drain regions. The co-implantation process is performed 3〇2 to implant a carbon co-planting in the source region and the drain region, and the light-doped ion implantation process 303 is performed. Forming a doped region in the source region, forming a sidewall on each of the sidewalls of the gate, and performing a source and a pole implant process 3〇4' to form a doped region. Performing - ', to activate the dopant, The non-deuterated "Miscellaneous Process 305' forms a desired crystalline form, and the figure 6 shows a process cross-sectional view of a method for fabricating a MOS transistor according to the present invention. Show that, firstly, a substrate is provided, and the substrate 200 has a closed a gate structure 206 composed of a dielectric layer 2〇2 and an open electrode layer. The gate dielectric layer 2〇2 is composed of, for example, a dioxy dielectric material, and the interpole electrode 2〇4 is doped. A source region and a non-polar region formed by a conductive material such as polycrystalline silicon (4) P°lySiH(10)) are respectively located on both sides of the interpolar structure, and a channel region 2〇u stands below the gate structure 2〇6. Next, a pre-amorphization process 3〇1 is performed to form a-amorphization region 212 in each of the source region f-polar regions to destroy the germanium lattice from the ytalline structure to the amorphous region ( Am〇rph〇us) structure. Pre-non-chemicalization can be carried out by ion implantation (21) in the source region and the non-polar region. The doping can be exemplified but not limited to ♦ (Si), recorded (Sb), Wrong (Ge), and arsenic (As). For example, an implantation energy of about 4 〇匕乂 and a planting dose of about ίο14 atoms/cm 2 ^ Ge can be used as an implant, or an implantation month b, a force of 40 keV, and a planting dose of about 3 can be used. 〇χ 1 〇 15 atoms / cm 2 of s as an implant. The angle of the implant can be perpendicular to the planting surface or at an oblique angle as desired. Having an oblique angle, for example about 3 to 10 degrees, allows the amorphous 201128712 zone to extend below the gate. A co-implantation process 302 is performed to implant a carbon co-implant in the source and drain regions. For example, as shown in FIG. 4, an ion implantation 214 is performed as a co-implantation process to form a co-doped region 216 in the lightly doped source/drain predetermined region. However, the position of the carbon co-implant implant is not limited to be substantially the same as the position of the implant implanted in the subsequent LDD implantation process, and may be implanted with the subsequent source/drain doping process. The location is roughly the same. In this way, the dopant effect of the dopant implanted in the subsequent process here after the rapid thermal process (RTp) tempering due to excessive diffusion can be reduced. In the present invention, the carbon co-implant is a precursor which includes CO or C〇2. Previously, the precursor was dissociated into a mixture containing carbon cations in the implanter, and then subjected to a separation procedure to obtain carbon cations for co-planting. The carbon implanted person's implantability can depend on the location of the implant, for example, i KeV to 20 KeV, preferably 5 Kev. The dose, from 1 to 1 x atoms, is preferably from ΐχΐ〇Μ to ΐχΐ〇ΐ5. It is preferable to use four quadrimiam, which performs the inclination angle of the four straight steps 1 (9) t angle, and may be 〇 to 6 相对 degrees with respect to the normal direction (n_ai dlreCtl〇n)', and preferably Deduction. = 姊 rotor plant 4 G3, for example, 5_ shows 4: = 2. 4 as a mask, an ion implantation 218, in part (4) 5 2 implanted _ light dose dopant to form a light swap Miscellaneous 201128712 Source/Bungee Zone (LDD) 220. In this particular embodiment, a co-implanted carbon co-implant is present in the LDD 22A. The dopant used in the lightly doped ion implantation process can be as follows. For the manufacture of NLDD (i.e., n-type ldd), for example, As or p can be used as a light dose dopant for the source/drain regions. For the manufacture of PLDD (ie, p-type LDD), for example, B, bf2, BwHz+, or (BWHZ) can be used: (where w is a number of 2 to 3 ,, preferably i8, and a redundancy is 2 to 40, Preferably, 22, and the number of m from 1 Å to 1 Torr is preferably _) as a light dose dopant in the source/drain region. A light dose of a dopant such as 1 〇 17 to 1 〇 20 atoms/cm 3 . · After Lug^DD's implanting process is completed, it can be carried out in a step-by-step process (spikeRTP) to activate the dopant. Alternatively, do not perform this step: and after the source/polarization is completed, - and tempering. Next, a source/dot-electrode implant process 3〇4 is performed, as shown on the sidewalls of the gate structure 206, a side layer or a multilayer layer structure is formed. For example, the tweezers can be composed of a single and nitrogen dream compound layer or consist of an oxidized "layer" and a nitrided (four) wall. Then, spacer = = polar region and _ straight into a heavy dose of dopant to form a blend: : == The dose of the heavy dose can be = 201128712 Finally, an annealing process 305, such as a rapid thermal process, or an instant tempering process to utilize a high temperature of 1000 to 1050 ° C is performed. The dopant in the substrate 200 is activated to form a desired bonding profile, and at the same time, the lattice structure of the surface of the substrate 200 damaged in each ion implantation process is repaired to grow into a substantially crystalline form. In the flow chart shown, the co-implantation process 302 is performed after the pre-amorphization process 301 and prior to the lightly doped ion implantation process 303, but it is worth noting that as long as the co-implant process 302 is in the tempering process The effect of controlling the good diffusion of the dopants in the substrate can be achieved before 305. Therefore, the co-implantation process 302 can be performed after the pre-amorphization process 301 and before the lightly doped ion implantation process 303; Figure 12 is shown after performing the lightly doped ion implantation process 303 and before the source/drain implant process 304; or after performing the source/drain implant process 304 as shown in Figure 13 And performing the tempering process 305. Therefore, the carbon co-implant is implanted in the substrate 200 at a position similar to that of the lightly doped ion implantation zone, or with a source/drainage dose. The dopant sites are substantially the same. Referring to Figure 7, there is shown the same steps as the above-described embodiments in accordance with another embodiment of the present invention, but further including a halo implantation 306. The implant process, also known as "pocket implant," is used to slow down the "punch through" of the 2011 20111212-like 'that' limits the lateral diffusion of the source/polarization doping f. Performed after the definition and before the source/bungee diffusion. Since the _ pole is at the edge of the gate below = cloth (four) peak is thick (four) close to the source / secret area. The depth of the spike concentration away from the source/no-polar ring is rapidly reduced. As shown in Fig. 7, the ring implanting process is performed after the co-implantation process 302 and prior to the light doping ion implantation process 3〇3. However, it can also be performed after the pre-amorphization process 301 and before the co-implantation process 302, as shown in FIG. The pusher used in ring implants is the opposite of the source/drain polarity. For example, when making ηρΕτ, LDD uses As dopant, while the ring implant process can use B or Bp as dopant. . When manufacturing PFETs, LDD uses b or egg 2 dopants, while ring implant processes can use As or P as dopants. The implant concentration in the annular implant area depends on the size of the device. The larger the size, the higher the concentration, which can be exemplified between lxlO17 and lx10i8 atoms/cm3. A planting angle of 0 to about 30 degrees or higher relative to the substrate normal (vertical line) can be used to extend the ring implant slightly below the gate. In the case of a ring implant process, the carbon co-implant is implanted in the substrate 200 at a location that is substantially the same as the dopant position of the lightly doped ion implantation zone or with the source/drain The dose doping sites are substantially the same, and may be substantially the same as the dopant sites of the ring implant process. As shown in Fig. 8, the annular implanting zone 230 includes a co-implanted carbon co-implant, in addition to the 201128712 implanted by the annular implant process, so that the dopant can be implanted in the ring. The diffusion is well controlled to form a preferred junction profile. When a carbon co-implant is present in the implant area together with the dopant, the carbon co-implant is present in the interstitials of the crystal, which inhibits the diffusion of dopants (such as boron or phosphorus) and achieves control. The effect of diffusion of the dopant gives a good joint profile. Figure 9 is a diagram showing the preparation of a MOS transistor according to the present invention. A specific embodiment of the PLDD obtained by using the carbon co-implant, and the PLDD obtained by the conventional method without using the co-implantation process, Comparison of secondary ion mass spectroscopy (SIMS) tests for B concentration. Both use PLF of 3 KeV as the dopant for PLDD implantation, but in a specific embodiment in accordance with the invention, the carbon co-implant is further used for the co-implantation process. As can be seen from Figure 9, the use of carbon as a co-implant of B reduces the diffusion of B to produce a shallower and steeper junction. Compared with the conventional use of fluorine co-implantation, the method of the present invention has better efficacy for reducing B diffusion. Figure 10 is a view showing an embodiment of the method for producing a MOS transistor according to the present invention. The NLDD obtained by using a carbon co-implant is prepared by the conventional method without using a co-implantation process. Comparison of concentrations of secondary ion mass spectrometry tests. Both use energy 4 KeV and agent 12 .201128712 amount of 1 · 5 χ 1015 atoms / cm 3 into the 8 as a dopant for NLDD implantation, but in a specific embodiment according to the invention, further use of carbon co-implant The co-implantation process was carried out with an energy of 3 Kev. It can be seen from Fig. 10 that the use of carbon as a co-implant of As also has the effect of reducing the diffusion of As to make a shallower and steeper junction. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the application of the present invention are intended to cover the scope of the present invention. [Simple Description of the Drawing] Fig. 1 is a schematic view showing the structure of a conventional field effect transistor. Figure 2 is a flow diagram of an embodiment of a method of fabricating a MOS transistor in accordance with the present invention. Figures 3 through 6 show process cross-sectional views of a method of fabricating a MOS transistor in accordance with the present invention. Figure, which shows a flow chart of another embodiment in accordance with the present invention. Figure 8 shows a cross-sectional view of a structure in accordance with an embodiment of the present invention in which the annular implant region includes a dopant and an implant. = Figure shows one of the methods for preparing a MOS transistor according to the present invention == Comparison of the method of the example and the conventional method for the mass spectrometry test of the pld_b concentration. Fig. 1 is a view showing a comparison of a specific embodiment of the MOS transistor according to the present invention and a conventional method for the As-ion ion mass spectrometry test in NLDD. - Figures 11 through 13 show flow diagrams of several embodiments of the oxime method of a MOS transistor in accordance with the present invention. [Major component symbol description] 100, 200 substrate 102, 202 gate dielectric layer 104, 204 gate electrode 106, 206 gate structure 108 sidewall spacer 110 lightly doped gate structure 112, 226 source / drain pole 201 Channel region 212 amorphized region 216 co-doped region 210, 214, 218, 224 ion implantation 220 lightly doped source/drain region 222 sidewall spacer 230 annular implant region 3〇1 pre-amorphization process 302 Co-implantation Process 303 Lightly Doped Ion Implantation Process 304 Source/Tungsten Implantation Process 305 Tempering Process 306 Ring Implantation Process
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