TW201128400A - A multi-facet hardware template for arbiters - Google Patents

Abstract

In this invention, a new multi-facet arbiter hardware template with reusability, modularity, composability, and expansibility is presented. This hardware template consists of 4 modules: PREEMPTION module, TOKEN_GENERATION module, TOKEN_CONTROL module, and BANDWIDTH module, and is easily implemented.

Description

201128400 IX. Description of the invention: [Technical field of invention] The arbitrator is mostly oriented to the hardware framework. The invention is an elastic hardware architecture designed to implement a variety of arbitrator hardware so that it can effectively manage the exclusive use of exclusive use. For example, the problem of who is the right to use in each period of time, such as bus bar, shared memory, switch, and shared processing unit. °σ [Prior technology]

The Round robin arbiter guarantees that all inputs are served and are treated fairly. It basically consists of a Programmable Priority Encoder (ppE), which is used to record priority indicators, an incrementer and a binary encoder. The Programmable Priority Encoder (PPE) consists of two simple priority encoders, jsmpl-PE), a thermal encoder and bitwise AND/〇R gates. Both of these designs are too complex for the simple round_robin mechanism to be easily integrated into the SoC. , fast and simpler smpl-PE Zhongmei makes the layer, forward-looking, and folding, and the design of the priority index makes the face d-scheduler change complicated.

t attack, the rest of the request from the other half by the arbiter will recognize an input to tear 2

I 昀 π π 理 这种 这种 这种 This operating mode, Τ·t· 'i 5 5 201128400 - more than the rest of the TV/2 input, resulting in unfairness. In this case, ppA cannot provide round-robm-style fairness. The scheduling performance of ppA is not as good as that of PPE-based iSLIP and DRRM. The idea of using the same "military", another arbiter design, the so-called exchange. Arbitration, (SA). The SA is a tree structure composed of a 4 x 4 SA service node. Each SA node consists of a D flip-flop, four priority encoders, a 4-bit ring counter, five 4-input R-gates, and four 2-input AND gates. SA speed is faster than PPA, and it is the fastest known arbiter, and its circuit structure has the advantages of hierarchical design. However, its circuit is large and complex. As a non-uniform distribution of SA, the treatment of non-uniform distribution is a non-fair distributed hierarchical tree arbitration architecture is a hybrid of network crossbar switch and crossbar arbiter. Arbitration and data transfer are performed at the same time. In addition to the hierarchical tree-like characteristics, each node requires less arbitration and the complexity is lower than the above-mentioned SA architecture, so the cr〇ssbar delay is small. This tree-arbitrating architecture is also not fair. As for the design of the arbiter hardware muW_faeet template, the design of the arbiter hardware muW_faeet template has never been seen before. [Summary of the Invention] With the rapid development of technology, the guessing of designing and implementing an embedded hall with thousands of cores has become one of the most critical issues. In many of them, /P (Intelleetuamoperty), such as processor, sensation film / network, peripheral units are all on one chip, competing with each other / other than / 201128400 different: source. The competition for the same or different types of use of the same source on the same wafer will be more intense. Therefore, it is becoming more and more important to use arbiters for ίί problems, high and low cost. The design of the cut 11 has been proposed. However, the design of multi-arbitrage-oriented devices: the "hard-frame" is generally not analyzed and discussed, and there is a lack of a systematic and flexible hardware-frame design function of Ke's arbitrators. Here, we deduced to design the elasticity. The arbitrator is mostly oriented to the hardware frame. The arbitrator of the present invention is composed of four modules as shown in the figure. PREEMPTION fills, TOKEN-GENERATION, TOKEN-CONTROL槙纰, and BANDWIDTH槙The actions, behaviors, and specifications of each model level in 岚 are described by their respective algorithms.

8n.j W Figure 1. The arbitrator is mostly oriented to the hardware framework. The algorithm of the PREEMPTION group is as follows: · Algorithm PREEMPTION{ri〇~ ri^.i, g〇~ gN-i) input,. ri〇~ riN .iiN requests (jnasked)) 201128400 output: g〇- gN.j (N output grants) begin for / = 0 to N-\ do gi ^~0; for i = 0 to TV-1 do begin if r,· ==1 then g, 1; break; end-for end TOKEN—GENERATION槙纰 The deductive method is as follows:

Aigorithm TOKEN—GENERATIONS ή〇 riw,g0 〜如,Q〇 〜h D〇~Dn 〇 Input·. I,ri〇 〜rir^,g〇 〜gN.i {N grants)

Input: Qe ~Qn-i {N internal states)

Output: D〇~ Dnj {N tokens) begin anyRl〇0; anyRJj ri〇; if /==1 // for equal-priority arbitration then begin for z = 0 to Nl do begin ifi>2 then anyRIi n/./ OranyRI^

D,· <- Qi and anyRlj; end end else begin // for non-equal-priority arbitration as Γ for z = 0 to Nl do D-, gt\ end if... begin Z),· = .. End // expansible for any other arbitration output all Di end • L·遂TOKEN—GENERATION is generated by the % method, tokens can/loss" wrong, loose priority, non-equal priority or other arbitration property. Therefore, the function of 201128400 TOKEN-GENERATION is extended with the surname. The tears of TOKEN CONTROL are like a fly · A\goritYim TOKEN—CONTROLire. ~reN.u D. ~DN.h E, r% ~riN.丨,Q()~QN.d input: E, re〇~ reN.j (N unmasked requests), D0~DNm] output: ri〇~riN-h iN masked Requests), Q0 ~QN-t begin for i = Oto Nl do Qt <- 1; for each arbitration time unit do begin for i=0 to Nl do Q,· D,·; if E == 1 //for Preemptive arbitration under Γ

Then for i = OioN-l do rij ref, else begin // non-preemptive arbitr. under Γ or others for i = Oto N-l do rij re·, and Qf, end end-for end The algorithm of the module is as follows:

Algorithm BANDWIDTH(r〇~rN.hw〇~g0 ~gN.h W,re0 ~ input: W, r〇~ rN.j (TV input requests), go ~gN·] input: w〇~wn-i ( N bandwidth requests set by requesters) output: re〇~ reN.j (N unmasked requests) begin load <— 0; for / = 0 to Λ^-l do QBtw,·; for each arbitration time unit do if W= = 1 // with bandwidth constraints then begin if load = 1 then for / = 0 to A^-l do QBi<-QBj + wf, else begin for / = 0 to N-\ do 9 201128400 if QBi == 0 then Begin; else begin rei — n·, if gi== 1 then QBt QBi A ; end end—for end end else // without bandwidth constraints f〇r/ = 〇to7V-l do re^n; end^f〇^ aU mi ^ 〇then l〇ad 1 ; " new bandwidth quota end

We can implement a different arbiter with one or one property by setting the parameters ",, and five" in the figure. That is to say, the arbitration of the 1 is more than hard, reusable, expandable, and combinable. The six kinds of arbiters are not allowed to be properly set by the corresponding three parameters in Figure 1.

Parameter setting and generation of the game. Relative priority Equal-priority No bandwidth limit No BW-constraint W=〇 W’l arbiter Priority is not right Non-equal priority /=0

Relative privilege equal-priority / priority is not right Non-equal priority

Non-preemption is not preemptive, five = 〇 W, I, E, arbiter

Preemption preemptive, five: W’I’E arbiter WI arbiter

Non-preemption is not preemptive, £ = 〇 WI’E’arbiter

Preemption is not preemptive, five=1 WI*E arbiter 201128400 [Embodiment] Same as [Invention] [Simplified description] Figure 1. The arbitrator is more oriented to the hardware frame. [Main component symbol description] ΜNumber of users . r, ·: The exclusive use requirement of the shared resource from the user/issued, OSzSTV·/. Along or g〇']: If the signal is 1 on behalf of the user / the use of the exclusive resources already obtained is recognized. W, ·: The bandwidth requirement for each input (user), 0 S z· S is 7.

Di ·. N 値 tokens, Q < i < N-1. Milk bandwidth requires setting parameters. /: Priority requires setting parameters. Five: Preemptive requirements are set.

Claims (1)

201128400 X. Patent application scope: 1. Figure 1 Arbiter is designed for hardware framework. Specifications, and its algorithm. , behavior, specifications, and its calculations 2 · PREEMPTIONm tile action, line horse, 3. TOKEN-GENERATION. 4· TOKEN—CONTROL The private method of the mold package. , action, ambiguity, specification, and deduction 5. It seems that the action of the m module, the external 仃, the specification, and its algorithm. 6. Table 1: Parameter setting and generation for six different arbiter. 12