TW201126522A - Memory device with field enhancement arrangement - Google Patents

Abstract

The present invention provides a memory device comprising a metal-oxide memory element in a current path between a first electrode at a first voltage and a second electrode at a second voltage; a nonconductive element adjacent to the metal-oxide memory element; a conductive element in the current path between the first electrode and the second electrode, the conductive element having a first part at a fist distance from the first electrode and a second part at a second distance from the first electrode, the first distance larger than the second distance, wherein the metal-oxide memory element is between the first part of the conductive element and the first electrode, and the nonconductive element is between the second part of the conductive element and the first electrode.

Description

201126522 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a S-remembrance device, and more particularly to a memory device having a field-enhanced arrangement. [Prior Art] Resistivity is a promising non-volatile memory. You, Lei, published in IED^Ipp. 771-774, 2007, "2 stacking ro_iR with oxide diodes as a switching element for high-density resistive memory applications, and; =〇 S S S S 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 In US Provisional Application No. 61/296,231, January 19, "WOxRRAM has promising memory characteristics. The memory in question has a plug shape and a relatively high current when forming memory cells. According to the invention, a main object of the invention is to provide a memory device having a metal oxide memory device, a non-conductive component and a conductive component. The metal oxide memory component is located at one. a first electrode of the first voltage, in a current path between a second electrode having a second voltage. For example: ^The first and second electrodes are upper and bottom electrodes. Other embodiments may have different electrical ,arrangement. a non-conducting element adjacent to the metal oxide memory and body element. In the embodiment, the non-conducting element comprises an oxide of a pad on the second electrode. The element is located at the first The current path between the electrode and the second electrode is in the embodiment of the present invention. The conductive element includes a spacer on the second electrode, 201126522, and a Wei-Plug plug. The material is; and the second electrode The first-P blade is such that the first-distance is greater than the second distance. The first-component is located at the first portion of the conductive element and the second-electrode enhances the metal oxide memory component adjacent to the non-conductive element, and is included in the Metal oxide memory secret implementation

And the circuit of -, _. In another embodiment, the normal operation U 5 does not perform the forming operation with the reset operation setting operation. ‘It is the benefit of the enhanced electric field of the 2L, 7L. In the embodiment, the reset operation has a relaxation in the setting operation. In another implementation, the coughing operation and the setting operation have opposite voltage polarities. μ heavy or one object read, month ^ - the purpose is to provide a manufacturing - record; value 1 Γ!, · wide above the first electrode - the formation of the recess - the pass - brother - conductive material and - the second conductive material; Forming the first conductive material of the memory device from the first:f electrical material to form the second conductive material of the memory device - non-conducting tillage, = = the non-conducting element; Forming a second electrode over the metal oxide body 7G and the V70 member such that the first electrode is between the conductive element and the remaining material of the second electrode a second thickness between the first thickness and the second thickness of the second embodiment, by oxidizing a surface of the conductive element, performing the step of forming a metal oxide memory read and forming the non- The steps of the material component. The actual step of the 201126522 surface forming the conductive element includes forming a memory having a table in the table; determining = path = gold! = 吏; setting (5): to = inverse: 5; new == = = wide; in the example, the second electrode is oxygen inert. Oxygen-inert electrode and electrode on the pole = guide step: in the bottom of the electric shape, ====: part of the electrode surface ^ In various embodiments, the method of manufacturing - anti-oxidation or -__ bracket - memory The turn of the cell. Second, = body 3 package Memory cells disclosed herein. * Early 歹 π (10) money body cells are included in the [Embodiment]: The description of the column disclosure will typically be referred to the implementation of the specific structure + the implementation method should be understood 岐 without any yan to _ county. I. EMBODIMENT AND METHODS However, other features and elements can be used in the disclosure. The preferred embodiment is described to make the current disclosure, and is not limited to 201126522. Those of ordinary skill in the art will recognize various variations of the temple in the following description. Elements as in various embodiments are collectively referred to the reference numerals. 1,1 ^ use of the present invention § memory cells to implement a cross-point memory array, schematic diagram, each memory cell contains a diode access device I - memory element based metal oxide . /,

As shown in the schematic diagram of FIG. 1, each of the memory arrays 1 含 includes a diode access device and a memory device-based dioxograph 1 is represented by a variable resistor. One) is configured to be connected in series in a current path between a corresponding word line 110 and a corresponding one bit line 12A. As described in more detail below, a memory component in a given memory cell is programmable to a plurality of resistive states including a first and a second resistive state. The memory array 100 includes a plurality of word lines 110 including word lines 110a, s, 11, and sub-lines ii 〇c extending in parallel in a first direction. The memory array 丨 (10) further includes a plurality of bit lines 12 〇 ' including bit lines 120a, bit lines 120b, and bit lines 120c extending in parallel in a second direction perpendicular to the first direction. The memory array 100 is referenced to the cross-scale column because of the word line u. And the odd line 12 互相 are mutually wrong, but there is no intersection on the entity, and the memory cell is located at the intersection of the word line 110 and the bit line 120. The memory cell 115 represents a memory cell of the memory array, and is disposed at a position of the intersection of the word line 110b and the bit line 12〇b, and the memory cell 115 includes one The pole body 13〇 is arranged in series with a memory element 14〇. The diode 140 is electrically coupled to the word line 11〇b, and the memory element 14() is electrically coupled to the bit line 120b. The memory cell 115 read or written to the memory array 10 can be induced to generate a current through selection by applying an appropriate voltage pulse to the corresponding word line 11 〇 b and the bit line 12 〇 b The memory cell is reached 115. The degree of voltage applied is dependent on the operation performed during the period. For example: a read operation or a program operation. 201126522 丄 图 曜 曜 曜 曜 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流 电流The cell το 115. The data value can be determined, for example, by comparing the appropriate reference current on the bit line _ (refer to, for example, the sense amplifier/data of structure 24 in FIG. 9). A data value is stored in the programming operation of the memory cell n5, the bias circuit (please refer to 'for example, the bias surface supply in FIG. 9, the f current source is lightly coupled to the corresponding word line 11Gb and the bit The line (4) applies a biasing arrangement across the memory cell 115 for amplitude and duration to sense a change in program control in the memory element (10) to store the data value in the memory cell 115. The electrical resistance of the body element 140 corresponds to the data value stored in the memory cell 115. The biasing arrangement includes a first biasing arrangement sufficient to bias the dipole in a forward direction Body 13〇 and corresponding to the resistance corresponding to the first programmed state In a second programmed state, the resistance changes the resistance state of the memory component 140. The biasing arrangement also includes a second biasing arrangement sufficient to forward bias the diode 130 and corresponding to the first programmed The resistance of the state changes to the resistance state of the memory element 140 to a resistance corresponding to the first programmed state. Each bias configuration for unipolar operation of the memory element 14A in an embodiment may include one or more A plurality of voltage pulses, and the degree of voltage and the number of pulses can be determined empirically for each of the embodiments. Figures 2A and 2B show memory cells arranged within 1交叉 of the array of intersections (including representative memories) A partial cross-sectional view of one embodiment of a cell 115), FIG. 2 is a cross-section along the bit line 120, and FIG. 2A shows a cross-section along the word line. Referring to Figures 2A and 2B, the memory Cell 115 includes a doped semiconductor region 132 located within word line 110b 201126522. Word line li〇b contains a doped semiconductor species having a conductivity profile opposite that of doped semiconductor region 132. Thus, in the doped 'half A PN junction 134 is defined between the conductor region 132 and the word line 110b, and the diode 13 includes the doped semiconductor region 132 and a portion of the word line ii 〇b adjacent to the doped semiconductor region 132. In the illustrated embodiment, word line 11 〇 b contains a doped p-type semiconductor material such as polysilicon, and the doped semiconductor region 132 contains a modified N-type semiconductor material.

In another embodiment, the word line 130 may include other conductive materials such as tungsten, titanium nitride, tantalum nitride, aluminum, and the diode may be on the top of the word line 11 and have different electrical patterns. One and the second doped region are formed. In yet another embodiment, the two lightly doped regions can be positioned between a plurality of highly doped regions of opposite conductivity to form a germanium diode, which is observed to improve the breakdown voltage of the diode. . The memory cell 115 includes a conductive element 15〇 extending through the dielectric 170 to couple the diode 130 to the memory element 14A. In the case of a small implementation, the material element (9) contains _ * and is recorded with the element 14 〇 ^ tungsten oxide WOx. The memory element 14G is surrounded by a layer of titanium nitride 15qa tantalum nitride and titanium nitride. Other substances can also be used as a cushion. In the illustrated embodiment, the formation of the memory element 14? containing tungsten oxide includes direct electrical oxidation, downstream oxidation, thermal diffusion oxidation, surface, and inverse. The oxidative (4) embodiment includes pure oxygen: an action such as oxygen/nitrogen or oxygen/nitrogen/hydrogen. In the next "oxidation-reality", the downstream reliance is applied about 15 (8) ears ^. The 1000 watt power, oxygen to gas flow rate ratio is between 〇 i and ^ η ΐ and f continues for 10 to 2000 seconds. See, for example, U.S. Patent, which is incorporated herein by reference. This process also causes the layer b〇A to oxidize to form a field-enhancing element 999. The field-enhancing element 999 contains the nitrogen of the memory element of the electrode Titanium oxide TiN〇X: The crane oxide touches the shape of the thicker layer of the titanium oxide layer. The shape is 201126522 ί: 穿 穿 Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕: The thickness of the medium to the top of the tungsten plug. Because of the distance: : Η = ΐ : The electric field between the upper electrode and the tungsten plug is larger than the tungsten "diameter", or the upper surface is strengthened. The entire memory element surface is evenly increased by the increase of / a becomes seven. In another embodiment, the memory element 140 can be packaged = 2 Wx # ' can be selected to be its _ yuan please - H The bit 120 includes the bit 120 as the upper electrode of the memory cell 115 electrically connected to the memory element 140, and the pixel 120 can be included and the uranium line 120 can contain uranium or other high Ξ ί The bungee and the conductor may be titanium nitride, mirror, money, Ji, 镧, ϊ, 钛, titanium: bismuth, chromium, vanadium, zinc, tungsten, molybdenum, copper, bismuth, antimony, money, and the like. The high work function electrode reduces the switching current of the operation. = For example, the operating current at 60 nm drops below 1 〇〇 microamperes and the switching speed is straight for two microseconds, which can be expected at 85. ° has greater than 3. . The period of preservation of the year. Moreover, the upper electrode having a similar free energy of formation can improve the preservation property. The dielectric 174 separates adjacent bit lines 12 (in the illustrated embodiment, the dielectrics 、0, 172 contain tree oxide. However, other dielectric materials may also be used. The cross-sectional views from Figures 2A and 2B may It can be seen that the memory cell of the array 1〇〇 is at the intersection of the word line 110 and the bit line 12G. The intersection of the word line 110b and the bit line 120b is represented by the symbol (4) cell ιΐ5 201126522. In addition, the memory element 140 and the conductive elements 150, 160 have a first width that is substantially the same as the width 114 of the word lines (see FIG. 2A). Note that the element 14 and the conductive element 15 〇, W0 has a second width, which is substantially the same, and the width 124 of the bit line 120 (see Fig. 2B) is the same. The term "real = up" as used herein is intended to accommodate manufacturing tolerances. Therefore, the cross-sectional area of the memory blister 2 of the array 10 is completely determined by the word lines 110 and the bit lines 12. The array 100 can have a high memory density.

The word lines 110 have a word line width 114, and the word lines Π0 are separated by a word line separated by a distance u (see FIG. 2A > the bit line 12 〇 has a bit line width of two 124, and is determined by a bit line * Separation distance 隹 122 separates adjacent bit lines ^ 2B). In a preferred implementation, the word line width 114 is separated from the word line by twice the feature size F of the array process, and the sum of the bit width = the bit line distance 122 is equal to the feature. Double the size F. A minimum feature size for determining the shape of the Lai Ke line 110 and the i-plane line 12G, such that the array has a 4F memory cell area. The memory array 100, the memory element 140, and the memory element 140 are formed by a more detailed manufacturing embodiment, and the memory "疋,,, is formed by oxidation of the material of the Vtl member 150. Receiving the corresponding word line _ and the bit bias line of the bit line 120b, _, _ yuan 115, = 140 in the resistance state of the sense-programmable variable ί Ϊ 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 The data of cell 115 is the same as that of the memory cell. Figure 3 shows the word line U0 on the substrate and the first on the word line 2011 2011 201126522 into the medium 170. In a cross-sectional view of the steps, the word line n〇 extends from a first direction and is shown in cross section. The illustrated embodiment contains a heterogeneous semiconductor material having a word line width 114 and is separated by a word line separation distance 112. Word line. Next, a bias array 600 having a width 610 is formed on the word line 11 of the exposed portion of the dielectric 17 . The doped semi-conducting well W is at word line η. For example, it is formed by ion implantation, and the resulting structure is shown in the cross-sectional view of Fig. 4Α_4β. The doped semiconductor region m has a conductive-like body region 132 opposite to the word line 11A and the word line 110 defines a PN junction 134, and the second H-guided domain 132 is from the nucleus conductor region ίί=FIG. 4A-4B The middle conductive element 150 is a structure shown in the cross-sectional view of the forming member 150 in the through hole 6A. The conductive element 150 in this embodiment includes a material county, and can be planarized by a via hole 6 如, such as chemical mechanical polishing to form a phase deposition material, the crane enhancement element 999==i=f remaining Partial self-alignment results in an additional mask to form the memory element 140 as shown in the cross-sectional view of FIG. Thereafter, the metal oxide memory element 140 is subjected to a gas of a gas, a hydrogen gas or an argon gas at a temperature higher than that of the gift of the second element = to d any suitable _ wire solid f 12 201126522 system). The time, temperature and pressure of the exposure process depend on several factors, including the system used, and the differences in the various embodiments. For example, the temperature range can be from 15 〇 to 500 ° C, time from 10 to 10,000 seconds, and pressure between 10 _ 5 and 10 Torr. Referring to Figures 11A-11B in detail, the cured metal oxide memory device 140 described herein is illustrative of improved metal oxide memory device 14 conversion performance and cycle durability. The turn-to-form work function bit line 130 is separated from the dielectric 174 by, for example, physical vapor deposition, and formed on the structure as shown in Figs. 6A-6B, resulting in an array of cross-points as shown in Figs. 2a-2B. In some embodiments, the selective exposure process for the Lu metal oxide memory device 140 described with respect to Figures 4A-4b can be substituted for operation on the bit line 130. A bias voltage circuit, such as a supply voltage and/or current source, can be formed on the same device, such as a S-resonance element, and lightly coupled to word line HQ and bit line 12 for applying the bias configuration described herein. . Forming the bit line 130 and the dielectric 174 can form a dielectric on the bit line 130 by forming the bit line material into the structure of Figures 4A-4B, and performing a planarization process such as chemical mechanical polishing. After FIG. 6B, an upper electrode having a conductor is formed. 7 is a simplified flow chart of an integrated circuit 1A of the present invention, the integrated circuit 1 includes a cross-point memory array of a memory cell, and the memory cell includes a gold-based oxide-based oxide Memory component and a diode access device. Word line decoder 14 is coupled to a plurality of word lines 16 and is in electronic communication. A bit line (row) decoder 18, the complex f bit lines 20 are electronically communicated to fetch and write data from memory cell (not shown) entries in array 100. The address is supplied to the line 22 to the word line decoder and driver 14 and the bit line decoder 18. The sense amplifier and data entry in block 24 is coupled to bit line decoder 18 via data line 26. The data is supplied from the input/output ports on the integrated circuit, or from other sources within or outside of the integrated circuit 10, through the data entry line 28 to the data in block 24 into the structure. Other circuits 30 may be included in the integrated circuit 10, such as a general purpose processor or special purpose, application circuit, or combination of modules to provide system functions on the wafer supported by the array. From the sense amplifier in block 24, by means of the data 13 201126522 10 internal or (10) into _, or integrated circuit configuration 4 configuration power (four) & config state machine, control the processor executed in the same integrated circuit use, Can be done. In another device that controls the device with γ 丨 仃 仃 仃 仃 可 可 可 可 可 可 可 可 可 可 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑The device memory device component 140 of the device can be cured by exposure to a gas comprising at least dinitrogen or argon. An oxide, such as titanium oxide, oxide oxide, 18 oxide, copper. Oxidation ί, oxide, silver gamma, chrome holding erroneous acid; pole ==:, relay, qing _ and high work function upper This device can not only use bipolar operation, but also use unipolar operation. The device may not be set or reset by an electric field of opposite polarity. The unipolar operation indicates that the device can be set or reset by an electric field of the same polarity. Figure 8 is an example memory cell with an electric field enhancement arrangement. A simple schematic diagram of 0 <, a δ-remembered body such as an anti-oxidation ram or a magnetic wear-resistant surface has a field, strong alignment. The memory cell has an upper electrode and a bottom electrode, and the i-memory elements are arranged in Current between the upper electrode and the bottom electrode Electrical series in the path. ~ Electrical series in the current path between the upper electrode and the bottom electrode, a conducting element or conductor having a "U" shaped cross section. The concave portion of the "u" shaped face of the conducting element is located The upper electrode is at a distance dl from the first distance, corresponding to the 201126522 thickness cn of the memory element. The σ of the conductive element is thicker than the distance calculated by the upper electrode, and dl is from the upper electrode to the conductive element The U-shaped section _ at the portion of the first turn, (10) is the second distance from the upper word, the arm portion of the face, ϋ. The guiding electrode and the non-conductive insulator 1β can be the same or different materials. The material requirements for thin insulator 1 are high-resistance materials, such as in insulators, inner support == or titanium oxynitride (TiN〇x). In order to enhance the field, the thickness of d2, the narrower the width of the end Sr and the element, the higher the electric field generated at the end of the insulator 1 and in the S-resonance element. temU is a cross-sectional view of the electric field-like touch-example memory cell. (4) The TEM image of the L'60 leg device is characterized by metal oxide·〇χ as Ί. The upper portion of the memory element is a combination of a non-conductive insulator TiN0x and a (4) electrical tungsten plug and (8) a surrounding memory tree and a conductive conductive titanium nitride pad. In this embodiment

The field enhancement device arrangement of TiNcT, which is insulated by the oxide salt pad, is forced to protrude from the remaining TiN pads. And the ancient 2::" memory * complementary MOS semiconductor _ good _ capacitive, and ° however ' unlike the transition metal oxide, W0x exhibits a low starting resistance sink current, and severe _ its write bandwidth. Other transition metal oxide hybrid memories are different. Due to the temperature = under-oxide elimination, the leakage path is formed in the original WOx resistive memory device. A formation process changes the low resistance state to a high L. The operation requires high electric current and requires the correct polarity; the opposite polarity of the formation of the 2011 20112222 pulse cannot reach a high resistance state. X-ray photoelectron spectroscopy analysis of the W〇x resistive memory indicates that the w〇x resistance type 3 recalls The top layer of the surface of the body is mainly composed of W〇3, and its composition is changed to a mixture of W〇2 + W2〇5+W〇3 at a distance of about 2.5 nm below the surface. Conductive atomic force microscopy shows that the leak path can be borrowed. By applying a current through the tip of the atomic force microscope to eliminate 'the suggestion that the leak path is oxidized, the seal is caused by Joule heat. 2 The proposed mechanism for the formation process is: positive voltage draws negative 较低 from lower surface> And the porous oxide is converted to the insulating layer W. 3. The upper electrode is oxygen-inert. The following table shows that the oxygen-containing upper electrode (TiN, pt) reacts with the upper electrode (Al, Ti). , W) shows a high resistance 鲅/low resistance makeup cone of a preferred resistive memory.

Resistance window TiN / WOx 5KO-100 KO Pt / WOx 5 KO-1 MO A1 / WOx _ No conversion Ti / WOx 〇·3 KO-3 KO W/WOx __^2Κ0-1 KO The setting/reset mechanism is described below. For the set operation, one or more of the bridges of the upper and bottom electrodes are produced by electrochemical oxidation reduction. The t = wo3.n layer produces a low resistance state. For the reset operation, the w〇3n filament ^ $2 straw is converted to the absolute _ W〇3 by the same mechanism that forms the program (by the deeper pull 2). Therefore, initially only on the unguarded device with a large number of _ paths 'Into a special reset. The resistance determines the layer close to the upper m surface. Therefore, the completely sealed by - normal weight, rush to achieve. For a variety of different 2 1 〇〇 nm) device implementation set and current display = 16 201126522 There is no or very weak dependence on the size of the device, suggesting that the reset and settling mechanism of the wox resistive memory is governed by the formation and splitting of the filament during the redox reaction. The 50 ns reset pulse has an intermediate reset voltage maintained at approximately ΐ 3 ν and a constant current held at approximately 0.65 mA. The initial resistance distribution is compared to the 50 most recent 180 fine w〇x resistive memory devices and the 50 nearest 60 nm WOx resistive memory devices. At 60 nm, the initial resistance is higher with a broad distribution (l〇gR between 3.8 and 65) and very tight for a 180 nm device (log R between 2.5 and 3·〇). This can be explained by the density of the leak path. If the leak path density is close to a single number in the area of 6〇nm χ 6〇nm Lu, then this distribution is expected from statistical fluctuations. The tight program voltage distribution is due to the setting and reset operation of the WOx resistive memory cells from 50, 60 nm. For the reset (resistance approx. l00k〇hm), the average voltage is 1.91 V ' standard deviation 0.31 V ' and for the setting (resistance approx. 10 k〇hm) the average voltage is 1.31 V with a standard deviation of 0.22 V. The current-time plot of the transient current shows that the 50 ns reset and set pulse performed well on the 60 nm WOX resistive memory cell. Multilayer wafer operation with 6〇nmW〇x resistive s-resonant cells can be achieved' to create two additional layers between 2〇κ〇 and 80KO in at least four layers, and the durability of the multi-layer wafer >1〇4 loop. % >51()9 reads the number of excellent reads disturbing the presence of immunity at a typical level of about 1.5 χ 10 ohms in a reset state of 0.25V 'usually about 2.0 x 1 〇 5 ohms at a weight of 0.5 V Set the state, usually the level is about 7.5 χ 103 ohms in the reset state of 0.5 V. Figure 10 is a diagram of the diameter of the electric field vs memory cell at the center, which is simulated and reset by the exemplary memory cell, both with and without an electric field enhancement arrangement ^ The example memory cell that does not have the electric field enhancement arrangement is referred to as a rod-like structure. In the rod-like structure, the conducting element lacks a "U" shaped cross section and is instead a simple rectangular cross section with a plug. The example memory cell that does not have the electric field enhancement arrangement is referred to as field enhancement 17 201126522 Structure 1 Because the two-armed pole of the "u"-shaped cross section of the conductive element is on the upper electrode and the conductive element The electricity of the P electric (1) has a more extreme tip of the "U"-shaped cross section than the rod-like structure. It will be even more questioned that the electric field of the size of the ’wc>x can be quite high when the size of the element is close to the conduction element. Near the edge One shape Reluctantly has a memory element of 1011111 to 10011111 diameter' showing the distance between the wide and the center of 70 pieces of the § memory. For the application of L5 v'. Day ~ Wei body 7C size depends on about 2Qnm, the data display field is substantially enhanced, the various diameters of the body components range from 1〇〇nm, 8〇nm6〇nm, 4〇nm, L1GlUn°U will memory cells The center of the Yuan is missing. Figure 11 indicates that at the time of ί, the two arms of the "u"-shaped cross section of the conducting element will correspond to the radius of the memory cell (half the diameter) of the side of the t冋屯琢. - 4 «^ 12 is a two-dimensional map of the electric field simulated by an exemplary memory cell with an electric field enhanced arrangement of 1 〇 0 plus 1 diameter. 4« &Fig. 3 is a two-dimensional map of an electric field simulated from a 20-torn 11-diameter exemplary memory cell with an electric field enhancement arrangement. ", t, Fig. 12 and Fig. 13 also show that when the size of the plug is repaired, the arms of the U-shaped wearing surface of the conducting element will be closer, and the high electric field of the two arms of the "U" shaped section of the conducting element is gradually The augmentation is concentrated in the center. Figure 1. 4 is a pulse voltage diagram of experimental results of a sample memory cell of various diameters with electric field enhancement arrangement in a forming operation. 201126522 Figure 15 is an arrangement enhanced by an electric field. The current graphs obtained from the experimental results of various diameters under various operations. The money and body cells in Fig. 14 and Fig. 15 show that when the cell size increases, the initial shape voltage and current decrease rapidly. Therefore, in (8) lung or below, In the case of such a small memory cell size, the control circuit does not operate, and the different forming operations with the command code are different from the command codes of the regular or reset operation. Instead, , can perform regular operations. Figure 16 is arranged by electric field enhancement

The example of 60 nm diameter ^, ρ _ _ in the reset and set the money (4) read ring under the real riding voltage period diagram. .s. Service Scale Figure 16 indicates that such small memory cells do not require different forming operations. A graph of the resistance vs. cycle number of a 60 nm-diameter sample memory cell with an enhanced electric field in a multi-cycle with a weight of 5 and S. ^ 17 indicates that the cycle endurance of the 60 nm device is greater than one million times. In the reset/set operation of one million cycles, the reset/set resistor window remains well separated. Approximately 10 times the resistance window can be properly maintained by a program validation algorithm. Figure 2 is a graph showing the resistance v.s. retention time for a 6Gnm straight (four) example memory cell 70 with an electric field enhanced lake after a consistent heating period. The present invention is described in detail by the preferred embodiments, and is not limited to the scope of the present invention, and is therefore known to those skilled in the art. It should be noted that the appropriate changes and modifications of the present invention will remain without departing from the spirit and scope of the present invention, and should be considered as further implementation of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS 19 201126522 FIG. 1 is a partial schematic view of a cross-point memory array using memory cells of the present invention. Figures 2A and 2B are partial cross-sectional views of one embodiment of a memory cell arranged within a cross-point array 1A. 3-6 illustrate a fabrication sequence step for fabricating a cross-point array of memory cells as shown in Figures 2A-2B. 7 is a simplified flow diagram of an integrated circuit of the present invention, the integrated circuit including an array of intersections of memory cells including a metal oxide based memory component and a diode access Device. Figure 8 is a simplified schematic diagram of an exemplary memory cell having an electric field enhanced arrangement. . Figure 9 is a cross-sectional TEM image of an exemplary memory cell having an electric field enhanced arrangement. #图10 is a diagram of the true path of the electric field vs. memory cell in the center, which is reset and set by the simulation with the example 5 memory cells, both of which have and do not have an electric field. Enhance the arrangement. 1. Figure 11 is an electric field diagram of a cross-sectional view simulated by a plurality of diameter exemplary memory cells having an electric field enhanced arrangement under a forming operation. Figure 12 is a two-dimensional map of an electric field simulated from an exemplary memory cell of 100 gastric diameters with an electric field enhanced arrangement. Figure 13 is a two dimensional diagram of an electric field simulated from an exemplary memory cell of 2 〇 nm diameter with an electric field enhanced arrangement. Figure 14 is a pulse voltage diagram of experimental results of a sample memory cell of various diameters having an electric field enhanced arrangement under a forming operation. , 15 is a current diagram derived from experimental results of exemplary memory cells of various diameters with enhanced electric field alignment under various operations. 201126522 Figure 16 is a graph of the resistance v.s. pulse voltage period from the experimental results of a 60 nm diameter sample memory cell with an electric field enhanced arrangement under multiple cycles of reset and set operation. Figure 17 is a graph of resistance vs. number of cycles from a plurality of cycles of reset and set operations of a 60 nm diameter example memory cell with an electric field enhanced arrangement. Figure 18 is a graph showing the resistance v.s. retention time for a 60 nm diameter example memory cell with an electric field enhanced arrangement after a substantial heating period. [Main component symbol description] 100 memory array 120, 120a, 120b, 120c bit line 130 diode 132 doped semiconductor region 170, 172, 174 medium 999 field enhancement element 114 word line width U2 sub-line separation distance 600 conduction Hole 1〇 integrated circuit 16 plural word lines 2 〇 plural bit lines 26 data lines 30 other circuits 34 controllers 110, 1103⁄4 110b, 110c word lines 115 memory cells 140 memory elements 134I > N joint 150A mat 150,160 conductive element 124 bit line width 122 bit line separation distance 610 bias array width 14 word line decoder I8 bit line (line) uncle crying 22 line 28 data entry line 32 data round line 36 bias Configure the supply voltage 21

Claims (1)

201126522 VII. Patent application scope: h—a memory device comprising: - a metal oxide memory tree, located between an electrode having a -first voltage and a current having a second electrical system - a second electrode In the path; a non-conducting element adjacent to the metal oxide slimming element; conducting the current between the first electrode and the second electrode, the transmitting member having a first distance from the first electrode And the distance from the second electrode to the second electrode is greater than the second distance, and the music processor element is located at the first portion of the conductive element. The memory device of the second aspect of the present invention, further comprising: performing an operation on the operation of the oxide element and resetting the operation, and a setting of the path. The reset operation and the setting operation have a total of _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The electrical test. The memory device of the first item further includes: an operation genus, an execution-reset operation on the object memory device, and a setting of the setting for the re-setting operation and 5. The memory device described in the first aspect of the invention, wherein the non-conducting element 7 is on the second electrode, the bismuth-oxide. Including: a memory device' wherein the conductive element head.一 a lining on the bungee, and a plug in the lining 22 201126522 = the memory device, wherein the memory device is 9. The memory device is described in the memory device. A method of a memory device, comprising: forming a conductive element in a recess above the first electrode, the first conductive material and a second conductive material, and the first one of the first conductive element The conductive material forms an oxide recording element; & Forming a non-oxide memory component adjacent to the non-conductive component from the second conductive material of the conductive element; and the metal oxide memory component is interposed between the metal oxide memory component and the conductive component In the method of the present invention, wherein the conductive element is formed into a conductive layer having a surface, the surface comprising the conductive material The first conductive material is adjacent to the surface of the first conductive material according to the method of claim 12, i.e., iG, the cap is oxidized by the conductive bismuth; the same is performed to form the metal oxide (4). The method of the towel-shaped conduction = forming the conductive tree having a surface, the surface comprising the first conductive material on the surface adjacent to the electrical material, wherein the straw is oxidized by the surface of the conductive element - The metal oxide memory device is formed and the non-conductive element is formed. 14. The method of claim 10, further comprising: forming a circuit on the metal oxide memory device - a reset operation and a circuit of 23 201126522, wherein the four scales and the mosquito operation have - The method of claim 5, further comprising: forming a circuit for performing a reset operation and a setting operation on the metal oxide memory device, the resetting operation and the setting operation device ^The opposite voltage polarity. 16. If the method described in the patent application section 1G is applied, a forming operation different from the determining and resetting operation is not required before the setting and resetting operation of the normal use of the memory cell. , °^ 17. The method of claim 10, wherein the second electrode is oxygen inert. 18. The method of claim 1, wherein the forming the non-conductive element comprises: oxidizing a conductive image of the conductive element on the bottom electrode. The method of claim 10, wherein forming the conductive element comprises: forming a conductive pad on the bottom electrode; and forming a conductive plug in the conductive pad. 20. The method of claim 10, wherein the memory device by the method is an anti-oxidation RAM. 21. The method of claim 10, wherein the memory device manufactured by the method is a magnetic tunnel junction RAM. 22. A memory device comprising: a memory cell intersection point array, the memory cell in the array comprising: a metal oxide memory element located at a first voltage first a non-conducting element between the electrode and a second electrode having a second voltage; a non-conducting element adjacent to the metal oxide memory element; a conducting element located at the first electrode and the The S 24 between the second electrodes 2011 26522 In the current path, the conductive element has a first portion at a first distance from the first electrode and a second portion at a second distance from the second electrode, the first distance being greater than the second distance, wherein The metal oxide memory component is between the first portion of the conductive component and the first electrode, and the non-conductive component is between the second portion of the conductive component and the first electrode. 25