TW201123746A - Modulator with loop-delay compensation - Google Patents

Abstract

The present invention is directed to a modulator with loop-delay compensation. A delta-sigma modulator generates a quantization code, and a digital compensation filter receives the quantization code and outputs a digital code. The digital compensation filter then feeds the digital code back to the delta-sigma modulator.

Description

201123746 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a delta-sigma modulator, and more particularly to a delta-sigma modulator with a digital auxiliary compensation filter. [Prior Art] [0002] A delta-sigma (AE) or sigma-delta (2 Δ ❹ ) modulator is a feedback system that uses a simple circuit function block to generate a high resolution. Triangular integral modulators are commonly used in a variety of electronic circuits, such as analog-to-digital converters (ADCs), digital to analog converters.

(DAC) or frequency synthesizers, B Because of the simplicity and low power consumption of the delta-sigma modulator, it has also received considerable attention in the field of wireless communication. [0003] The number-war model of the ideal continuous-time (third-order) delta-sigma modulator is shown, where Ai, Az and As are feedback DAC coefficients, fs is the sampling frequency, X(s) is the input signal, and E(z) is the quantization miscellaneous News, while γ(ζ) is the round out %. However, in the actual circuit environment, there is a avoidance delay in the feedback path. The loop delay will cause the pole shift of the modulation system, which in turn changes the original noise-transfer-function (NTF). To solve the aforementioned problem, the analog compensation path can be increased by 1 £, as shown in the first B, where rd is the loop delay, and k2 and k3 are the feedback DAc coefficients considering the feedback delay. However, increasing the analog compensation path kf not only increases the additional energy consumption, but also increases the distortion caused by the extra analog circuit. [0004] In view of the fact that traditional analog compensation techniques cannot effectively solve the problem of loop delay, it is imperative to propose a novel mechanism that can be represented by the exact number 098145722. Form number A0101 Page 3 of 22 page 0982078049-0 201123746 The circuit replaces the analog circuit' to solve the loop delay problem. SUMMARY OF THE INVENTION [0007] In view of the above, one of the objects of embodiments of the present invention is to provide a compensation filter for overcoming the loop delay in a delta-sigma modulator without using an additional Analog circuit. According to an embodiment of the invention, the modulator mainly comprises a continuous time delta-sigma modulator and a digital auxiliary compensation filter. The delta-sigma modulator includes an integrating circuit, an analog-to-digital converter (ADC), and a digital analog converter (DAC). An analog digital converter (ADC) receives the rounding of the integrating circuit to generate a quantized code. The compensation filter receives the quantized code to generate a digital code and feeds it to a digital analog converter (DAC), the output of which is fed to an integrating circuit. [Embodiment] The functional block diagram of the first A diagram shows the continuous time (continu〇us_time, ct) trigonometric integration (delta-sigma (A2) or sigma-deita (ΣΑ)) of the compensation filter 22 of the embodiment of the present invention. Modulator 20. The second B diagram shows an equivalent mathematical model or a frequency domain model of the functional block diagram of the second a diagram. For the analysis of the above mathematical model, reference may be made to the document "Compensation filter for the excess-loop delay of a delta-sigma modulator" disclosed by YU_YU Chen (one of the inventors of the present application). In the present embodiment, the delta-sigma modulator 2 includes an integration circuit 200 and an analog-to-digital converter (ADC) (or quantizer) 2〇2' on the forward path and a digital analogy on the feedback path. Converter (DAC) 2〇4. The integration circuit 200 includes a plurality of integrators 2001 connected in series. In general, 098145722 Form No. A0101 Page 4 of 22 0982078049-0 201123746 ❹ [0008] The delta-order delta-sigma modulator 20 has n integrators 2001. An adder 2003 is interposed between each two adjacent integrators 2001, and the first integrator 2001 also has an adder 2003. Each adder 2003 receives the output signal of the previous integrator 2001 (for the first adder 2003, the received (analog) input signal X), and subtracts the output signal of the DAC 204, and outputs the differential signal to the next one. Integrator 2001. The ADC 2〇2 receives the output signal of the integrating circuit 200, converts it into a quantized code q, and outputs it to the compensation filter 22. The DAC 204 receives the (digital) output code y generated by the compensation filter 22, converts it into an analog signal, and outputs it to the integration circuit 200. The third A diagram shows the compensation filter 22 of the second A diagram in the embodiment of the present invention. Detailed function block diagram. The third B diagram shows the equivalent mathematical model or frequency domain model of the third A graph. The compensation filter 22 is a digital auxiliary loop filter that subtracts the continuous quantization code q[nl] output from the ADC 202 and q[n] to generate a differential code y[n], that is, y. [n]=q[n]-q[nl ]. In the present embodiment, the compensation filter 22 includes an adder 220 for subtracting the current quantized code q[n] from the delayed quantized code q[n-1] (which is generated by the delay element 222). In the field of Ζ, the conversion function of the compensation filter 22 can be expressed as 卜z_1 (as shown in the second B). The transfer function l-zM of the compensation filter 22 can be used to compensate for the pole offset caused by the loop delay of the actual feedback path of the delta-sigma modulator 20. In the s field, the equivalent conversion function can be written as: 1 ~z-1 ~s/ f

S where f is the sampling frequency and s/f is used as the differentiator.

S S

[0009] In this embodiment, the coefficients of the DAC 204 (as shown in FIG. 2B, 098145722 Form No. A0101, page 5/22 pages 0982078049-0 201123746 2...kf) can be compensated by conventional analog techniques (eg, Directly shown in Figure B). The fourth figure illustrates a second-order (that is, three integrators 2001) triangular integral modulator 2〇 with a compensation filter 22 according to an embodiment of the present invention, and simultaneously displays a conventional second-order triangular integral modulation with analog compensation feedback. The DAC coefficients of the two integrators 4001 are , and , and the compensation coefficient is kf. These coefficients k, 1, and 1 can be used as the three DAC coefficients k 〆 and kf (shown by the dashed arrows) of the three integrators 2001 of the triangular integral modulator 20 of the present embodiment, respectively. In general, the DAC coefficients of the n-th order delta-sigma modulator of this embodiment can be directly obtained from the DAC coefficients of a conventional (N-1)-order delta-sigma modulator with analog compensation feedback. [0010] For the design of the analog feedback DAC coefficients of the conventional delta-sigma modulator, reference may be made to the following document 'A Continuous-Time Sigma-Delta as disclosed by S. Yan and E.. Sanchez-Sinencio et al. Modulator with 88-dB Dynamic Range and 1. MHz Signal Bandwidth", ISSCC Dig. Tech. Papers (February 2003), pages 62-63, as revealed by P. Fontaine, AN Mohigldin and A. Bellaouar et al. "A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop DelayM » ISSCC Dig. Tech. Papers (February 2005), pp. 498-499, and by G.

Mitteregger et al., "A 14b 20mW 640 MHz CMOS CT Δ Σ ADC with 20MHz Signal Bandwidth and 12b ENOB", ISSCC Dig. Tech. Papers (February 2006), pp. 131-140. 098145722 Form No. A0101 Page 6 of 22 0982078049-0 201123746 [0011] ο [0012]

[0013] Q

[0014] 098145722 The fifth figure illustrates the implementation circuit of the second or third compensation filter 22. In the present embodiment, the quantization code q is a thermometer code. The current quantized code q[n] output by the 4-bit ADC 2〇2 and the previous quantized code “difficulty” output by the register 50 are fed together to an exclusive-OR or an exclusive-OR (hereinafter referred to as x〇). R) Gate array 52 to produce an absolute value of (1-z), i.e., 丨1-ζ-ι丨, having a pattern of consecutive "1''s. The actual value of 丨1-Z-1丨 is the number of consecutive “丨,. For example, the actual value of the pattern (00001 10000 0000) is 2. If the resolution of ADC 202 is 2N, then 丨izi丨 is required. The resolution is 2N-2. It is worth noting that in the transitional towel, the continuous performance will appear in random locations. For example, for the subtraction of 丨1-ζ-1 |, 7-5 and 3-1 (currently The value minus the previous value is 2, but the consecutive 1 positions of the logic X0R gate array 52 output are (C7, C6) and (C3, C2) respectively. The high logic level inputs of the DAC are (D1D3) and ( D1D2). This randomization will help to reduce the harmonic tones of the DAC mismatch. According to one of the features of this example, the number of "1 15 1" of the logical x〇R gate array output c_c is at most 3, The logic X0R gate array wheel Ci_ci5 is connected in a special way to two logical OR (01{) gates 54 with five inputs so that the outputs of adjacent sequence numbers are not connected to the same logic or gate 54. Again, using a subtractor 56 to generate a symbol control signal, which is combined with the turn-off signal Di of the logic or gate 54, and the heart and the 匕 are processed by the logic circuit 58 to obtain the control signal Dx. DY and Dz are used to control the switches of the DAC 204. Figure 6A shows the tri-state J) AC unit of the embodiment of the present invention, and the sixth B shows the different operational states of the tri-state DAC unit, wherein the signal h is the output of the logic or closure 54, and the control signals,,, and are the output of the logic 58 in the logic form number A0101 page 7/22 pages 0982078049-0 201123746. Where, when the signal 〇1 is at the high level Then, the corresponding DAC unit is selected and the control signal 〇2 will be at a low level. Then, according to the symbol control signal, the control signal DX4DY is at a high level. On the other hand, when the signal D. is at a low level, the corresponding The DAC unit is in an idle state and 1 has no current output, and the control signal Γ>ζ will be at a high level to maintain the current of the current source. [0015] The above description is only a preferred embodiment of the present invention, not The scope of the claims of the present invention is intended to be limited to the scope of the appended claims. a map display The mathematical model of the continuous-time triangular integrator is considered. The mathematical model of the first B graph shows the actual continuous-time triangular integral modulator with the analog compensation path. The functional block diagram of the second A diagram shows the compensation filtering of the embodiment of the present invention. The continuous time triangular integral modulator of the device. The second B diagram shows the equivalent mathematical model of the functional block diagram of the second A. The third A shows the details of the compensation filter 22 of the second A diagram in the embodiment of the present invention. Functional block diagram. The third B diagram shows the equivalent mathematical model or frequency domain model of the third A graph. The fourth figure illustrates a third-order three-angle integral modulator with a compensation filter according to an embodiment of the present invention, and simultaneously displays a conventional second-order triangular integral modulator with analog compensation feedback. The fifth diagram illustrates the implementation circuit of the compensation filter 22 of the second A diagram or the third A. 098145722 Form No. A0101 Page 8 of 22 0982078049-0 201123746 The sixth diagram shows a tri-state DAC unit according to an embodiment of the present invention. Figure 6B shows the different operational states of the tri-state DAC unit of Figure 6A. [Main component symbol description] [0017] 20 Triangular integral modulator 22 Compensation filter

200 integration circuit 202 analog-to-digital converter 204 digital analog converter 220 adder 222 delay element 2001 integrator 2003 adder 40 delta-sigma modulator 4001 integrator 50 register 52 logic XOR gate array 54 logic OR gate

56 Subtractor 58 Logic circuit X Input signal q Quantization code y Output Ma Dx, Ι) γ, 〇 2 control signal k!, k2, k3, kf coefficient 098145722 Form No. A0101 Page 9 of 22 0982078049-0

Claims (1)

201123746 VII. Patent application scope: 1. A modulator with loop delay compensation, comprising: a triangular integral modulator for generating a quantization code; and a digital compensation filter for receiving the quantization code and outputting A digital bit code, the digital compensation filter returns the digital code to the triangular integral modulator. 2. The modulator with loop delay compensation according to claim 1, wherein the above-mentioned delta-sigma modulator is a continuous time (CT) delta-sigma modulator. 3. The modulator with loop delay compensation according to claim 1, wherein the digital compensation filter generates a continuous differential code between quantized codes. 4. The modulator with loop delay compensation according to claim 3, wherein the digital compensation filter comprises: a delay element, according to a current quantization code q[η] to generate a delay quantization matrix q[ And n_l]; and an adder, subtracting the current quantized code q[n] from the delayed quantized code q[nl] to generate the output digital code y[n], expressed as follows: y[n]=q[n ]-q[nl] ° 5. The converter with loop delay compensation as described in claim 3, wherein the conversion function of the above-mentioned digital compensation filter in the Z domain is: l-z_1. 6. The modulator with loop delay compensation according to claim 3, wherein the conversion function of the above-mentioned digital compensation filter in the S domain is: s/f S where f is the sampling frequency. S7. The modulator with loop delay compensation as described in claim 3, wherein the digital compensation filter described above includes a differentiator in 098145722 Form No. A0101, Page 10 of 22 0982078049-0 201123746. A modulator with loop delay compensation as described in claim 5, wherein the quantization code is a thermometer code. The modulator with loop delay compensation according to claim 8 , wherein the digital compensation filter comprises: 暂 a register, which generates a delay quantization code according to the current quantization code; a logical mutual exclusion or An (XOR) gate array that receives the current quantized code and the delayed quantized code to generate an absolute value of (1-ζ_1) and the absolute value has a continuous "Γ pattern, wherein the absolute value of the (1-ζ_1) The true value is the number of "1"s in the continuous "Γ pattern"; and a plurality of logical ORs (for receiving the output of the logical mutex or gate array. ίο . with a loop as described in claim 9 The delay compensation modulator further includes: a subtractor that generates a symbol control signal according to the current quantization code and the delay quantization code; and ❹11. A plurality of logic circuits that receive the output of the logic or gate The symbol control signal is used to generate a plurality of control signals to control a digital analog conversion (DAC) unit of the delta-sigma modulator. As described in claim 1, the loop delay compensation is adjusted. The above-mentioned delta-sigma modulator includes: an integrating circuit; an analog k-bit converter (ADC) that receives an output of the integrating circuit for generating the quantized code and feeding the digital offset filter; A digital analog converter (DAC) that receives the digital code and returns the output of the digital analog converter to the integrating circuit. 098145722 Form No. A0101 Page 11 of 22 0982078049-0 201123746 12 . The loop delay compensation modulator according to Item 11, wherein the integration circuit comprises: a plurality of serially connected integrators; and a plurality of adders, wherein each of the two adjacent integrators is interposed between The adder, and each of the integrators has an adder before; wherein the adder receives the output of the previous integrator, but receives an input signal if the adder is the first adder; the addition The output of the digital analog converter is subtracted; therefore, the adder outputs a differential signal and feeds it to the next integrator. 13 . The transformer includes: an integrating circuit; an analog-to-digital converter (ADC) that receives an output of the integrating circuit to generate a quantized code; a digital offset filter that receives the quantized code to output a digital code; a digital analog converter (DAC) that receives the digital code and feeds the output of the digital analog converter to the integrating circuit. 14. A converter with loop delay compensation as described in claim 13 of the patent specification, wherein The above-mentioned digital compensation filter generates a continuous differential code between the quantized codes. 15. The modulator with loop delay compensation according to claim 14, wherein the digital compensation filter comprises: a delay element, according to a The quantization code q[n] is currently generated to generate a delayed quantization code q[η-1]; and an adder subtracts the current quantized code q[n] from the delayed quantized code q[nl] to generate the output digit The code y[n] is expressed as follows: y[n]=q[n]-q[nl] ° 098145722 Form No. A0101 Page 12 of 22 0982078049-0 As stated in the application of the 14th patent Circuit delay compensation modulator, where the digital compensation of the upper f Wave field in the Z transfer function is: which, as its spot profile 15 apply eye heart depends secret material back late compensation modulator of the above-described digital compensation filter comprises a differentiator. The above-mentioned digital compensation filter in the modulator with loop delay compensation as described in the patent scope (10) includes: a register 'which generates a delay quantization gamma according to the current quantization 玛; -, a mutexe or (_ The gate array 'receives the current quantized and the extended code to generate an absolute value of (] τ Ζ ) and the absolute value has a continuous 1 pattern, wherein the true value of the absolute value of (1-Ζ-1) is The number of consecutive " Γ patterns" 1"; and a plurality of logical ORs ((8) gates are used to receive the output of the logic mutex or gate array. As stated in the patent paragraph 11帛18 The modulator further includes: - a subtractor that quantizes the pigeon according to the current quantization code and the delay to generate a symbol control signal; and a plurality of logic circuits that receive the output of the logic or gate and the symbol control L number ' a digital analog conversion (DAC) unit for generating a plurality of control signals to control the delta-sigma modulator. For example, the above-mentioned integration circuit includes: a plurality of strings Connected product And a plurality of adders, wherein each of the two adjacent integrators is interposed with the adder, and each of the S integrators has a different one before; the form number Α0101 page 13 / A total of 22 pages 〇q85 201123746, wherein the adder receives the output of the previous integrator, but if the adder is the first adder, it receives an input signal; the adder subtracts the output of the digital analog converter; Therefore, the adder outputs a differential signal and feeds it to the next one. 098145722 Form No. A0101 Page 14 of 22 0982078049-0