201123443 六、發明說明： 【發明所屬之技術領域】 ’且特別是有關於一 本發明是有關於一種半導體元件 種雙载子電晶體。 【先前技術】 近年來隨著科技的進步，半導體產業蓬勃發展，相 提供之積體電路往往針對縮小尺寸為重要考量。因此，春 参t開發之積體電路的尺寸日益下縮，其組成元件亦隨之^ 小，而得以呼應產業需求。 然而，一般互補金屬氧化物（CM〇s)邏輯製程由於 成本及應用考量，並未提供特性良好的雙載子電晶體。在 不改變製程步驟及光罩數量的前提下，只能製造如傳統之 水平式（lateral)雙極性電晶體，其電流增益相當低，而且 此類雙極性電晶體的尺寸難以隨著製程進步而下縮。 由此可見，現有的雙载子電晶體顯然仍存在許多不便 與缺陷，而亟待加以進-步改進。為了解決上述問題，相 關領域莫不費盡心思來謀求解決之道，但長久以來一直未 見適用的方式被發展完成。因此，如何能在不改變製程步 驟以及不增加光罩數量下，提供一種相容於互補金屬氧化 物邏輯製程的雙載子電晶體，實屬當前重要研發課題之 一，亦成爲當前相關領域亟需改進的目標。 【發明内容】 201123443 程= 相，互補金屬氧化 加光罩數量下，可具有尺寸下縮的=製私步驟以及不增 依據本發明—實施例，—種雙載子電晶體包 -多雜區、第二摻雜區、第三摻雜區 隔物與插塞。 》电層閘極、間 區位ΐ第结構上第==::別:—其中第二摻雜 間隔物位於間極與介電層外圍，： :二=位於井中。另外，第-摻雜區與第二摻雜區各 二導電型。'，第一推雜區與第二推雜區均具有第 第-發明另—實施例’―種雙載子電晶體包含井、 五細π品、第二推雜區、第三推雜區、第四摻雜區、第 極，=、第一介電層、第二介電層、第一閉極、第二閘 、播塞、第-間隔物、第二間隔物與電容介電質層。 位於ΐ結才it’該些推雜區皆位於井中，其中第二摻雜區 一於：-：雜區與第五摻雜區之間。第三摻雜區位在第 雜區區之間，與第一、第二換雜區相連。第四換 „第三摻雜區上方’而且位於第一、第二摻雜區之 =第=電=於井上方，第-、第二閘極 四摻雜區上，插上方。電容介電質層位於第 插塞貝穿電谷介電質層接觸到第四摻雜區。 201123443 第一間隔物位於第一閘極與第一介電層外圍，使插塞與第 一閘極絕緣；第二間隔物位於第二閘極與第二介電層外 圍，使插塞與第二閘極絕緣。 s 在傳導類型方面，井、第四摻雜區、第五摻雜區均具 有第-導電型；第-摻雜區、第二摻雜區、第三摻雜區;句 具有第二導電型。 -~ ϋ兩m阻性保謾氧化層 (resistive protection oxide )或是金屬矽化物阻隔層 • (self-aligned silicide blocking layer)。 θ 依據本發明又一實施例，一種雙載子電晶體包含井、 第：摻雜區、第二摻雜區、第三摻雜區、第四摻雜區开第 五摻雜區、插塞與電阻性保護氧化層（奶論 ^otection oxide)； , ( ^ s细de blocklng laye〇取代電阻性保護氧化層。gned 在結構上，該歸純冑 位於第-摻雜區與第五摻雜區之間井:^中第二摻雜區 推雜區與第二摻雜區之間， 雜區位於第一 區。第四摻雜區位於第三摻 「摻雜區及第二摻雜 第二摻雜區之間，且連接第二松’並位於第-摻雜區與 性保護氧化層位於第四：丄雜區及第二摻雜區。電阻 二摻雜區各有—部份與電限外’第1雜區與第 氧化層接觸到第四摻雜ί化層相連，插塞貫穿 在傳導類型方面， u :第-導電型，·第1雜區第四摻:區舆第五接雜區均具 具有第二導電型。 第-摻雜區舆第三摻雜區均 201123443 以下將以實施例對上述之說明以及接下來的實施方式 做詳細的描述，並對本揭示内容之技術方案提供更進一步 的解釋。 【實施方式】201123443 6. Description of the Invention: [Technical Field to Which the Invention pertains] </ RTI> and particularly relates to a semiconductor device of a bi-carrier transistor. [Prior Art] In recent years, with the advancement of technology, the semiconductor industry has flourished, and the integrated circuit provided by the phase is often considered as an important consideration for downsizing. As a result, the size of the integrated circuit developed by Chunshen t is shrinking, and its components are also small, which is able to respond to industrial needs. However, the general complementary metal oxide (CM〇s) logic process does not provide a well-characterized dual-carrier transistor due to cost and application considerations. Without changing the process steps and the number of masks, only conventional bipolar transistors can be fabricated, the current gain is quite low, and the size of such bipolar transistors is difficult to progress with the process. Down. It can be seen that the existing dual-carrier transistors obviously still have many inconveniences and defects, and it is urgent to further improve. In order to solve the above problems, the relevant fields have not exhausted their efforts to find a solution, but the methods that have not been applied for a long time have been developed. Therefore, how to provide a bi-carrier transistor compatible with the complementary metal oxide logic process without changing the process steps and without increasing the number of masks is one of the current important research and development topics, and has become a related field. The goal to be improved. SUMMARY OF THE INVENTION 201123443 Cheng = phase, the number of complementary metal oxide masks, can have a size reduction = private steps and does not increase according to the invention - examples, a kind of double carrier transistor package - multi-hybrid a second doped region, a third doped region spacer and a plug. 》Electrical layer gate, inter-region ΐ on the structure of the first ==:: other: - where the second doping spacer is located at the periphery of the interpole and dielectric layer: : 2 = in the well. In addition, the first doped region and the second doped region are each of two conductivity types. ', the first doping region and the second doping region both have the first-inventive-embodiment'-the kind of bi-carrier crystal containing well, the five fine π product, the second doping region, and the third doping region a fourth doped region, a first electrode, a first dielectric layer, a second dielectric layer, a first closed electrode, a second gate, a plug, a spacer, a second spacer, and a capacitor dielectric Floor. The doping regions are located in the well, wherein the second doping region is between: -: the doped region and the fifth doped region. The third doped region is between the first inter-cell regions and is connected to the first and second mismatch regions. The fourth change is "above the third doped region" and is located in the first and second doped regions = the first = second = above the well, the first and the second gate are four doped regions, inserted above. Capacitor dielectric The first layer is located at the periphery of the first gate and the first dielectric layer to insulate the plug from the first gate; The second spacer is located at the periphery of the second gate and the second dielectric layer to insulate the plug from the second gate. s In terms of conduction type, the well, the fourth doped region, and the fifth doped region each have a first- Conductive type; first doped region, second doped region, third doped region; sentence has a second conductivity type. -~ ϋ two m resistive protective oxide layer (resistive protection oxide) or metal telluride barrier According to still another embodiment of the present invention, a bipolar transistor includes a well, a doped region, a second doped region, a third doped region, and a fourth doped region. The fifth region is doped with a doped region, a plug and a resistive protective oxide layer; ( ^ s fine de blocklng laye〇 Resistive protective oxide layer. gned structurally, the pure germanium is located between the first doped region and the fifth doped region: between the second doped region doped region and the second doped region The impurity region is located in the first region. The fourth doped region is located between the third doped region and the second doped second doped region, and is connected to the second loose portion and is located in the first doped region and is protected. The oxide layer is located at the fourth: the doped region and the second doped region. The resistively doped regions each have a portion connected to the fourth doped layer and the first doped region and the first oxide region are in contact with the fourth doped layer. The plug runs through the conduction type, u: the first conductivity type, the first impurity region, the fourth dopant region, and the fifth impurity region of the region have the second conductivity type. The first doping region and the third doping region The above description and the following embodiments will be described in detail by way of examples, and further explanation of the technical solutions of the disclosure will be provided.
為了使本揭示内容之敘述更加詳盡與完備，可參照所 附之圖式及以下所述各種實施例’圖式中相同之號碼代表 相同或相似之元件。另一方面，眾所週知的元件與步驟並 未描述於實施例中，以避免對本發明造成不必要的限制。 第1圖是依照本揭示内容一實施例之一種雙載子電晶 體100的剖面圖。如圖所示’如圖所示，雙載子電晶體1〇〇 是一種閘控雙載子電晶體（gated BJT)。雙載子電晶體1〇0 包含井130、第一摻雜區136、第二摻雜區134、第三摻雜 區132、閘極150、介電層145、間隔物140與插塞160。 在結構上，井130位於深井120上，而深井12〇位於 基板110上；或者，在其他實施例中，井與基板之間可無 須深井’改由井直接形成於基板上。 上述摻雜區136、134、132分別位於井13〇中，其中 第二摻雜區134位在第一、第三摻雜區136、132之間。介 電層145位於井130之上方，閘極15〇位於介電層145之 上方。間隔物14(M立於介電層145與閘極15〇外圍，並 環繞閘極150與介電層145。插塞16〇位於閑極15〇上· 直接與閘極15G接觸。第三摻雜區132位於井13〇中。」 =2雜區136與第二摻雜區134…部份與間; 物140相連。 201123443 在傳導類型方面，并 一導電型、然第三摻雜區132所摻雜:離區曲132均具有第 且右當第—掺雜區136與第二摻雜E 具有第一導電型。實 修雜£134均 導電型為p型右第-導電型為N型，則第二 型為Nf 反之’右第-導電型為P型，則第二導電 應用上’第-摻雜區136可作為射 區134可作盔隹拉r η "-七’弟一摻雜 而井第三捧雜區132可作為基極區B， 邱八第—摻雜區132電性相連亦形成基極區B-^刀。在實際實作上面’應用在先進半導體製程如45太 米_技術中，閘極15〇之長度(Length)可為45奈米而 介電層145厚度為12埃(入），在此介電層厚度下，施加相 當電壓於閘極15G上，閘極電流(Gate c_nt)會以直接穿 隨(TunnelingCurrent)過介電層145進入基極區b内；如此 來透過額外的電流注入基極區内，進而誘發更高的集 極區電流，而使雙載子電晶體之特性更佳化。更甚者，由 於射極區E與集極區c夾集所形成之基極區B寬度可達45 奈米，就雙載子電晶體來講，基極區B寬度愈窄，電性特 性愈佳。 除此之外，由於本實施例使用插塞160直接接觸在介 電層145上之閘極150，在進行插塞160相關製程中會更 加劣化介電層145之品質，導致除直接穿隧電流(Direct Tunneling)外，會外加另一個阱輔助穿隧電流 (Trap-assisted Tunneling Current)，更高的額外電流注入基 極區，而使得雙載子電晶體之可驅動電流更為增加，電性 201123443 特性愈佳。 第2圖是依照本揭示内容另—竇 晶體2〇〇的剖面圖。如圖所示，雙-種雙载子電 垂直式雙載子電曰p 3子電晶體200是一種 一摻雜區231、第-咕川0包含井23〇、第 雜區283 '第五摻雜區’23°° 二摻雜區270、第四摻 2〇2當 區、第六摻雜區281、第七摻 282、第-介電層24() 禾^雜£ 第一閙極“ 矛"电盾242、第一閘極250、 弟一閘極252、插塞26〇、第一間 與電容介電質層262。 m第-間㈣292 位於中’井⑽位於深井22。上，而深井22。 可，或者’在其他實施财，井與基板之間 …、須冰井，改由井直接形成於基板上。 上述之摻雜區 231、232、27〇、281、282、283、234 ::於2 230中’其中第二掺雜區232位於第-摻雜區231 ”第五摻雜11 234之間。第三摻雜區27〇位在第-、第二 =雜區231、232之間，與第一、第二摻雜區231、232相 =第四摻雜區283位於第三摻雜區謂上方，而且位於 、第一摻雜區231、232之間。第一、第二介電層24〇、 242=別位於井23〇上方，第一、第二閘極25〇、252分別 位於第、第二介電層240、242的上方。電容介電質層 262位於第四摻雜區283上，插塞260貫穿電容介電質層 262接觸到第四摻雜區283。第一間隔物290位於第一閘極 25〇與第一介電層240外圍，使插塞26〇與第—閘極250 絕緣，第二間隔物292位於第二閘極252與第二介電層242 外圍，使插塞260與第二閘極252絕緣。。 201123443 中，可無須第六摻雜區281與第七摻雜^ 282 /、他實施例 製程上’上述電容介電質層地可 — 層（resistive protecti〇n 〇xide)或全屬 物 5 乳化 (se—gned silicide bl〇eking 。金屬石夕化物阻隔層 在傳導類型方面，井230、第四摻 區234、第六摻雜區卻與第七摻雜區如均且^摻^ 電型，然第五摻雜區234所摻雜之離子濃产大^ 導 摻雜之離子濃度。第-摻雜區231 ^於井230所 摻雜區27。均具有第二導電型，然第第一::=、第三 扣所摻雜之離子濃度大於第三摻摻雜區加、 =::第一第二摻雜區231 = 第七、第四摻雜區281、一 = ，用上’第一、第二換雜區231、2 其中第-摻雜區231與第二摻雜區 乍為f極區B， 性連接，第五穆雜區234可作為隼 、;由外部線路電 在製程上，可於第一、第二 230中袋植入（pocket implant)以Ζ第24三0换242下方之井 以輕微摻雜沒極（LDD)作為第力、第 夕雜區270 ’並 、 擦雜區231、232。然後 282、加。接著，形成第、第七、第四摻雜區28卜 201123443 形成插塞260接觸至第六摻雜區283。 在半導體製程中，比如形成第一導電型電晶體中使用 第二導電型雜質袋植入’加以第一導電型雜質為輕微換雜 沒極（LDD)植入；以此類推形成第二導電型電晶體中使 用第-導電型雜質袋植入，加以第二導電型雜質為輕㈣ 雜沒極（LDD)植入；在本實施例中，若要利用光罩資料 上-些邏輯運算處理，遮蔽原本該植入之袋植入…伽 implant)’改以另外一種導電型之袋植入，同樣作法也可應 用到輕微摻雜沒極（LDD)製程，可不用多增加光罩及製 程步驟。 第3圖是依照本揭示内容又一實施例的一種雙載子電 晶體的剖面圖。如圖所示，雙載子電晶體300是一種垂直 式雙載子電晶體。雙載子電晶體扇包含井33() 3雜80區：^^雜區332、第三摻雜區37G、第四摻雜區 380、第五摻雜區334、插塞36〇與電阻性保護氧化層綱 跳加酬⑽⑽⑹心或者^金屬魏物阻隔層 層(s^^gned SlIlcide blGeking layer )取代電阻性保護氧化 位於ΐϋΓΓ，井330位於深井32G±，而深井別 、广板 上，或者，在其他實施例中，井與基板之 可無須深井，改由井直接形成於基板上。 曰 上述之摻雜區33卜332、37〇、38〇、334 中，其中第二摻雜區332位於第一換雜區 、^ =4之間。第三換雜區37。位於第一捧雜區：:雜 t雜區说之間，且連接第一摻雜區331及第二穆雜^ 201123443 =第:捧雜區380位於第三摻雜區370上，並位Μ 與第二摻雜區332之間，且連接第-摻= 及第一摻雜區332。電阻 雅£ 331 區380上。另外 ^氧化層390位於第四摻雜 一邻第摻雜區331與第二摻雜區332 it 縣與電阻性保護氧化層39G =各有 性保護氣化爲竭·插塞360貝穿電阻 旻乳化層390接觸到第四摻雜區38〇。 幻且 在傳導類型方面，井330、笛,Α 雜區334均具有第—1 、★四摻雜區38G與第五摻 離子濃度可大於井 ㈣然第五摻雜區334所摻雜之 ;井3 3 0所推雜之離+、，豊♦ 331、第二摻雜區332與第三摻雜辰度帛—摻雜區 型，鈇第 墙.、 區370均具有第二導電 …、第一、第二摻雜區331 等电 第三摻雜區37〇 <離子濃度。另外’ f參雜之離子濃度大於 332所摻雜之齙 又 卜苐一、第二摻雜區33卜 子濃度 子浪度可大於第四摻雜區通所摻雜之離 應用上，第一、第二摻雜區331 其中第-摻雜區331與第二摻雜 ° 土極區B ’ 性連接，第五摻雜區334可作為隼極由外部線路電 可作為鼾；Γ：, 马集極區C，第四摻雜區38〇 為射極£E，插塞360可作為射極電極。 形成於井330中袋植入（P〇cketi_nt)以 :摻雜區。接著，形丄麟:二=\第 德，耶山而„ , 释雜區331、332。然 穿過電==護氧化層39。。另外，亦可形成插請 性保濩氧化層390接觸至第四摻雜區,。 37〇 植入（P〇Cket —a1")所製造出來的基極區 寬度識）可以製造出比_般靠擴散方式In order to make the description of the present disclosure more complete and complete, the same reference numerals are used to refer to the same or similar elements in the drawings. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention. 1 is a cross-sectional view of a bipolar transistor 100 in accordance with an embodiment of the present disclosure. As shown in the figure, as shown, the bipolar transistor 1〇〇 is a gated bicarrier transistor (gated BJT). The bipolar transistor 1 〇 0 includes a well 130, a first doped region 136, a second doped region 134, a third doped region 132, a gate 150, a dielectric layer 145, a spacer 140, and a plug 160. Structurally, the well 130 is located on the deep well 120 and the deep well 12 is located on the substrate 110; or, in other embodiments, the well and the substrate may be formed directly on the substrate without the need for a deep well. The doped regions 136, 134, 132 are respectively located in the well 13〇, wherein the second doped region 134 is located between the first and third doped regions 136, 132. Dielectric layer 145 is above well 130 and gate 15 is above dielectric layer 145. The spacer 14 (M stands on the periphery of the dielectric layer 145 and the gate 15?) and surrounds the gate 150 and the dielectric layer 145. The plug 16 is located on the idler 15 and is in direct contact with the gate 15G. The impurity region 132 is located in the well 13". The =2 hetero region 136 and the second doped region 134 are partially connected to each other. The object 140 is connected. 201123443 In terms of conductivity type, the first conductivity type, the third doping region 132 The doping: the leaving regions 132 each have a first and right when the first doping region 136 and the second doping E have a first conductivity type. The practice is 134, the conductivity type is p-type right first conductivity type N Type, the second type is Nf, and the 'right first-conductivity type is P type, then the second conductive application 'the first doped region 136 can be used as the shot 134 can be used as a helmet r r η "-七' brother A doped well third holding region 132 can be used as the base region B, and the Qiu Ba first-doped region 132 is electrically connected to form a base region B-^ knife. In actual practice, the application is applied to an advanced semiconductor process. For example, in the 45-meter-meter, the length of the gate 15〇 can be 45 nm and the thickness of the dielectric layer 145 is 12 angstroms (in). Under the thickness of the dielectric layer, a considerable voltage is applied to the gate 15G. Upper gate The current (Gate c_nt) enters the base region b through the dielectric layer 145; thus, the extra current is injected into the base region, thereby inducing a higher collector current, and The characteristics of the carrier transistor are better. Moreover, since the width of the base region B formed by the emitter region E and the collector region c is up to 45 nm, in the case of a bipolar transistor, the base The narrower the width of the polar region B, the better the electrical characteristics. In addition, since the plug 160 directly contacts the gate 150 on the dielectric layer 145, the plug 160 is more deteriorated in the process of performing the plug 160. The quality of the dielectric layer 145 causes a Trap-assisted Tunneling Current to be added in addition to the direct tunneling current, and a higher extra current is injected into the base region, thereby making the dual load The driveable current of the sub-transistor is further increased, and the electrical property 201123443 is better. Fig. 2 is a cross-sectional view of the sinus crystal 2〇〇 according to the disclosure. As shown, the double-type double carrier is electrically vertical. The bi-carrier 曰p 3 sub-crystal 200 is a doped region 231 The first-咕川0 includes well 23〇, the first impurity region 283 'the fifth doped region'23°° the second doped region 270, the fourth doped 2〇2 region, the sixth doped region 281, and the seventh doped 282 , the first dielectric layer 24 (), the first bungee "spear" "electric shield 242, the first gate 250, the brother a gate 252, the plug 26 〇, the first and the capacitor dielectric Layer 262. m-di (four) 292 is located in the middle 'well (10) located in the deep well 22. On, while deep well 22. Yes, or 'in other implementations, between the well and the substrate..., the ice well must be formed directly on the substrate by the well. The above doped regions 231, 232, 27A, 281, 282, 283, 234 :: in 2 230 'where the second doped region 232 is located between the first doped region 231 ” fifth doping 11 234. The third doped region 27 is clamped between the first and second = doped regions 231, 232, and the first and second doped regions 231, 232 = the fourth doped region 283 is located in the third doped region. Above, and located between the first doped regions 231, 232. The first and second dielectric layers 24, 242 = are located above the well 23, and the first and second gates 25, 252 are respectively located Above the second dielectric layer 240, 242. The capacitor dielectric layer 262 is located on the fourth doping region 283, and the plug 260 contacts the fourth doping region 283 through the capacitor dielectric layer 262. The first spacer 290 is located at the periphery of the first gate 25 〇 and the first dielectric layer 240 to insulate the plug 26 〇 from the first gate 250 , and the second spacer 292 is located outside the second gate 252 and the second dielectric layer 242 . The plug 260 is insulated from the second gate 252. In 201123443, the sixth doping region 281 and the seventh doping 282 are not required, and the above-mentioned capacitor dielectric layer can be layered ( Resistive Protecti〇n 〇xide) or all-genus 5 emulsification (se-gned silicide bl〇eking. Metallic lithology barrier layer in terms of conductivity type, well 230, fourth doping zone 234, sixth doping zone and seventh The doped regions are both doped and doped, and the ions doped by the fifth doped region 234 are concentrated to produce a large doping ion concentration. The doped region 231 is doped in the well 230. Each has a second conductivity type, but the first::=, the third buckle is doped with an ion concentration greater than the third doped region plus, =:: the first second doped region 231 = seventh, Four doped regions 281, a =, using 'first and second impurity-doping regions 231, 2, wherein the first doped region 231 and the second doped region 乍 are f-polar regions B, sexually connected, fifth The region 234 can be used as a crucible; the external line can be electrically processed on the process, and the well can be implanted in the first and second 230 pockets to replace the well below the 242th 242 with a slightly doped immersion (LDD). As the first force, the first eclipse region 270 'and the rubbing regions 231, 232. Then 282, add. Then, the formation of the seventh, fourth, fourth doping region 28 201123443 form the plug 260 contact to the sixth doping Miscellaneous area 283. In a semiconductor process, for example, forming a first conductivity type transistor using a second conductivity type impurity bag implant 'to the first conductivity type impurity is a lightly mixed impurity (LDD) implant; and so on to form a second The conductive type transistor is implanted using a first-conductivity type impurity bag, and the second conductivity type impurity is a light (tetra) impurity-doped (LDD) implant; in this embodiment, if a mask is used for some logic operations Processing, masking the original implanted bag implant...Gam implant)' is changed to another conductive type of bag implant, the same method can also be applied to the lightly doped immersion (LDD) process, without adding more masks and Process steps. Figure 3 is a cross-sectional view of a dual carrier transistor in accordance with yet another embodiment of the present disclosure. As shown, the bipolar transistor 300 is a vertical bipolar transistor. The bipolar transistor fan comprises a well 33() 3 impurity 80 region: ^^ impurity region 332, third doped region 37G, fourth doped region 380, fifth doped region 334, plug 36〇 and resistive Protection of the oxide layer (10) (10) (6) heart or ^ metal Wei material barrier layer (s^^gned SlIlcide blGeking layer) instead of resistive protection oxidation located in the ΐϋΓΓ, well 330 located in the deep well 32G ±, deep well, wide plate, or In other embodiments, the well and the substrate may be formed on the substrate without a deep well.曰 In the above doped regions 33 332, 37 〇, 38 〇, 334, wherein the second doping region 332 is located between the first impurity-changing region and ^=4. The third change zone 37. Located between the first doping region:: the hetero-doping region, and connecting the first doping region 331 and the second doping region 201123443 = the first: the doping region 380 is located on the third doping region 370, and is located at Between the second doped region 332 and the first doped region and the first doped region 332. Resistance ya £ 331 on the 380. In addition, the oxide layer 390 is located in the fourth doped adjacent doped region 331 and the second doped region 332 it county and the resistive protective oxide layer 39G = each protective gasification is exhausted and the plug 360 is worn. The emulsion layer 390 contacts the fourth doped region 38A. In terms of conduction type, the well 330, the flute, and the argon region 334 each have a first -1, a fourth doped region 38G and a fifth doped ion concentration may be greater than a well (four) and a fifth doped region 334 doped; The wells 3 3 0 are separated from +, 豊 ♦ 331 , the second doped region 332 and the third doped 帛-doped region type, the first wall, the region 370 have a second conductivity... The first and second doping regions 331 are electrically third doped regions 37 〇 < ion concentration. In addition, the concentration of the 'f-doped ion is greater than 332, and the second doped region 33 can be larger than the doping of the fourth doped region. First, a second doping region 331, wherein the first doping region 331 is connected to the second doping region 4A, and the fifth doping region 334 can be used as a drain for the external line to be used as a 鼾; The polar region C, the fourth doped region 38A is an emitter £E, and the plug 360 can serve as an emitter electrode. The bag is implanted in the well 330 (P〇cketi_nt) to: doped regions. Then, the shape of the unicorn: two = \ Dide, Yashan and „, the release zone 331, 332. However, through the electricity == protective oxide layer 39. In addition, can also form a plug-in protective oxide layer 390 contact To the fourth doped region, the 37 〇 implant (P〇Cket — a1") created the base region width) can be made to diffuse than
[SI 201123443 (Diffusion)做製造出來的基極區寬度來的小跟窄，如此一 來’針對雙載子電晶體的一些特性如截止頻率（cut 〇ff frequency)均來的較佳。 實作上，以0.18微米互補金氧半導體邏輯製程來實現 上述各個實施例之雙載子電晶體，其截止頻率可高達 18GHz。在相同製程條件下，習知水平式雙載子電晶體的 截止頻率卻難以超過4GHz。[SI 201123443 (Diffusion) makes the small and narrow width of the base region width, so that some characteristics such as the cut 〇ff frequency are better for the dual-carrier transistor. In practice, the dual carrier transistor of each of the above embodiments is implemented with a 0.18 micron complementary MOS logic process with a cutoff frequency of up to 18 GHz. Under the same process conditions, the cutoff frequency of the conventional horizontal type bipolar transistor is difficult to exceed 4 GHz.
第4圖是第2圖之雙載子電晶體的頻率響應圖，其中 Ft代表截止頻率，90nm代表90奈米半導體製程技術， 〇.18um代表0.18微米半導體製程技術，而sim為利用元 件模擬軟體模擬出來電性特性，mea•代表實際元件製造出 來利用精密儀器量測出來資料；如圖所示，雙載子電晶體 可擴縮性佳（Good Scalability)，即使在不同製程[A]、[C] :，雙載子電晶體都有雜訊低、電流驅動力強、截止頻率 高等特性。 综上所述，本實施方式所提供之技術方案與現有技 相比具有明顯的優點和有益效果。藉由上述技術方案， 達到相當的技術進步性及實用性，並具有産業上的廣泛 用價值’其至少具有下列優點： ’、 體邏二载子電晶體可完全相容於互補金屬氧化物半 a()利用互補金屬氧化物半導體邏輯製程，以簡化 作〜程，並且可擴縮性佳； ㈣2由於採用垂直式架構以及較窄之基極寬度 曰曰體具有低雜訊、高截止頻率等特性； 13 201123443 雙載子電晶體適用度高、電流驅動力強，可廣泛 、用在現有的或開發中的高速雙極互補金氧半導體 (BiCMOS)之應用。 雖然本揭示内容已以實施方式揭露如上，然其並非用 以限定本發明’任何熟習技藝者，在不脫離本揭示内容之 精神和範圍内，當可作各種之更動與潤飾，因本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 ” 【圖式簡單說明】 為讓本揭示内容之上述和其他目的、特徵、優點與實 施例能更明顯易懂，所附圖式之說明如下： 第1圖是依照本揭示内容一實施例之一種雙載子電曰曰 體的剖面圖； 第2圖是依照本揭示内容另一實施例之一種雙戴子電 晶體的剖面圖；以及 第3圖是依照本揭示内容又一實施例之一種雙載子電 晶體的剖面圖；以及 第4圖是第3圖之雙載子電晶體的頻率響應圖。 【主要元件符號說明】 100 雙載子電晶體 110 :基板 120 深井 130 井 132 第三摻雜區 134 第二換雜區 136 第一摻雜區 140 間隔物 14 201123443Figure 4 is a frequency response diagram of the bipolar transistor of Figure 2, where Ft represents the cutoff frequency, 90 nm represents the 90 nm semiconductor process technology, 1818um represents the 0.18 micron semiconductor process technology, and sim uses the component simulation software. Simulated electrical characteristics, mea• represents the actual components manufactured using precision instruments to measure the data; as shown, the dual-carrier transistor is Good Scalability, even in different processes [A], [ C] : The dual-carrier transistor has low noise, strong current driving force and high cut-off frequency. In summary, the technical solutions provided by the present embodiment have obvious advantages and advantageous effects compared with the prior art. With the above technical solutions, considerable technological advancement and practicability are achieved, and it has industrial wide-ranging value, which has at least the following advantages: ', the body-logic two-carrier transistor can be completely compatible with the complementary metal oxide half. a() utilizes a complementary metal oxide semiconductor logic process to simplify the process and has good scalability; (4) 2 due to the vertical architecture and narrow base width, the body has low noise, high cutoff frequency, etc. Features; 13 201123443 The dual-carrier transistor has high applicability and strong current driving capability, and can be widely used in existing or developing high-speed bipolar complementary metal-oxide semiconductor (BiCMOS) applications. Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the invention to those skilled in the art, and various modifications and refinements may be made without departing from the spirit and scope of the disclosure. The scope of protection is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. A cross-sectional view of a dual-carrier electrical body; FIG. 2 is a cross-sectional view of a double-worn transistor in accordance with another embodiment of the present disclosure; and FIG. 3 is a cross-sectional view of another embodiment of the present disclosure. A cross-sectional view of the bipolar transistor; and Fig. 4 is a frequency response diagram of the bipolar transistor of Fig. 3. [Key element symbol description] 100 bipolar transistor 110: substrate 120 deep well 130 well 132 third Doped region 134 second swap region 136 first doped region 140 spacer 14 201123443
145 :介電層 150 :閘極 160 :插塞 200 :雙載子電晶體 210 :基板 220 :深井 230 :井 231 :第一摻雜區 232 :第二摻雜區 234 :第七摻雜區 240 :第一介電層 242 :第二介電層 250 :第一閘極 252 :第二閘極 260 :插塞 262 :電容介電質層 270 :第三摻雜區 281 :第四摻雜區 282 :第五摻雜區 283 :第六摻雜區 290 :第一間隔物 292 :第二間隔物 300 :雙載子電晶體 310 :基板 320 :深井 330 :井 331 :第一摻雜區 332 :第二摻雜區 334 :第五摻雜區 360 :插塞 370 :第三摻雜區 380 :第四摻雜區 390 :電阻性保護氧化層 B ： 基極區 C : 集極區 E ： 射極區145: dielectric layer 150: gate 160: plug 200: bipolar transistor 210: substrate 220: deep well 230: well 231: first doped region 232: second doped region 234: seventh doped region 240: first dielectric layer 242: second dielectric layer 250: first gate 252: second gate 260: plug 262: capacitor dielectric layer 270: third doping region 281: fourth doping Region 282: fifth doped region 283: sixth doped region 290: first spacer 292: second spacer 300: bipolar transistor 310: substrate 320: deep well 330: well 331: first doped region 332: second doped region 334: fifth doped region 360: plug 370: third doped region 380: fourth doped region 390: resistive protective oxide layer B: base region C: collector region E : Shooting area
L SI 15L SI 15