TW201123386A - Chip module sharing the same PCB - Google Patents
Chip module sharing the same PCB Download PDFInfo
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- TW201123386A TW201123386A TW098143877A TW98143877A TW201123386A TW 201123386 A TW201123386 A TW 201123386A TW 098143877 A TW098143877 A TW 098143877A TW 98143877 A TW98143877 A TW 98143877A TW 201123386 A TW201123386 A TW 201123386A
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- motherboard
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Wire Bonding (AREA)
Abstract
Description
201123386 六、發明說明: 【發明所屬之技術頜域】 本發明係有關於一種晶片模組,尤指一種可共用相同 主機板之晶片模組。 【先前技術】 在現代進步的資訊社會中,由積體電路所構成的 理機系統早已被普遍運用於生活的各個層面。舉凡自動和 制之家電用品、行動通訊設備、個人電腦,無不可見積^ 電路之蹤跡,而積體電路的主體,就是經由習知半導體= 程所生產的晶粒(die)。 又 製造晶粒的過程,是先由生產一晶圓(wafer)開始,在 一片晶圓上區分出多個區域,並在每個區域上,利用半 體製程形成各種電路,最後再對晶圓上的各個區域進行切 割而成各個晶粒。當得到晶粒後,還須經過一定的方式, 將曰曰粒電連至-電路板上’例如—印刷電路板㈣咖 咖油board,PCB),如此—來,日日日粒就可透過該電路板得 ,所需的操作電壓以進行1定運算^舉例來說,該晶粒 係為-編碼電路(encodercircuit),當提供該編碼電路運作所 需的電壓後,該晶粒即可針對該電路板所輸人的資料訊號 進仃編碼運算,織再輸出編碼訊號至該電路板。 :般而言’晶片電性連接至電路板的方式可以為將晶 直接電連至電路板之裸晶(barechip)配置法,或是透過一 ii2aekage)先將晶片進行封裝後,再經由縣體内的 電性^而電性連接至電路板,以接收電源與傳輸訊號。 的替樣體的主要功能在於提供晶片與電路板之間 如虎傳輸;丨©以及倾^的目的,此外由於目前電子 201123386 產品逐漸朝輕薄短小與高運算速度的趨勢發展,因此造成 封裝體所要求的輸入/輸出接腳數(package pinc〇u叫也隨之 增加,同時厚度必須越來越薄,且面積亦必須越來越小, 過去採用引腳插入(pin through hole,ΡΤΉ)的封裝技術由於 受到電路板上相對應插入孔的大小限制,因此封裝體的尺 寸無法進一步地縮小,且輸入/輸出接腳數也同時受a到限 制,因此表面黏著(surface mount techn〇I〇gy,SM 丁)的封^201123386 VI. Description of the Invention: [Technical Jaw Domain of the Invention] The present invention relates to a wafer module, and more particularly to a wafer module that can share the same motherboard. [Prior Art] In the modern and progressive information society, the computer system composed of integrated circuits has been widely used in all aspects of life. For household appliances, mobile communication devices, and personal computers, there is no trace of the circuit, and the main body of the integrated circuit is the die produced by the conventional semiconductor. The process of fabricating a die begins with the production of a wafer, which distinguishes multiple regions on a wafer, and in each region, uses a semi-system process to form various circuits, and finally wafers. Each of the upper regions is cut into individual crystal grains. After obtaining the crystal grains, the granules must be electrically connected to the circuit board, for example, a printed circuit board (4) café board (PCB), so that the daily granules can pass through. The circuit board obtains the required operating voltage for performing a predetermined operation. For example, the die is an encoder circuit. When the voltage required for the operation of the encoding circuit is provided, the die can be targeted. The data signal input by the circuit board is input and encoded, and the encoded signal is outputted to the circuit board. Generally speaking, the method of electrically connecting the chip to the circuit board can be a bare chip configuration method of directly connecting the crystal to the circuit board, or encapsulating the wafer through a ii2aekage, and then passing through the county body. The internal electrical and electrical connection to the circuit board to receive power and transmission signals. The main function of the substitute body is to provide the purpose of transferring between the chip and the circuit board, such as tiger transmission; 丨© and 倾 ^, and because the current electronic 201123386 product is gradually moving toward the trend of light, thin, short and high computing speed, it is required by the package. The number of input/output pins (package pinc〇u is also increased, and the thickness must be thinner and thinner, and the area must be smaller and smaller. In the past, pin-on-pin (ΡΤΉ) packaging technology was used. Due to the size limitation of the corresponding insertion holes on the board, the size of the package cannot be further reduced, and the number of input/output pins is also limited by a, so the surface is attached (surface mount techn〇I〇gy, SM Ding)'s seal ^
技術便逐漸取代該⑽插人的封裝技術,以降低封裝體^ 尺寸° w㈣腳插入與表面黏著的封裝技術均屬於 I /HenPhei>al)的封裝方式,目此在封裝體體積的縮減與輪 輸出接腳數的增加上仍有其先天上的限制。舉例來說, =面黏著的封裝技術,當週邊排列的接腳數增加時, 板日卞,會因為相鄰接腳之間的距離過短而 的情況,面矩陣一胸: 入格/列⑽丨咖咖y'贿)封裝體,其由於輪 相鄰崎排列方式,不但 時的組u率,同祕叫升縣體絲於電路板 晶片的電性連接;η雨出接腳數也可大幅增加。依據 接合㈣一 •格;分 格陣列封裝體。 j可裝肢與覆晶(flip chip)接合球 作晶將她其晶片尺寸製The technology gradually replaces the (10) plug-in packaging technology to reduce the package size. w (four) pin insertion and surface adhesion packaging technology are all I / HenPhei > a) package, the purpose of the package volume reduction and wheel There is still an innate limit on the increase in the number of output pins. For example, if the number of pins arranged in the periphery increases, the number of pins in the periphery increases, because the distance between adjacent pins is too short, the matrix is one chest: the grid/column (10) 丨 咖 咖 y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Can be greatly increased. According to the joint (four) one grid; the grid array package. j can be loaded with limbs and flip chip bonding balls to make her wafer size
Level Chip Scale Package, 5 201123386 製程’因此造成成品尺寸的纽,在相同功能之 曰曰片上,不利後端模組廠之交互運用,因而造成主機板 (mother board)之庫存量增加’並且也增加因應不同尺 片所開發之新主機板的成本。 3曰 /緣是’本發明人減上述缺失之可改善,且依據多年 來從事此方面之侧經驗,悉錢察且研究之,並配合學 理之運用,而提出-種設計合理且有效改善上述缺失= 發明。 【發明内容】 本發明所要解決的技術問題,在於提供—種晶片模 組’其.可共用相同主機板之晶片模組。 為了解決上述技術問題,根據本發明之其中一種方 案,提供-種可共用相同主機板之晶片模組,其包括:一 晶片單元及-導電單元。其中,該晶片單元係具有至少一 晶片本體及魏個電性設置於±述至少U本體的底部 且排列成矩陣(matrix)形狀之導電焊塾。該導電單元係且 有複數個選雜地電性設置於該晶片單元之料導電焊塾 上之導電體’每-個導電體係具有—幾何中心及一半徑, 並且每兩個導電體之兩鑛何巾^的間距料於該導電體 的半徑加上G.15毫米至G.25毫米’其巾該晶片本體係透過 該等導電體而電性設置於該主機板的上方。 為了解決上述技術問題,根據本發明之其中一種方 案,提供一種可共用相同主機板之晶片模組,其包括:一 晶片單元、一第一導電單元、一轉接基板單元及一第二導 電單元ms片單元係具有至少_晶片本體及複數 個電性設置於上述至少-晶片本體的底部且排列成矩陣 201123386 (matrix)形狀之導電焊墊。該第一導電單元係具有複數個 選擇性地電性設置於該晶片單元之該等導電焊墊上之第一 導電體,每一個第一導電體係具有一幾何中心及一半徑,Level Chip Scale Package, 5 201123386 Process 'Therefore, the size of the finished product is on the same function, which is unfavorable for the interaction of the back-end module factory, thus increasing the inventory of the motherboard (also increasing the inventory). The cost of new motherboards developed for different sizes. 3曰/缘是' The inventor can improve the above-mentioned defects, and based on years of experience in this aspect, learn and research, and with the use of academics, propose a reasonable design and effectively improve the above Missing = invention. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a wafer module that can share a wafer module of the same motherboard. In order to solve the above technical problems, according to one of the embodiments of the present invention, there is provided a wafer module which can share the same motherboard, comprising: a wafer unit and a conductive unit. The wafer unit has at least one wafer body and a conductive pad disposed on the bottom of the U body and arranged in a matrix shape. The conductive unit is composed of a plurality of conductors electrically connected to the conductive pads of the wafer unit. Each of the conductive systems has a geometric center and a radius, and two of each of the two conductors The spacing of the film is based on the radius of the conductor plus G.15 mm to G.25 mm. The wafer system is electrically disposed above the motherboard through the conductors. In order to solve the above technical problem, according to one aspect of the present invention, a wafer module that can share the same motherboard includes: a wafer unit, a first conductive unit, a transfer substrate unit, and a second conductive unit. The ms chip unit has at least a wafer body and a plurality of conductive pads electrically disposed at the bottom of the at least the wafer body and arranged in a matrix 201123386 (matrix) shape. The first conductive unit has a plurality of first conductive bodies selectively electrically disposed on the conductive pads of the wafer unit, each of the first conductive systems having a geometric center and a radius.
並且母兩個第一導電體之兩個幾何中心的間距係等於該第 一導電體的半徑加上0.15毫米至〇.25毫米。該轉接基板單 元係具有一轉接電路板、複數個設置於該轉接電路板的上 表面之上層焊墊、及複數個設置於該轉接電路板的下表面 且分別電性連接於該等上層焊墊之下層焊墊。該第二導電 單元係具有複數個選擇性地電性設置於該轉接基板單元之 下層焊塾上之第二導電體’其中該轉接電路板係透過該等 第二導電體而電性設置於該主機板的上方。 因此,本發明的有益效果在於:本發明將現有尺寸相 近之晶片以目定之接腳制方式設置,明加相同^晶 生’並且亦可降低因不同晶片而產生之主機二 .備料庫存及新主機板的開發成本。 為了月b更進一步暸解本發明為達成預定目的所採取之 技^手段及功效,請參_下㈣本發明之詳細說明盘 附圖’相彳§本發明之目的、特徵與特點 Θ二 入且具體之瞭解,然㈣_式僅提供參考與 非用來對本發明加以限制者。 /、 用並 【實施方式】 請參閱第一A圖至第一B圖所示 係提供一種可共用相同主機板之晶片 片單元1及一導電單元2。 ’本發明第一實施例 模組,其包括And the distance between the two geometric centers of the two first conductors is equal to the radius of the first conductor plus 0.15 mm to 〇.25 mm. The interposer substrate unit has a transit circuit board, a plurality of layer pads disposed on the upper surface of the interposer circuit board, and a plurality of lower surfaces disposed on the interposer circuit board and electrically connected to the interposer substrate Wait for the underlying pads to be soldered. The second conductive unit has a plurality of second electrical conductors selectively electrically disposed on the underlying solder pads of the interposer substrate unit. The transit circuit board is electrically disposed through the second electrical conductors. Above the motherboard. Therefore, the present invention has the beneficial effects that the present invention sets the existing wafers of similar size in a targeted pin-up manner, and adds the same crystals and can also reduce the host generated by different wafers. The development cost of the motherboard. For a more detailed understanding of the techniques and functions of the present invention for achieving the intended purpose, please refer to the following: (4) The detailed description of the present invention is in accordance with the purpose, features and features of the present invention. It is specifically understood that the (4) _ formula is only for reference and not to limit the invention. [Embodiment] Please refer to FIGS. 1A to 1B to provide a wafer unit 1 and a conductive unit 2 which can share the same motherboard. a first embodiment of the present invention, comprising:
由上述圖中可知 該 體10及複數個電性設置於上述至少 曰日片單元1係具有至少 晶 片本· 一晶片本 1 0的底 201123386 部且排列成矩陣(matrix)形狀之導電焊墊丄丄。其中,上 述至少-晶片本體10係可為一半導體晶片,其係由〜曰曰 圓經過加工後所形成,並且此半導體晶片具有一預定的資 訊處理功能。 再者,該導電單元2係具有複數個選擇性地電性設置 於該晶片單元i之該等導電烊M i上之導電體2 〇,每 一,導電體2◦係具有—幾何中心2◦〇及-半徑r,並 且母兩個導電體2 Q之兩個幾何$心2 q q的間距^係等 於該導電體2 Q的半徑加上G.15毫米至〇·25毫米,其中 依據不同的設計需求,每一個導電體2 〇係可為一錫球 (solder ball)或一金球(g〇id bump)。 ^此外,該晶片本體1〇係透過該等導電體2 0而電性 設置=該錢板4的上方。以本發明第—實施例所舉的例 子而s,該主機板4的上表面係具有複數個主機板焊墊 0 ’並且該等導電體2 0係選擇性地電性連接於該主 4之該等主機板焊墊4〇。 請參閱第二圖所示,本發明第二實施例係提供一種可 共用相同主機板之晶片模組,其包括:一晶片單元1、一 第一導電車元2a、一轉接基板單元3及一第二導 2b。 平兀 由上述圖中可知,該晶片單元1係具有至少一晶片本 體1 0及複數個電性設置於上述至少一晶片本體i 〇的底 部且排列成矩陣(matrix)形狀之導電焊墊丄丄。其中,上 述至少一晶片本體1〇係可為一半導體晶片,其係由一晶 圓經過加工後所形成,並且此半導體晶片具有一預定的= 訊處理功能。 貝 201123386 再者,該第一導電單元2 a係具有複數個選擇性地電 性設置於該晶片單元1之該等導電焊丄上之第一導電 體20a,每一個第一導電體2〇a係具有一幾何中心2 00及一半徑r,並且每兩個第一導電體2〇3之兩個幾 何中心2 Q 0關距d係等於該第-導電體2 Q a的半徑 r加上0.15毫米至0.25毫米。其中依據不同的設計需求, 每一個第一導電體及每一個第二導電體皆為錫球(s〇丨 ball)或金球(g〇id bump)。It can be seen from the above figure that the body 10 and a plurality of conductive pads are electrically disposed on the at least one chip unit 1 having at least the bottom portion 201123386 of the wafer book and a wafer book 10 and arranged in a matrix shape. Hey. Wherein, at least the wafer body 10 can be a semiconductor wafer which is formed by processing a 曰曰 circle, and the semiconductor wafer has a predetermined information processing function. Furthermore, the conductive unit 2 has a plurality of electrical conductors 2 选择性 selectively electrically disposed on the conductive 烊 M i of the wafer unit i, and each of the electrical conductors 2 has a geometric center 2 ◦ 〇 and - radius r, and the two geometries of the two conductors 2 Q of the parent $Qq qq are equal to the radius of the conductor 2 Q plus G.15 mm to 〇·25 mm, depending on the Design requirements, each conductor 2 can be a solder ball or a gold ball (g〇id bump). Further, the wafer body 1 is electrically connected to the upper side of the money board 4 through the conductors 20. In the example of the first embodiment of the present invention, the upper surface of the motherboard 4 has a plurality of motherboard pads 0' and the conductors 20 are selectively electrically connected to the main 4 These motherboard solder pads are 4 turns. Referring to the second embodiment, a second embodiment of the present invention provides a chip module that can share the same motherboard, and includes: a wafer unit 1, a first conductive vehicle element 2a, a switching substrate unit 3, and A second guide 2b. As can be seen from the above figures, the wafer unit 1 has at least one wafer body 10 and a plurality of conductive pads arranged electrically in the bottom of the at least one wafer body i 且 and arranged in a matrix shape. . The at least one wafer body 1 can be a semiconductor wafer which is formed by processing a wafer, and the semiconductor wafer has a predetermined processing function. Further, the first conductive unit 2a has a plurality of first conductive bodies 20a selectively electrically disposed on the conductive pads of the wafer unit 1, each of the first conductive bodies 2a The system has a geometric center 200 and a radius r, and the two geometric centers 2 Q 0 of each two first conductors 2〇3 are equal to the radius r of the first conductor 2 Q a plus 0.15 From millimeters to 0.25 mm. According to different design requirements, each of the first electrical conductors and each of the second electrical conductors are s〇丨 balls or g bumpid bumps.
此外,泫轉接基板單元3係具有一轉接電路板3〇、 複數個設置於該轉接電路板3 0的上表面之上層焊墊3 1、複數個設置於該轉接電路板3 0的下表面且分別電性 連接於該等上層焊墊3 1之下層焊墊3 2、及複數條電性 連接於該等上層焊墊3 1及該等下層焊墊3 2之間之導電 線路3 3,其中該等上層焊墊3 ]_及該等下層焊墊3 2係 彼此錯位,亦即每一個上層焊墊3 i與每一個下層焊墊雖 然相對應,但並非位於同一垂直線上。 另外 琢弟一等電皁b係具有複數個選擇性地 性設置於該轉接基板單元3之下層焊墊3 2上之第-導。 體2 0 b,其中該轉接電路板3 〇係透過該等第邮 2 0 b而電性設置於該主機板4的上方。以本發明第二= 施例所舉關子而言,該域板4係具錢數個主= 墊4 0 ’並且該等第二導電體2 Q b係選擇地電性連 該等主機板焊墊40。 ? 要於 綜上所述 乃胂兄,尺寸相近之晶片以固 腳排列方式設置,以增加相同功能晶片之通用性, <接 可降低因不同晶#而產生之主機板的備料庫存及新主g 201123386 的開發成本。 惟,本發明之所有範圍應以下述之 準’凡合於本發明申料職圍之精神=專利$1«圍為 施例,皆應包含於本發明之料巾,任何熟=似變化之實 在本發明之領域内,可輕易思及之變化或。該項技藝者 以下本案之專利範圍。 夕皆可涵蓋在 【圖式簡單說明】 第一 A圖係為本發明可共用相同主機板之晶片 實施例之側視示意圖圖; 莫叙的苐〜 第一B圖係為本發明可共用相同主機板之晶片镇会 實施例之晶片單元的底視示意圖圖;以及、、''且的苐〜 第二圖係為本發明可共用相同主機板之晶月模叙+ 施例之側視示意圖圖。 、第〜實 晶片本體 1 〇 導電焊墊 1 1 導電體 2 〇 幾何中心 2 〇 0 半徑 Γ 間距 d 第一導電體 2 0 a 第二導電體 2〇b 轉接電路板 3〇 上層焊墊 3 1 下層谭塾 3 2 導電線路 【主要元件符號說明】 晶片單元 1 導電單元 2 第一導電單元 2a 第二導電單元 2b 轉接基板單元 3 201123386 主機板 4 主機板焊墊In addition, the 泫-transfer substrate unit 3 has a transit circuit board 3 〇, a plurality of layer pads 3 1 disposed on the upper surface of the arranging circuit board 30 , and a plurality of the layout pads 3 1 . The lower surface is electrically connected to the lower pad 3 2 of the upper pad 3 1 , and the plurality of conductive lines electrically connected between the upper pad 3 1 and the lower pad 3 2 3 3, wherein the upper pads 3 _ and the lower pads 3 2 are offset from each other, that is, each of the upper pads 3 i corresponds to each of the lower pads, but not on the same vertical line. In addition, the first-class electric soap b has a plurality of first guides selectively disposed on the underlying pads 3 2 of the interposer substrate unit 3. The body 2 0 b, wherein the transit circuit board 3 is electrically disposed above the motherboard 4 through the first mail 202. In the second embodiment of the present invention, the domain board 4 has a plurality of main = pads 40' and the second conductors 2 Qb are selectively electrically connected to the motherboards. Pad 40. ? In summary, the similarly-sized wafers are arranged in a fixed-foot arrangement to increase the versatility of the same functional chip, and the stock and the new master of the motherboard produced by the different crystals can be reduced. g Development cost of 201123386. However, all the scope of the present invention should be based on the following spirits: the spirit of the application of the invention = patent $1«, which should be included in the towel of the present invention, and any cooked change Variations or modifications can be easily considered in the field of the invention. The artist's patent scope in the following case. The first A is a schematic side view of an embodiment of a wafer in which the same motherboard can be shared by the present invention; the first B diagram is the same as the invention A schematic bottom view of a wafer unit of a wafer slab embodiment of the motherboard; and, '' 苐 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 侧 侧 侧 + 侧 + + Figure. , the first real chip body 1 〇 conductive pad 1 1 conductor 2 〇 geometric center 2 〇 0 radius Γ spacing d first conductor 2 0 a second conductor 2 〇 b transit circuit board 3 〇 upper pad 3 1 Lower layer Tan 3 2 conductive line [Main component symbol description] Wafer unit 1 Conductive unit 2 First conductive unit 2a Second conductive unit 2b Transfer substrate unit 3 201123386 Motherboard 4 Motherboard pad
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TW098143877A TW201123386A (en) | 2009-12-21 | 2009-12-21 | Chip module sharing the same PCB |
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