TW201123322A - Sealing package method for stacked semiconductor package using solder ball aligning - Google Patents

Sealing package method for stacked semiconductor package using solder ball aligning Download PDF

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Publication number
TW201123322A
TW201123322A TW098143548A TW98143548A TW201123322A TW 201123322 A TW201123322 A TW 201123322A TW 098143548 A TW098143548 A TW 098143548A TW 98143548 A TW98143548 A TW 98143548A TW 201123322 A TW201123322 A TW 201123322A
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Taiwan
Prior art keywords
solder ball
solder
package
solder balls
layer
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TW098143548A
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Chinese (zh)
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TWI395278B (en
Inventor
Wei-Hua Lu
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Univ Nat Pingtung Sci & Tech
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Priority to TW98143548A priority Critical patent/TWI395278B/en
Publication of TW201123322A publication Critical patent/TW201123322A/en
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Publication of TWI395278B publication Critical patent/TWI395278B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Sealing package method for stacked semiconductor package using solder ball aligning comprises the steps of providing a first package carrier having a first surface, a plurality of first solder balls, a plurality of second solder balls and a passivation layer, wherein a height of each second solder ball is higher than a height of each first solder ball. Each second solder ball has an embedded part and an exposed part, wherein the first surface, each first solder ball and each embedded part of each second solder ball are covered by the passivation layer. Removing parts of the passivation layer to expose each first solder ball by using each exposed part of each second solder ball aligning. Forming an annular metal circuit onto the passivation layer and each exposed part of each second solder ball is connected to the annular metal circuit. Forming a solder layer onto the annular metal circuit and each first solder ball. Providing a second package carrier having a second surface, a plurality of contacts and a metal layer corresponding to the annular metal circuit. Electrically connecting the contacts and the metal layer of the second package carrier to the solder layer and each second solder ball of the first package carrier.

Description

201123322 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關於一種堆疊式半導體封裝件，特別係 有關於一種堆疊式半導體封裝件之錫球對位氣密封裝方 法。 【先前技術】 [0002] 習知二封裝載體間在進行堆疊接合前，其中一封裝 載體通常必須先進行微影蝕刻製程以移除保護層而顯露 埋入該封裝載體内之錫球/導接墊，之後，再將另一封裝 載體之導接部與該裝載體之錫球/導接墊電性連接而達成 上下電性導通，然而，該封裝載體在進行微影蝕刻製程 時，因其封裝載體表面皆受到保護層覆蓋，故無任何標 記可供製程對位之用，導致製程中常無法準確顯露該封 裝載體内主動/被動元件之錫球/導接墊位置，進而影響 另一封裝載體堆疊於該封裝載體時，另一封裝載體之導 接部與該封裝載體内之錫球/導接墊電性連接製程之進行 〇 【發明内容】 [0003] 本發明之主要目的係在於提供一種堆疊式半導體封 裝件之錫球對位氣密封裝方法，其包含下列步驟：提供 一第一封裝載體，該第一封裝載體係具有一第一表面、 複數個形成於該第一表面之第一錫球、複數個形成於該 第一錫球外側之第二錫球及一保護層，各該第二錫球之 高度係高於各該第一錫球之高度，且各該第二錫球係具 有一埋入部及一顯露部，該保護層係覆蓋該第一表面' 098143548 表單編號A0101 第4頁/共18頁 0982074607-0 201123322 各該第一錫球及各該第二錫球之各該埋入部；以各該第 二錫球之各該顯露部進行對位，並移除部份該保護層而 顯露各該第一錫球；形成一環形金屬線路於該保護層上 ，該環形金屬線路係連接各該第二錫球之各該顯露部； 形成一錫層於該環形金屬線路及各該第一錫球上；提供 一第二封裝載體，該第二封裝載體係具有一第二表面、201123322 VI. Description of the Invention: [Technical Field] The present invention relates to a stacked semiconductor package, and more particularly to a solder ball alignment gas sealing method for a stacked semiconductor package. [Prior Art] [0002] Before the package bonding is performed between the two package carriers, one of the package carriers usually has to perform a photolithography process to remove the protective layer to expose the solder balls/conductions embedded in the package carrier. After the pad, the conductive portion of the other package carrier is electrically connected to the solder ball/guide pad of the carrier to achieve electrical conduction. However, the package carrier is subjected to a photolithography process because of The surface of the package carrier is covered by the protective layer, so there is no mark for the process alignment, which often causes the position of the solder ball/guide pad of the active/passive component in the package carrier to be accurately revealed in the process, thereby affecting another package carrier. When the package carrier is stacked on the package carrier, the conductive connection process of the other package carrier and the solder ball/guide pad in the package carrier are performed. [0003] The main object of the present invention is to provide a A solder ball alignment gas sealing method for a stacked semiconductor package, comprising the steps of: providing a first package carrier, the first package carrier having a first surface, a first solder ball formed on the first surface, a plurality of second solder balls formed on the outer side of the first solder ball, and a protective layer, each of the second solder balls being higher in height than each of the first solder balls The height, and each of the second solder balls has a buried portion and a exposed portion, the protective layer covers the first surface '098143548 Form No. A0101 Page 4 / Total 18 Page 0982074607-0 201123322 Each of the first tin Each of the embedded portions of the ball and each of the second solder balls is aligned with each of the exposed portions of the second solder balls, and a portion of the protective layer is removed to expose the first solder balls; forming a ring a metal line is disposed on the protective layer, the annular metal line is connected to each of the exposed portions of each of the second solder balls; a tin layer is formed on the annular metal line and each of the first solder balls; and a second package carrier is provided The second package carrier has a second surface,

[0004] 098143548 複數個形成於該第二表面之導接點及一對應該環形金屬 線路之金屬層；以及將該第二封裝載體之該些導接點及 該金屬層接合於該第一封裝載體上之該錫層及各該第二 錫球。由於各該第二錫球之高度係高於各該第一錫球之 高度，且該保護層係顯露各該第二錫球之各該顯露部， 因此方便進行對位以準確移除部份該保護層並顯露出該 些第一錫球，使得該第二封裝載體之該些導接點可與該 第一封裝載體之該些第一錫球電性連接，再者，該第一 封裝載體係以該第二錫球及形成於該環形金屬線路之該 錫層與該第二封裝載體之該金屬層接合，以形成氣密封 裝。 【實施方式】 請參閱第1A至1F及2A至2E圖，其係本發明之一較佳 實施例，一種堆疊式半導體封裝件之錫球對位氣密封裝 方法之截面示意圖及上視圖，係包含下列步驟：首先， 請參閱第1A及2A圖，提供一第一封裝載體100，該第一封 裝載體100係具有一第一表面110、複數個形成於該第一 表面110之第一錫球120、複數個形成於該第一錫球120 外側之第二錫球130及一保護層140，各該第二錫球130 之高度係高於各該第一錫球1 2 0之高度，在本實施例中， 表單編號A0101 第5頁/共18頁 0982074607-0 201123322 各該第二錫球130係位於該第一表面11〇之周邊區域上， 且各該第二錫球1 3 〇係具有一埋入部丨3丨及一顯露部i 3 2 ，该保護層140係覆蓋該第—表面11()、各該第一錫球 120及各該第二錫球13〇之各該埋入部131，在本實施例 中，该保護層140之厚度係大於各該第一錫球12〇之高度 ，以凡整覆蓋各該第一錫球12〇 ;接著，請參閱第1B&2B 圖，以各該第二錫球130之各該顯露部132進行對位，並 移除部份該保護層140顯露各該第一錫球12〇 ;之後，請 參閱第1C及2C圖’形成-環形金屬線路2〇〇於該保護層 140上，该裱形金屬線路2〇〇係連接各該第二錫球之 各該顯露部132 ’在本實施例中，該環形金屬線路200材 質係可為銅；接著，請參閱第1D及2DH，形成-錫層300 於該環形金屬線路200及各該第一錫球12〇上，其中各該 第二錫球130之各該顯露部132係具有—頂點U2a，該錫 098143548 層3〇0係具有一錫層表面310，該錫層表面310與該頂點 係可為共平面；之後，請參閱㈣及则提供一 第二封裝载體400 ’該第二封裝载體4〇〇係具有一第二表 面410、複數個形成於該第二表面仙之導接點42〇及一 對應該環形金屬線路200之金屬層430，該導接點420係 可為連接墊或薛球，該金屬層43〇係可為環形線路層；最 後，請參閱第1F圖’將該第二封褒載體彻之該些導接點 及4金屬層430接合於該第—封褒載體1〇〇上之該錫 層300及各該第二錫球13〇之各該顯露部⑶，以電性連 接該第一封裝載體100及第二封裝載體400，並且藉由各 “―錫球130及該錫層300使該第二封裝載體400之該 與該環。。接合，成-氣密環 第6頁/共is頁 0982074 201123322 鲁、、x 70成β堆疊式半導體封裝件之錫球對位氣密封聚 並使该第二封裝載體伽與該第-封裝載體1 00之間具 卜密閉空間S。由於各該第二錫球130之高度係高於各 '•玄第一錫球12〇之高度，且該保護層14〇係顯露各該第二 錫球130之各該顯露部132，因此方便進行對位以準確移 除邛份该保護層14〇並顯露出該些第一錫球12〇，使得該 第二封裝载體400之該些導接點42〇及該金屬層43〇可與 该第一封裝載體1〇〇之該些第二錫球13〇及該錫層3〇〇接 f, 合，再者，藉由該環形金屬線路200、該錫層300及該金 屬層430，使得該第一封裝載體1〇〇及該第二封裝載體 400可達成氣密封裝。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神 和範圍内所作之任何變化與修改，均屬於本發明之保護 範圍。 【圖式簡單說明】 f ' [0005]第1A至1F圖：依據本發明之一較佳實施例，一種堆疊式 半導體封裝件之錫球對位氣密封裝方法之截面示意圖。 第2A至2E圖：依據本發明之一較佳實施例，該堆疊式半 導體封裝件之錫球對位氣密封裝方法之上視圖。 【主要元件符號說明】 E0006] 100第一封裝載體 110第一表面 120第一錫球 130第二錫球 131埋入部 1 3 2顯露部 1 3 2 a頂點 0982074607-0 098143548 表單編號A0101 第7頁/共18頁 201123322 140保護層 2 0 0環形金屬線路 300錫層 310錫層表面 400第二封裝載體 410第二表面 420導接點 430金屬層 S密閉空間 098143548 表單編號A0101 第8頁/共18頁 0982074607-0[0004] 098143548 a plurality of conductive contacts formed on the second surface and a pair of metal layers that should be annular metal lines; and bonding the conductive contacts of the second package carrier and the metal layer to the first package The tin layer on the carrier and each of the second solder balls. Since the height of each of the second solder balls is higher than the height of each of the first solder balls, and the protective layer exposes each of the exposed portions of the second solder balls, it is convenient to perform alignment to accurately remove portions. The first layer of the second solder ball is electrically connected to the first solder balls of the first package carrier, and the first package is further The carrier is bonded to the metal layer of the second solder ball and the tin layer formed on the annular metal line to form a hermetic package. [Embodiment] Please refer to FIGS. 1A to 1F and 2A to 2E, which are schematic cross-sectional views and top views of a solder ball alignment gas sealing method for a stacked semiconductor package according to a preferred embodiment of the present invention. The method includes the following steps: First, referring to FIGS. 1A and 2A, a first package carrier 100 is provided. The first package carrier 100 has a first surface 110 and a plurality of first solder balls formed on the first surface 110. 120. A plurality of second solder balls 130 and a protective layer 140 formed on the outer side of the first solder ball 120. The height of each of the second solder balls 130 is higher than the height of each of the first solder balls. In this embodiment, the form number A0101 is 5th/18 pages 0982074607-0 201123322, each of the second solder balls 130 is located on the peripheral area of the first surface 11〇, and each of the second solder balls is 1 3 Having a buried portion 丨3丨 and a exposed portion i 3 2 , the protective layer 140 covering the first surface 11 (), each of the first solder balls 120 and each of the second solder balls 13 该 the buried portion 131, in this embodiment, the thickness of the protective layer 140 is greater than the height of each of the first solder balls 12〇, Each of the first solder balls 12 is covered; then, referring to FIG. 1B & 2B, the respective exposed portions 132 of the second solder balls 130 are aligned, and a portion of the protective layer 140 is removed. Each of the first solder balls 12 〇; thereafter, refer to FIGS. 1C and 2C 'forming-annular metal lines 2 〇〇 on the protective layer 140, the 金属-shaped metal lines 2 连接 connecting the second solder balls In this embodiment, the annular metal line 200 may be made of copper; then, referring to FIGS. 1D and 2DH, a tin layer 300 is formed on the annular metal line 200 and each of the first tins. Each of the exposed portions 132 of each of the second solder balls 130 has a vertex U2a having a tin layer surface 310, and the tin layer surface 310 and the vertex are For the coplanarity; then, refer to (4) and provide a second package carrier 400. The second package carrier 4 has a second surface 410, and a plurality of guiding points formed on the second surface 42〇 and a pair of metal layers 430 which should be the annular metal line 200, the guiding point 420 can be a connection pad or a Xue ball. The metal layer 43 can be an annular circuit layer; finally, please refer to FIG. 1F', the second sealing carrier is completely connected to the guiding points and the 4 metal layer 430 is bonded to the first sealing carrier 1 Each of the exposed portions (3) of the tin layer 300 and each of the second solder balls 13 is electrically connected to the first package carrier 100 and the second package carrier 400, and by each of the "tin balls 130 and the tin" The layer 300 is such that the second package carrier 400 is bonded to the ring. The gas-filled ring is formed into a hermetic ring. Page 6/total is page 0982074 201123322 Lu, x 70 into a β-stacked semiconductor package. The sealing is concentrated and the space between the second package carrier and the first package carrier 100 is confined. Since the height of each of the second solder balls 130 is higher than the height of each of the first tin balls 12, and the protective layer 14 reveals each of the exposed portions 132 of each of the second solder balls 130, it is convenient Performing alignment to accurately remove the protective layer 14 〇 and revealing the first solder balls 12 , such that the conductive contacts 42 and the metal layer 43 of the second package carrier 400 can The second solder balls 13 of the first package carrier 1 and the tin layer 3 are connected to each other, and further, by the annular metal line 200, the tin layer 300 and the metal layer 430, The first package carrier 1 and the second package carrier 400 can be made airtight. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are cross-sectional views showing a solder ball alignment gas sealing method of a stacked semiconductor package in accordance with a preferred embodiment of the present invention. 2A to 2E are views showing a top view of a solder ball alignment gas sealing method of the stacked semiconductor package in accordance with a preferred embodiment of the present invention. [Main component symbol description] E0006] 100 first package carrier 110 first surface 120 first solder ball 130 second solder ball 131 buried portion 1 3 2 exposed portion 1 3 2 a vertex 0982074607-0 098143548 Form No. A0101 Page 7 / Total 18 pages 201123322 140 protective layer 200 0 annular metal line 300 tin layer 310 tin layer surface 400 second package carrier 410 second surface 420 junction point 430 metal layer S confined space 098143548 Form No. A0101 Page 8 of 18 Page 0982074607-0

Claims (1)

201123322 七、申請專利範圍： 1 . 一種堆疊式半導體封裝件之錫球對位氣密封裝方法，其至 少包含： 提供一第一封装載體，該第一封裝載體係具有一第一表面 、複數個形成於該第一表面之第一錫球、複數個形成於該 第一錫球外側之第二錫球及一保護層，各該第二錫球之高 度係南於各該第一錫球之高度，且各該第二錫球係具有一 埋入部及一顯露部’該保護層係覆蓋該第一表面、各該第 (一錫球及各該第二錫球之各該埋入部； 以各該第二錫球之各該顯露部進行對位，並移除部份該保 護層而顯露各該第一錫球； 形成一裱形金屬線路於該保護層上，該環形金屬線路係連 接各5亥第二錫球之各該顯露部； 形成一錫層於該環形金屬線路及各該第一錫球上； 提供第一封農載體，其具有_第二表面、複數個形成於 。亥第一表面之導接點及一對應該環形金屬線路之金屬層； U 认反 將邊第二封裝載體之該些導接點及該金屬層接合於該第一 封裝載體上之該錫層及各該第二錫球。 如申Μ專利辄圍第1項所述之堆疊式半導體封裝件之錫球 對位氣密封裝方法，其中各該第二錫球係位於該第-表面 之周邊區域上。 士申叫專利牵巳圍第1項所述之堆叠式半導體封裂件之錫球 4對位氣密封裝方法，其中該環形金屬線路材質係為鋼。 如申凊專利範圍第1項所述之堆疊式半導體封裂件之錫球 098143548 <單編號Α0101 第9頁/共18頁 0982074607-0 201123322 =位氧㈣裝方法’其中各該第二錫球之各 有—頂點，該踢層係具有-錫層表面，令錫㈠係具 點係為共平面。 ^錫層表面與該頂 如申請專利範®第〗項所述 對位氣密封裝方法，且中判^/體封聚件之錫球 錫球之高度。，、中㈣相之厚㈣大於各該第- 2請專利範圍第1項所述之堆疊式半導體封裝件之錫球 子位虱密封裝方法，其中該第二 體之間係具有、载體與以-封展載 =申請專利範圍第！項所述之堆疊式半導體封裝件之錫球 、立乳搶封裝方法，其中該導接點係為連接塾或銲球。 098143548 表單編號A0101 第10頁/共18頁 0982074607-0201123322 VII. Patent application scope: 1. A solder ball alignment gas sealing method for stacked semiconductor packages, comprising at least: providing a first package carrier, the first package carrier having a first surface and a plurality of a first solder ball formed on the first surface, a plurality of second solder balls formed on the outer side of the first solder ball, and a protective layer, wherein the height of each of the second solder balls is south of each of the first solder balls a height, and each of the second solder balls has a buried portion and a exposed portion. The protective layer covers the first surface, each of the first (the first solder ball and each of the second solder balls); Each of the exposed portions of each of the second solder balls is aligned, and a portion of the protective layer is removed to expose the first solder balls; a meandering metal line is formed on the protective layer, and the annular metal circuit is connected Each of the exposed portions of each of the 5th second tin balls; forming a tin layer on the annular metal line and each of the first solder balls; and providing a first agricultural carrier having a second surface and a plurality of layers formed thereon. Guide point of the first surface of the sea and a pair of ring metal a metal layer of the line; U acknowledging that the conductive points of the second package carrier and the metal layer are bonded to the tin layer on the first package carrier and each of the second solder balls. The solder ball alignment gas sealing method of the stacked semiconductor package according to Item 1, wherein each of the second solder balls is located on a peripheral region of the first surface. The method for soldering a solder ball of a stacked semiconductor sealing member, wherein the material of the annular metal circuit is steel. The solder ball of the stacked semiconductor sealing member according to claim 1 of the patent application scope 098143548 <single number Α0101 Page 9/18 pages 0982074607-0 201123322 = Bit oxygen (four) mounting method 'where each of the second solder balls has a apex, the kick layer has a tin layer surface, so that tin (a) The point is a coplanar. ^ The surface of the tin layer and the height of the solder ball mounted by the top as described in the patent application, and the height of the solder ball of the body is determined. The thickness of the middle (four) phase (four) is greater than the stacked half of the first paragraph of the second-party patent scope A tin ball sub-seal sealing method of a body package, wherein the second body has a solder ball of a stacked semiconductor package, a carrier and a package-mounted package; The method of squeezing the milk, wherein the guiding point is a joint or a solder ball. 098143548 Form No. A0101 Page 10 of 18 0982074607-0
TW98143548A 2009-12-18 2009-12-18 Sealing package method for stacked semiconductor package using solder ball aligning TWI395278B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172310A (en) * 2022-09-05 2022-10-11 江苏长晶浦联功率半导体有限公司 Three-dimensional packaging structure and manufacturing method thereof

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JP2002158312A (en) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd Semiconductor package for three-dimensional mounting, its manufacturing method and semiconductor device
TWI272685B (en) * 2005-04-01 2007-02-01 Advanced Semiconductor Eng Method for stacking packages in SIP process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172310A (en) * 2022-09-05 2022-10-11 江苏长晶浦联功率半导体有限公司 Three-dimensional packaging structure and manufacturing method thereof
CN115172310B (en) * 2022-09-05 2022-11-29 江苏长晶浦联功率半导体有限公司 Three-dimensional packaging structure and manufacturing method thereof

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