201123192 A00003 33052twf.d〇c/d 六、發明說明： 【發明所屬之技術領域】 法 本發明是有關於-種非揮發性記憶體的存取方法，且 特別是有關於-種非揮射生記憶體裝置的多階重新排序方 【先前技術】 快閃記憶體（flash mem〇ry)是一種可程弋 _gmmmable)的唯讀記憶體(福崎me_y，r〇m)，^ 除並更新所儲存的資料。這種㈣記憶& 中的應用非常廣泛’常見於記憶卡及隨 身碟等作為數位電子產品間交換詞的媒介。 進，且容量越來越大，而使== 體的存取時事來在― 料寫入失敗置為讀），而使得快閃記憶體的資 請參照圖1〜圖2,圖1〜圖2繪示為習知技術之快閃記 201123192 A00003 33052twf.doc/d 憶體的存取方法的動作示意圖。在圖1的繪示中，邏輯區 塊位址(logical block address) LBAN對應的實體區塊位址 (physical block address)為 ΡΒΑ0，資料 W1〜W3 依序被寫入 實體區塊位址ΡΒΑ0的資料區塊中，其中當資料W3被寫 入實體區塊位址ΡΒΑ0時，資料W3所預定寫入之部份記 憶頁已被資料W2所使用，因此必須先抹除實體區塊位址 ΡΒΑ0上所有的資料後才能將資料W3寫入實體區塊位址 ΡΒΑ0。然而，快閃記憶體的資料抹除動作將會耗費許多時 間’且資料W1、W2仍為使用者所欲保留的資料，因此不 能將實體區塊位址ΡΒΑ0上的資料刪除。此時便需要進行 如圖2所繪示的資料存取動作，將實體區塊位址pBA〇的 資料W1複製到邏輯區塊位址LBAN所對應的另一實體區 塊位址PBA1 ’並將資料W2讀出後與資料W3重新排序， 然後將重新排序後的資料W2與W3儲存到實體位址 PBA1。完成邏輯區塊位址LBAN的重新排序操作後，便 可以抹除實體區塊位址ΡΒΑ0的記憶區塊，並將邏輯區塊 位址LBAN改對應到實體區塊位址PBA1，以增加一個可 用的空白實體區塊位址。 然而，由於前述將實體區塊位址PBA〇的資料複製到 實體區塊位址PBA1 (ΡΒΑ0 -> PBA1)的操作會使得記憶體 裝置處於忙綠(busy)狀態而無法回應主機(h〇st)的存取^要 求，因此一般非揮發性記憶體的規範標準均會定義非揮發 性記憶體裝置處於忙碌狀態的最大時間長（即額定忙碌期 限）。習知之快閃記憶體存取方法雖可解決資料寫入時，資 201123192 A00003 33052twf.doc/d 料寫入位置已被使用而無法進行寫人的獅，但 ，中所儲存㈣料量過大時，重新排序資料將❹許多時 ，，而使得㈣記憶_存取動作無法於額社綠期限内 元成’而造成資料存取失敗。 【發明内容】 本發明提供-種非揮發性記憶體控制裝置及並多階201123192 A00003 33052twf.d〇c/d VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for accessing non-volatile memory, and in particular to a non-wave type Multi-level reordering method of memory device [Prior Art] Flash mem〇ry is a read-only memory (Fusaki me_y, r〇m) that can be processed _gmmmable, ^ Stored information. This (4) memory & application is very widespread. It is often used as a medium for exchanging words between digital electronic products such as memory cards and flash drives. Into, and the capacity is getting larger and larger, so that the access to the == body is set to read in the material write failure, and the resources of the flash memory are shown in Figure 1 to Figure 2, Figure 1 to Figure 2 is a schematic diagram of the operation of the access method of the memory of the flash memory 201123192 A00003 33052twf.doc/d. In the illustration of FIG. 1, the physical block address of the logical block address LBAN is ΡΒΑ0, and the data W1~W3 are sequentially written into the physical block address ΡΒΑ0. In the data block, when the data W3 is written into the physical block address ΡΒΑ0, part of the memory page scheduled to be written by the data W3 has been used by the data W2, so the physical block address ΡΒΑ0 must be erased first. The data W3 can be written to the physical block address ΡΒΑ0 after all the data. However, the data erase operation of the flash memory will take a lot of time' and the data W1, W2 are still the data that the user wants to retain, so the data on the physical block address ΡΒΑ0 cannot be deleted. At this time, the data access action as shown in FIG. 2 is required, and the data W1 of the physical block address pBA〇 is copied to another physical block address PBA1′ corresponding to the logical block address LBAN and The data W2 is read out and reordered with the data W3, and then the reordered data W2 and W3 are stored to the physical address PBA1. After the reordering operation of the logical block address LBAN is completed, the memory block of the physical block address ΡΒΑ0 can be erased, and the logical block address LBAN is correspondingly mapped to the physical block address PBA1 to increase an available The blank physical block address. However, since the foregoing operation of copying the physical block address PBA〇 data to the physical block address PBA1 (ΡΒΑ0 -> PBA1) causes the memory device to be in a busy state and cannot respond to the host (h〇 The access requirements of st), therefore the general non-volatile memory specification standards will define the maximum length of time that the non-volatile memory device is busy (ie, the rated busy period). Although the conventional flash memory access method can solve the data writing, the 201123192 A00003 33052twf.doc/d material writing position has been used and it is impossible to write the lion, but the medium is stored (4) when the material amount is too large Reordering the data will be a lot of time, and the (4) memory_access action cannot be completed within the deadline of the social greening period, resulting in data access failure. SUMMARY OF THE INVENTION The present invention provides a non-volatile memory control device and multiple stages
重新排序方法，可聽非揮紐記鐘裝置畴取時間超 過額定的規格值。 本發明提出一種非揮發性記憶體裝置的多階重新排 序方法，其步驟包括當—邏輯區塊位址需要進行重新排序 時’將，輯區塊位址所對應的記憶區塊切分為多個子區 塊接著，在一額定忙碌期限内，執行一主機命令，以及 ^上，子區塊中的-個子區塊進行重新排序。之後，在另 一額定忙碌期限内，執行另一主機命令，以及對上述子區 塊中的另一個子區塊進行重新排序。 在本發明之一實施例中，上述之多階重新排序方法， 括建立一重新排序狀態表，其中重新排序狀態表包含 :邏輯位址攔位與一重新排序階段欄位。當邏輯區塊位址 需要進行重新排序時，將邏輯區塊位址登記於 態表的邏輯位址欄位。 序狀 在本發明之一實施例中，上述之多階重新排序方法， 更包括當上述子區塊全部完成重新排序時，將 址自重新_記縣中職。 ^ 201123192 A00003 33052twf.doc/d 在本發明之一實施例中，上述之重新排序狀態表更包 含一實體位址欄位，以記錄邏輯區塊位址所對應的實體區 塊位址。 1111 在本發明之-實絶例中’上述之重新排序階段搁位記 錄上述子區塊中尚待進行重新排序的子區塊。 在本發明之一實施例中，上述之重新排序階段攔位記 錄上述子區塊中已完成重新排序的子區塊。 在本發明之-實施例中’上述之重新排序階段棚位記 錄多階重新排序中的目前階段狀態。 在本發明之一實施例中，上述之重新排序狀態表建立 在一記憶裝置中。 在本發明之-實施例中’上述之記憶裝置為靜態記憶 體或動態記憶體。 本發明提出一種非揮發性記憶體控制裝置，用以存取 一快閃記憶體，非揮發性記憶體控制裝置包括一控制器， 耦接快閃記憶體，當一邏輯區塊位址需要進行重新排序 時:控制㈣邏輯區塊位址賴應的記憶區塊切分為多個 子區塊，在一額定忙碌期限内，執行一主機命令，以及對 上述子區塊中的一個子區塊進行重新排序，並在另一額定 匕碌期限内’執行另—主機命令，以及對上述子區塊中的 另一個子區塊進行重新排序。 在本發明之一實施例中，上述之非揮發性記憶體控制 2置更包括一記憶裴置，耦接控制器，記憶裝置建立一重 b序狀態表，其中重新排序狀態表包含一邏輯位址攔位 201123192 A00003 33052twf.d〇c/d 重”段攔位，當邏輯區塊位址需要進行重新排 二將"她址登記於重新排序狀態表的邏= 裝置在二:中’上述之非揮發性記憶體控制 收主機命令傳輸心，输㈣11，傳輸介面用以接 取指ί:二限内，執_ 揮發性記憶體的存取時間超過額定I規格^序’以避免非 為讓本發日月之上述特徵和優點能更明 舉實他例，並配合所附圖式作詳細說明如下。下文特 【實施方式】 體存㈣揮發性記憶 Μ図，扪動作不思圖，請同時參照圖3Α〜圖3Β，在圖 對摩1〗的實施例中，邏輯區塊位址⑶颜最多可同時 三個實體區塊位址ρ論〜ρΒΑ2，然不以此為限。The reordering method allows the audible non-window clock device to take longer than the rated specification value. The invention provides a multi-level reordering method for a non-volatile memory device, the steps of which include: when the logical block address needs to be reordered, the memory block corresponding to the block address is divided into multiple The sub-blocks then perform a host command within a nominal busy period, and the sub-blocks in the sub-block are reordered. Thereafter, another host command is executed during another rated busy period, and another sub-block in the above sub-block is reordered. In an embodiment of the invention, the multi-level reordering method includes establishing a reordering state table, wherein the reordering state table includes: a logical address block and a reordering stage field. When the logical block address needs to be reordered, the logical block address is registered in the logical address field of the state table. Sequence In an embodiment of the present invention, the multi-level reordering method described above further includes: when the sub-blocks are all re-sorted, the address is re-remembered. In an embodiment of the present invention, the reordering state table further includes a physical address field to record a physical block address corresponding to the logical block address. 1111 In the real-world example of the present invention, the reordering phase described above records the sub-blocks in the sub-block that have yet to be reordered. In an embodiment of the invention, the reordering stage block records the sub-blocks that have been reordered in the sub-blocks. In the embodiment of the invention - the current phase state in the multi-order reordering of the shed record in the reordering phase described above. In one embodiment of the invention, the reordering state table described above is built into a memory device. In the embodiment of the invention, the memory device described above is a static memory or a dynamic memory. The present invention provides a non-volatile memory control device for accessing a flash memory. The non-volatile memory control device includes a controller coupled to the flash memory when a logical block address needs to be performed. When reordering: control (4) logical block address depends on the memory block divided into multiple sub-blocks, execute a host command within a rated busy period, and perform a sub-block in the above sub-block Reorder and 'execute another-host command during another rated period of time, and reorder another sub-block in the above sub-block. In an embodiment of the present invention, the non-volatile memory control 2 includes a memory device coupled to the controller, and the memory device establishes a heavy b-sequence state table, wherein the reordering state table includes a logical address Block 201123192 A00003 33052twf.d〇c/d heavy "segment block, when the logical block address needs to be re-arranged, "her address is registered in the reordering state table of the logic = device in two: in the above The non-volatile memory control receives the host command transmission heart, the input (four) 11, the transmission interface is used to access the finger ί: within the second limit, the access time of the _ volatile memory exceeds the rated I specification ^ sequence 'to avoid The above features and advantages of the present day and month can be more clearly illustrated, and are described in detail below with reference to the drawings. The following [Embodiment] Body storage (4) Volatile memory Μ図, 扪 action does not think, please Referring to FIG. 3A to FIG. 3A, in the embodiment of the figure, the logical block address (3) can be at most three physical block addresses ρ_ρΒΑ2, but not limited thereto.
Pfiln Α所繪不’資料W1〜W3依序被寫入實體區塊位址 的資料區〜塊中’其中當資料W3被寫入實體區塊位 資料A〇時’資料W3所預定寫入之資料區塊的位置已被 二;、^2所使用。此時為避免過度頻繁地對非揮發性記憶 备卜订抹除與寫入而造成時間的浪費，可將資料W3存入 輯區塊位址LBAN所對應的另一實體區塊位址 1(其為一空白實體區塊位址）。如此一來，便可免去讀 201123192 A00003 33052twf.doc/d 取並抹除實體區塊位址PBAO的資料Wl、W2後，再重新 寫入資料W1〜W3等步驟而省下許多時間。類似地，圖3B 繪示為另一針對邏輯區塊位址LBAN寫入的資料W4，當 資料W4所預定寫入之資料區塊的位置已被實體區塊位址 ΙΈΑ0的資料W2以及實體區塊位址PBA1的資料W3所使 用時，可將資料W4存入到邏輯區塊位址LBAN所對應的 另一實體區塊位址PBA2(其為一空白實體區塊位址）。 依此類推，邏輯區塊位址LBAN所對應的三個實體區 ，位址PBA0〜PBA2可提供給寫入邏輯區塊位址LBAN的 資料儲存，而當資料的預定寫入位置在三個實體區塊位址 PBA0〜PBA2中皆已被使用時，便需要對邏輯區塊位址 LBAN進行重新排序，也就是對非揮發性記憶體中邏輯區 塊位址LBAN所職衫個實體區齡址pBAG〜pBA2進 行重新排序。町將列舉本發明之實施例，以提供不同於 習知技術之非揮發性記憶體的重新排序方法，避免如習知 因重新排序資·費過多時間，而使得快閃記情 體的存取動作無法於限定的時間内完成。 心 M卜請參 的多階會新Μ:二 * 的非揮發性記憶體 夂昭C 的一實施例的動作流程圖。並請同時 階重續示的本㈣的轉發性記憶體的多 斤排序方法的實施例的動作示意圖。 在本實施例中，其步驟舍杯.音止 址需要推m 百先，當一邏輯區塊位 二，進仃重新排料，輯邏無·輯對應 刀分為多個子區塊(步驟s彻）。例如圖犯所示 201123192 A00003 33052twf.doc/d 輯區塊位址LB AN所對應的三個银μ ΡΒΑΟ〜ΡΒΑ2需要進行㈣Μ只體區塊位址 ★「“ 要進重新排序。在本實施例中是葬由達 以雜狀態表」來管理多階重新排序的階段^態， 確保王料區_可以完成4_序 :要=重，㈣邏輯區塊位址登記於重^ 二1如1多階重新排序的階段狀態的方式並不二此Pfiln Α not painted 'data W1 ~ W3 are sequentially written to the physical block address of the data area ~ block 'When the data W3 is written to the physical block data A ' 'data W3 is scheduled to write The location of the data block has been used by two; In this case, in order to avoid waste of time caused by excessively frequent erasing and writing of the non-volatile memory, the data W3 may be stored in another physical block address 1 corresponding to the block address LBAN ( It is a blank physical block address). In this way, you can save time by reading 201123192 A00003 33052twf.doc/d and erasing the data of the physical block address PBAO Wl, W2, and then rewriting the data W1~W3. Similarly, FIG. 3B illustrates another data W4 written for the logical block address LBAN. When the location of the data block to which the data W4 is scheduled to be written has been the physical WB address ΙΈΑ0, the data W2 and the physical area. When the data W3 of the block address PBA1 is used, the data W4 can be stored in another physical block address PBA2 (which is a blank physical block address) corresponding to the logical block address LBAN. And so on, the three physical areas corresponding to the logical block address LBAN, the address PBA0~PBA2 can be provided to the data storage of the write logical block address LBAN, and when the predetermined write position of the data is in three entities When the block addresses PBA0~PBA2 have been used, the logical block address LBAN needs to be reordered, that is, the logical block address in the non-volatile memory is the physical area address of the LBAN. pBAG~pBA2 are reordered. The embodiment of the present invention will be exemplified to provide a reordering method for non-volatile memory different from the prior art, so as to avoid the flashing of the ticker as long as the re-sorting time is too long. Unable to complete in a limited time. The multi-step meeting of the heart M: The non-volatile memory of the second * The flow chart of an embodiment of the C. In addition, the operation diagram of the embodiment of the multi-pitch sorting method of the forwarding memory of the present (4) is continued. In this embodiment, the step of the sound box needs to push m hundred first, when a logical block is two, the re-discharge is entered, and the corresponding knife is divided into multiple sub-blocks (step s thorough). For example, the figure is shown in 201123192 A00003 33052twf.doc/d The block address LB AN corresponds to the three silver μ ΡΒΑΟ ~ ΡΒΑ 2 need to be carried out (4) Μ only body block address ★ "" to re-order. In this embodiment, the stage of the multi-level reordering is managed by the burial state table, and the king material area _ can be completed 4_order: to = heavy, (4) logical block address is registered in the ^ 2, such as 1 multi-order reordering stage state is not the same
== 其他實施例中可以使用暫存器來記錄多階 重新排序的目前階段狀態。 如圖5A的繪示，非揮發性記憶體中邏輯區塊位址 LBAN所對應的實體區塊位址pBA〇〜pBA2可 個子區塊SO〜S3，而重新排序狀態表可如下列表i ^示、：== In other embodiments, a scratchpad can be used to record the current phase state of a multi-level reorder. As shown in FIG. 5A, the physical block addresses pBA〇~pBA2 corresponding to the logical block address LBAN in the non-volatile memory may have sub-blocks SO~S3, and the reordering status table may be as follows: ,:
邏輯位址 LBAN 實體位址 重新排序階段 PBA0 〇 PBA1 PBA2 表1 重新排序狀態表可包括邏輯位址欄位、實體位址欄位 以及重新排序欄位。其中「邏輯位址」欄位記錄需進行重 新排序的邏輯區塊位址，「實體位址」攔位記錄邏輯區塊 位址所對應的實體區塊位址，另外「重新排序階段」欄位 則記錄多階重新排序中目前的階段狀態。例如，重新排序 階段攔位可記錄在子區塊S0〜S3中目前已完成重新排序的 201123192 A00003 33052twf.doc/d 子區塊的名稱或是數量，或是印鐮. 進行重新排相子區塊的名稱歧數量$ 序階段棚位被用來記錄多階重== 二t :0广…前為第1個階段狀態。子區 塊S0將會在此弟Η_段狀態令被重新排序，而盆 區塊S1〜S3則不會被重新排序。在此， _ = =靜=:r’一置可= 另外請特別注意，分割的子區塊的數目不一定要 4!。在本發明的精神中’子區塊的數目可 依據實際的狀況來分割’而至少為丨個。舉例來說忙 實體區塊位址所職的資料區塊的大小來 塊越大時所需切·的子區塊數目越多，相反地 區塊越小時所需切割出的子區塊數目越少。 接著，在一額定忙碡期限内，執行一主機 對上述分割出的子區塊中的一個子區塊進行重新排序(步 驟S42〇)。其中，額定忙碌期限為非揮發性記憶體執行任 何資取時所預設的規格值(例如250毫秒），而主機命 令可旎疋主機所發出要對某一邏輯區塊位址進行存取的^ 求。一般而言，步驟S420所述主機命令所存取的邏輯區 塊位址以及進行重新排序的邏輯區塊位址二者可以是不相 同的。非揮發性記賊必須在駭忙袖㈣完成主機> 令的相_作。舉例來說，若线命令指示對邏輯區壤^ 址LBAN進行資料的寫入，則非揮發性記憶體裝置必須在 201123192 A00003 33052twf.doc/d 250毫秒内完成對邏輯區塊位址LBAN的寫入操作，並將 所處忙碌狀態解除並回報給主機。然而，一般寫入的動作 均少於額定忙碌期限(例如僅需120毫秒)即可完成，此時 便可利用剩餘的時間（130毫秒)進行邏輯區塊位址LBAN 的部分重新排序。 例如，如圖5A所示可先將邏輯區塊位址LBAN所對 應s己憶區塊之子區塊S0進行重新排序。也就是說，將實 φ 體區塊位址ΡΒΑ0、PBA1與PBA2的子區塊s〇的資料讀 出並進行更新操作，然後將更新後的資料寫入到另一資料 區塊中（例如實體區塊位址PBA100所對應的資料區塊）。 另外，值得注意的是，主機命令所指示執行的資料存取動 作並不限定於需要進行重新排序的邏輯區塊位址（亦即邏 輯區塊位址LBAN)，當主機命令所指示對邏輯區塊位址 LBAN以外的邏輯區塊位址進行存取時，亦可利用剩餘的 時間對邏輯區塊位址LBAN進行重新排序。完成子區塊's〇 的^新排序操作後，表1所示重新排序階段欄位會被更新 為1」，表示目刖為弟2個階段狀態而準備對下一個子區 塊S1進行重新排序。 類似地，當非揮發性記憶體因執行另一主機命令而處 於另一個忙碌期間時，非揮發性記憶體必須在另一額定忙 1期限(以下稱第二期限)内完成所述另—主機命令的相關 二枓存取操作。若完賴述另—域命令的侧操作後亦 有剩餘的時間，則可以在所述第二期限内對上述分割出的 子區塊SKS3中的另-個子區塊進行重新排序（步驟 201123192 A00003 33052twf.doc/d S430)。如圖5B所不，可利用剩餘時間對子區塊S1進行 重新排序’而將子區塊S1 #已更新資料寫人到實體區塊 位址PBA100對應的賁料區塊中。完成子區塊S1的重新排 序操作後，表1所示重新排序階段櫚位會被更新為「2」， 表示目前為第3個階段狀態而準備對下一個子區塊S2進 行重新排序。此時重新排序狀態表所紀錄的内容可如下列 表2所示： 邏輯位址 實體位址 重新排序階段 LBAN PBA0 2 PBA1 PBA2 表2 依此類推，可利用在其他額定忙碌期限内執行其他主 機命令的剩餘時間來進行剩餘的兩個子區塊§2、S3。當所 有的子區塊SO〜S3皆寫入到實體區塊位址PBA100時，邏 輯區塊位址LBAN的重新排序便告完成。此時邏輯區塊位 址LBAN所對應的實體區塊位址變為PBA100 (如圖5C所 示）’而原本與邏輯區塊位址LBAN所對應的實體區塊位 址ΡΒΑ0〜PBA2也可被清除而成為空白的實體區塊位址(釋 放實體區塊位址ΡΒΑ0〜PBA2)。另外，重新排序狀態表所 紀錄的邏輯區塊位址LBAN、實體區塊位址pba〇~pba2 以及重新排序階段欄位中所紀錄的資料也將全部被刪除。 12 201123192 A00003 33052twf.doc/d 區塊二卜並是序狀態表所記錄的邏輯 行重新排序時，亦會被登: 己到；=輯區塊位址亦需要進 表3所示：胃裉且°己至j重新排序狀態表中，如下列Logical Address LBAN Physical Address Reordering Phase PBA0 〇 PBA1 PBA2 Table 1 The reordering status table can include logical address fields, physical address fields, and reordering fields. The "Logical Address" field records the logical block address to be reordered, the "Physical Address" block records the physical block address corresponding to the logical block address, and the "Reordering Stage" field. Then record the current phase state in multi-level reordering. For example, the reordering stage block can record the name or number of the 201123192 A00003 33052twf.doc/d sub-blocks that have been reordered in the sub-blocks S0-S3, or the stamps. The number of names of the blocks is different. The stage stage is used to record the multi-order weight == two t: 0 wide... before the first stage state. The sub-block S0 will be reordered in this case, and the blocks S1 to S3 will not be reordered. Here, _ = = static =: r' can be set = In addition, please note that the number of divided sub-blocks does not have to be 4! In the spirit of the present invention, the number of sub-blocks can be divided according to actual conditions, and at least one. For example, the size of the data block in which the busy physical block address is located is larger. The larger the block size, the more the number of sub-blocks that need to be cut. On the contrary, the smaller the block, the smaller the number of sub-blocks to be cut. . Next, a host performs a reordering of one of the divided sub-blocks within a rated busy period (step S42). The rated busy period is a specification value (for example, 250 milliseconds) preset by the non-volatile memory when performing any acquisition, and the host command can be used by the host to access a certain logical block address. ^ Seek. In general, the logical block address accessed by the host command and the logical block address to be reordered in step S420 may be different. The non-volatile thief must complete the host> command in the busy sleeve (4). For example, if the line command indicates that data is written to the logical area LBAN, the non-volatile memory device must complete writing to the logical block address LBAN within 250 milliseconds of 201123192 A00003 33052twf.doc/d. Enter the operation and release the busy status and report it to the host. However, the general write action is less than the rated busy period (for example, only 120 milliseconds), and the remaining time (130 milliseconds) can be used to partially reorder the logical block address LBAN. For example, as shown in FIG. 5A, the sub-block S0 of the logical block address LBAN corresponding to the block can be reordered. That is to say, the data of the real φ body block address ΡΒΑ0, PBA1 and the sub-block s〇 of PBA2 are read out and updated, and then the updated data is written into another data block (for example, an entity) The data block corresponding to the block address PBA100). In addition, it is worth noting that the data access action indicated by the host command is not limited to the logical block address (ie, the logical block address LBAN) that needs to be reordered, when the host command indicates the logical region. When the logical block address other than the block address LBAN is accessed, the logical block address LBAN may be reordered by the remaining time. After completing the new sort operation of the sub-block 's〇, the reordering stage field shown in Table 1 will be updated to 1", indicating that the next sub-block S1 is reordered after the target is 2 stages. . Similarly, when the non-volatile memory is in another busy period due to execution of another host command, the non-volatile memory must complete the other host within another rated busy 1 period (hereinafter referred to as the second period). The associated two-way access operation of the command. If there is any remaining time after the side operation of the other domain command, the other sub-blocks in the divided sub-block SKS3 may be reordered in the second period (step 201123192 A00003) 33052twf.doc/d S430). As shown in Fig. 5B, the sub-block S1 can be reordered by the remaining time, and the sub-block S1 #updated data is written to the stock block corresponding to the physical block address PBA100. After the reordering operation of the sub-block S1 is completed, the reordering phase shown in Table 1 will be updated to "2", indicating that the next sub-block S2 is ready to be reordered for the third stage state. The content recorded in the reordering status table at this time can be as shown in the following list 2: Logical Address Entity Address Reordering Phase LBAN PBA0 2 PBA1 PBA2 Table 2 and so on, can be used to execute other host commands within other rated busy periods The remaining time is for the remaining two sub-blocks § 2, S3. When all of the sub-blocks SO to S3 are written to the physical block address PBA100, the reordering of the logical block address LBAN is completed. At this time, the physical block address corresponding to the logical block address LBAN becomes PBA100 (as shown in FIG. 5C), and the physical block address ΡΒΑ0~PBA2 corresponding to the logical block address LBAN can also be Clear the physical block address that becomes blank (release the physical block address ΡΒΑ0~PBA2). In addition, the logical block address LBAN, the physical block address pba〇~pba2, and the data recorded in the reordering stage field recorded in the reordering status table will also be deleted. 12 201123192 A00003 33052twf.doc/d Block 2 and the logical row reordered by the sequence status table will also be posted: already arrived; = block block address also needs to be shown in Table 3: stomach cramps And ° to j reorder the status table, as below
塊位LBAN $未完成重新齡時，邏輯區 Λ須進行重新排序，此時邏輯區塊位址 表。而重新排序狀態 實°°塊位址進仃乡階重新财的先後順序可以 齡，例如可依照登糾重新排序狀絲中的時 間先後，亦或是資料的重要性等等來決定。 ,卜二：=十對本發明的用以存取非揮發性記憶體的記 裝置提出-實施例來加以說明，期使本領域具通 爷知識者都可以瞭解本發明並具以實施。 請參照圖6,圖6繚示本發明的一實施例的非揮發性 13 201123192 AUUUUJ 33052twf.d〇c/d 記憶體控制裝置600。記憶體控制裝置6〇〇耦接非揮發性 記憶體640，並對非揮發性記憶體64〇進行存取控制。非 揮發性記憶體640可以是快閃記憶體、電子可抹除式唯讀 記憶體等。記憶體控制裝置6〇〇包括控制器61〇、記憶裝 置620以及傳輸介面63〇。其中，控制器61〇耦接至非揮 發性記憶體640。且控制器61〇在邏輯區塊位址需要進行 ==時，__續細麵塊切_ 此外，當控制器610接收主機命令時，控制器61〇在 額疋忙碌期限内，執行主機命令並對分割出的子區塊中的 二個子區塊進行重新排序。另外，控制器㈣亦在另 = 行另-主機命令，以對分割出的子區塊 宁的另一個子區塊進行重新排序。 建立:己_則耦接控制器610。記憶裝置620用以 ^欄2^ 表’其中重新排序狀態表包含一邏輯位 新排序時欄位，當邏輯區塊位址需要進行重 r攔位，並在控制器61G分割出的子區塊 3 排序^字邏輯區塊位址自重新排序記錄表中二成重新 發明的記Γ控制裝置議的動作細節相信在本 _ 此處不再對記.隨控制裝置 值得注意的是，記憶體控制裝置_還包括有傳輸介 201123192 33052twf.doc/d 面630。傳輸介面630耦接控制器610’用以接收使用者對 非揮發性記憶體640所傳送的主機命令。當然，傳輸介面 630也可以用來傳輸存入非揮發性記憶體64〇或由非揮發 性記憶體640讀出的資料。這種傳輸介面的功能及建構^ =，為本領域具通常知識者所熟知的技術，在此不多詳述。 綜上所述，本發明利用利用在額定忙碌期限内，執行* 取指令_餘_ ’來對子區塊進行錄排序。如此: 便不需要另外再蚊發丨重㈣序社機命令，僅 指令執行_餘時間即可完成子區塊㈣新排序，可 非揮發性記龍的使用效率，並職轉發性記憶體^ 取時間超過額定的規格值。 、存 雖然本發明已以實施例揭露如上，然豆 =明，任何所屬技術領域+具有通f知識者 = 本發明之精神和範_，當可作脫離 發明之保護範圍當視後附之申請專利：二;本 【圖式簡單說明】 的動m2,示為習知技術之㈣記憶體的存取方法 體存=::::本發明-實施例之非揮發性記憶 法的3:=:=:發性記憶想的多階重新排序方 圖5A- 傾5C繪示為本發明的非揮發性記憶體的多階 15 201123192 33052twf.doc/d 重新排序方法的實施例的動作示意圖。 圖6繪示本發明的一實施例的非揮發性記憶體控制裝 置的方塊圖。 【主要元件符號說明】 600:記憶體控制裝置 610 :控制器 620 :儲存裝置 630 :傳輸介面 ΡΒΑ0〜PBA100 :實體區塊位址 LBAN :邏輯區塊位址 W1〜W4 :資料 S0〜S3 :子區塊 S410〜S430:多階重新排序的步驟When the block bit LBAN $ is not completed, the logical area does not need to be reordered, at this time the logical block address table. The reordering state The actual order of the block location can be determined by the order of the re-ordering of the township. For example, it can be determined according to the time sequence in the reordering of the wire, or the importance of the data. And the following is a description of the present invention for accessing non-volatile memory, and it will be explained by those skilled in the art that the present invention can be implemented and implemented. Please refer to FIG. 6. FIG. 6 is a diagram showing a non-volatile 13 201123192 AUUUUJ 33052 twf.d〇c/d memory control device 600 according to an embodiment of the present invention. The memory control device 6 is coupled to the non-volatile memory 640 and performs access control on the non-volatile memory 64. The non-volatile memory 640 may be a flash memory, an electronic erasable read only memory, or the like. The memory control device 6A includes a controller 61, a memory device 620, and a transmission interface 63A. The controller 61 is coupled to the non-volatile memory 640. And the controller 61 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ And reordering the two sub-blocks in the segmented sub-block. In addition, the controller (4) also performs another-host command on the other line to reorder another sub-block of the divided sub-block. Established: coupled to controller 610. The memory device 620 is configured to use the column 2' table, wherein the reordering state table includes a logical bit new sorting field, and when the logical block address needs to be heavily r-blocked, and the sub-block is segmented by the controller 61G. 3 Sorting the word logical block address from the reordering record table. The details of the action of the reinvented device control device are believed to be no longer in this _. The control device is worth noting that the memory control The device_ also includes a transmission medium 201123192 33052twf.doc/d face 630. The transmission interface 630 is coupled to the controller 610' for receiving host commands transmitted by the user to the non-volatile memory 640. Of course, the transmission interface 630 can also be used to transfer data stored in or read from the non-volatile memory 64. The function and construction of such a transmission interface is well known to those skilled in the art and will not be described in detail herein. In summary, the present invention utilizes the use of *fetching____ to perform the sorting of sub-blocks within the rated busy period. So: you don't need another mosquito to send a heavy weight (4) order machine command, only the command execution _ remaining time can complete the sub-block (four) new sorting, the use efficiency of non-volatile record dragon, concurrent forwarding memory ^ Take time exceeds the rated specification value. Although the present invention has been disclosed in the above embodiments, the present invention is in the technical field and has the knowledge and scope of the present invention, and can be used as a protection patent from the scope of the invention. : 2; This is a simple description of the motion m2, shown as a conventional technique (4) memory access method body =:::: The non-volatile memory method of the present invention - 3:=: =: Multi-order reordering of the desired memory Figure 5A - Pour 5C is a schematic diagram of the operation of the embodiment of the multi-order 15 201123192 33052 twf.doc/d reordering method of the non-volatile memory of the present invention. Figure 6 is a block diagram of a non-volatile memory control device in accordance with an embodiment of the present invention. [Main component symbol description] 600: Memory control device 610: Controller 620: Storage device 630: Transmission interface ΡΒΑ0~PBA100: Physical block address LBAN: Logical block address W1~W4: Data S0~S3: Child Blocks S410 to S430: steps of multi-order reordering