201122869 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種輔助方法，特別是晶圓佈局輔助方法。 【先前技術】 由於積體電路不如傳統電路一般，可以事先在麵包板 (breadbcwd)或印刷電路板（PrinteddrcuitbQa⑷上做實驗來驗 證電路設計結果。為了提高積體電路生產時的&率（yidd)及降 低成本，設計人員在設計電路時，輯人員會使用模擬軟體模擬 電路的效能。在完成模擬之後，才會進行積體電路的生產。 電路模擬軟體主要的功能是模擬電子元件的物理現象。在此 軟體中，制者只要定義-電財的元件的參數以及元件之間連 接關係，並且放入測試訊號以及選擇模擬的種類，使用者即可得 到此電路的電路響應(response)。舉例而言，對於一個金屬氧化物 半導體场效電晶體（Metal Oxide Semiconductor Field-Effect201122869 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an auxiliary method, particularly a wafer layout assisting method. [Prior Art] Since the integrated circuit is not as good as the conventional circuit, the circuit design result can be verified in advance on a breadbcwd or a printed circuit board (PrinteddrcuitbQa(4). In order to improve the & rate (yidd) of the integrated circuit production And to reduce costs, designers design the circuit, the personnel will use the performance of the analog software analog circuit. After the simulation is completed, the production of the integrated circuit will be carried out. The main function of the circuit simulation software is to simulate the physical phenomenon of electronic components. In this software, the manufacturer can obtain the circuit response of the circuit by simply defining the parameters of the components of the electricity and the connection relationship between the components, and putting the test signal and selecting the type of the simulation. For a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field-Effect
Transistor ’ M〇SFET _ M〇s電晶體），使用者需要定義的參數 為半導體的種類、閉級(Gate)縣度(Length)、寬度(Width)以及指 數(Finger number)。 隨著半導體的技術日新月異，積體電路的製程也不斷地演 進。在從深次微米(deepSUbmicronmeter)製程，演進到當今的奈米 (nanometer·)製程的過程中，因為元件尺寸的不斷縮小，許多非理 想效應也伴隨而生。其巾有許多非理想效應與元件的佈局以及相 對位置有關。在這裡，_以舰層長度(LengthGfdiffijsiGn L〇D) 201122869 效應參數融仔練明。概層長度效叙有人稱錢溝槽應力 效應(Shall〇W-Trench-Is〇lati〇nStressEffect)，這是 M〇s 電晶體的特 性會與其閘極(Gate)到擴散層區域邊緣(Edge 〇f the Diffiisi〇n 的長度有關。在這裡我們通常需要佈局相關的參數从和sb來增 進電路模擬的精確度，从和SB是電晶體的閘極分別到兩個擴^ 層區域邊緣的距離。由於我們㈣在元件佈騎會好個電晶體 共用-個擴散層，電晶體的相對位置與佈局方法可能極大的改變 這些參數。元件的佈局與相對位置通f會在電路模擬之後的佈局 P皆段才會被決定。在電路顯的階段將無法將得知佈局相關參 數，也就無法了解其對於電路的影響。 【發明内容】 鑑於以上關題，本發明係提出—晶_局輔财法、以及 系統。此方法用以協㈣路設計人員在設計電路時， 關參數。 此晶圓佈弱助方法包括：（A)讀取—f路資訊職，該電路 資訊播案包純油元件、概個龍顧元件的元件參數和複 數個連接_ ; (B)根據職路:#訊難產生—_制者介面介 面’以供-使用者進行預估佈局編排(晴^⑽咖柳伽）； (C)接收由該使用者輸入之至少一預估佈局編排；⑼判斷是否已完 成預估佈局’·及(E)若已完成預估佈局，職行下述步驟：根據元 件種類、元件參數及難佈域排，產生佈局相關參數。 綜合以上所述，根據本發明之晶圓佈局辅助方法，可在佈局 201122869 2前使用-_化_估佈局編排預估佈局後的佈局相關參數， :而在電路模㈣考慮這些佈局相_參數，以減少佈局前電路 模擬的結果與佈局後電路模擬的結果的差異。 、二上之關於本發_容之說明及以下之實施方式之說明係用 =不範與解釋本發明之精神與原理，並且提供本發明之專利申請 範圍更進一步之解釋。 【實施方式】 以下在實施方式巾詳細敘述本㈣之詳細特徵以及優點，其 内容足以使任何《侧技藝者了解本㈣之技軸容並據以實 施’且根據本說明書所揭露之内容、ΐ請專利範圍及圖式，任何 熟習相關技藝者可輕§地理解本發_關之目的及優點。以下之 實施例係進-料細制本拥讀點，域點限制本 發明之範疇。 本發月所提出之方法，可為—工具程式，使用於—電腦或是 其他具有運算功能的電子裝置。社具程式不限於任何的程式語 言，電腦亦不限於任何平台。 、本發明所提出之電腦可讀取之記錄媒體，係為硬碟、光碟、 =碟或是記《，歧其他的触儲錢置。儲姐此記錄媒體 當中的電腦程式碼，所執行的魏與上述缸具程式相同。 月…第1圆』’係為本發明之第一實施例之流程圖。此實 括下歹j步驟.讀取一電路資訊檔案⑻⑼，電路資訊檀案包 括複數個元件、_元件·數個树參數和元件的連接關 201122869 =產生—_使用者介面伽帅 一⑽獅);接收由使用者輸入之至少一預估佈局編排 剛，判斷㈣成預估佈局編排(㈣；以及， 局編排，則執行下述步驟.抽秘_丨 神 .根據預估佈局編排，產生佈局相關參 數(S150)。 〆 在步驟S11〇中’電路資訊檔案為電路圖(Schematic)或是電路 連接表(Ne㈣。電路_是連接表包括複數航件、複數個 對應該7L件的元件參數和複數個連接_。上述的元件為金屬氧 化物半導體场效電晶體、雙載子接面電晶體卿咖此㈣加 Transistor ’_、電阻、電容、電感、二極體仰〇岭電獅、 電流源、喊源、接地等。每個元件對應至少—侧元件參數。 以氧化金屬半導體為例，這些元件參數為_的長、寬、指數等 等。 請參照『第2A圖』，係為一示意用之電路連接表。此電路連 接表内·件參數，細目前在電路設計±f _ 6圖(齡却 Short-channel IGFET Model)電路模型所使用的元件參數為例。此 電路由-P型氧化金屬半導體錢_ N型氧化金屬半導體所組 成。此電路連接表包括元件名稱、元件參數以及元件間的連接關 係°『第2B圖』則為-示意用的電路圖。此電路包括一電流源、 一電阻R1 ’二個N型氧化金屬半導體、_2、nm3以及一 個P型氧化金屬半導體PM1以及一接地。 在步驟S120中’圖形介面根據元件的參數(比如說長或是寬）， 201122869 顯示基於相對大小的元件的幾何做。顧形介面中可顯示元件 名稱。此外’在圖形介面中，可對於不同屬性的元件標記不同的 顏色。使用者能根據不同的顏色，快速的區別出不同屬性的元件。 使用者〃面包括確箱局完成、儲存佈局卿或是讀取佈局圖形 等的指令。 於本發明之—實施例中，此工具程式會先將所有元件分類成 可佈局元―)以及不可佈局元件(n〇nphysicai ，vlce)可佈局兀件可在半物製程時形成於晶圓上，比如說為 氧金屬半導體、雙載子接面電晶體卿心juncti〇n Transi_， BJT)電阻、電谷、電感、二極體(diGde)。不可佈局元件為電壓 源、電流源、訊號源、接地、理想電阻、理想電容、理想電感、 理想電子it件、寄生電子树料。接著，此玉具程式僅將可佈 局元件顯示於圖形介面。 『第2C圖』係為根據『第2B圖』產生的圖形介面。此圆形 介面中，可佈元件為-餘R1，三個N型氧化金屬半導體 顧卜NM2、NM3以及-個p型氧化金屬半導體pM1。在此圆上 P型氧化金屬半導體PM1賴示了賊的井區區域。 於本發明之-實施例中，當電路資訊檔案有多階層結構 (Hierarchy)時’ _者可選取是否魏全部錯層結構的預估佈局 編排’或是特定次、線路(Sub_circui城下層電路方塊(Sub bl〇c_ 預估佈局編排。這裡也可以接受過去已經完成_估佈局編排為 新預估佈局編排的一部分。 201122869 在步驟S130中，接收由該使用者輸入之至少一預估佈局編 排。使用者輸入的預估佈局編排包括元件的位置、元件的放置角 度。於本發明之一實施例中，預估佈局編排更可包括在元件周圍 加上啞元件(dummydevice)，或是將兩個以上的元件使用交錯結合 (interleaving)的方式合併，或是將兩個以上的元件使用並排 (side-by-side)的方式合併，或是將元件的井區(weu)變大。 在步驟S130中，使用者可使用滑鼠或鍵盤或觸控螢幕等輸入 • 裝置輸入預估佈局編排。 在步驟S130中’另可接收使用者輸入的可佈局元件的複數個 組合關係。也就是說’使用者可選取、移動、轉動、合併、或分 離圖示的元件以達成預估佈局編排。 在步驟S130中，於本發明之另一實施例中，至少一個可佈局 元件可從預估佈局編排中移除。 在步驟S130中，於本發明之另一實施例中，可同時產生一或 參數個使用者介面。使用者介面可以顯示元件的資訊。使用者介面 可以提供使用者一個方便輸入的介面，達成預估佈局編排。 在步驟S130中，於本發明之另一實施例中，使用者介面可以 有文字輸入空格、拉下式視窗或點選按鈕等方式輸入。 在步驟S130中’於本發明之另一實施例中，當使用者選取某 -元件時，在圖形制者介面或使用者介面上麵示相關的元件。 在步驟S130中，於本發明之另一實施例中，當使用者選取某 一元件時’會在電路資訊檔案上標示(HighUght)出來。 201122869 "月參照第2D圖』’係為根據圖形介面輸入的預估佈局編排。 於此實施例中，電阻R1的方向做九十度的旋轉，N型氧化金屬半 導體ΝΝΠ、NM2以交錯結合的方式合併。丽卜觀2的組合只 是其連接關係中的-種。N魏化金屬半導體麵3的兩側加上了 °亞元件，P型氧化金屬半導體PM1的井區被擴大。 在步驟S130中，於本發明之另一實施例中，使用者可指定特 疋端點間的連線，在計算佈局相關參數時可計算此一連線上與連 線相關的佈局相關參數。 接著，執行步驟S140中。電路設計者在完成預估佈局編排後， 會根據使用者介面傳送確認預估佈局編排完成指令。當接收預估 佈局編排完成指令後，判斷已完成預估佈局編排。 若已完成預估佈局編排時，可根據預估佈局編排產生對應的 佈局相關參數。此佈局參數包括擴散層長度效應參數、井區鄰近 效應參數科1BSM4電賴㈣言，其產生纖層長度效應 參數的方法，可參考 BSIM4.4.0 Manual Copyright © 2004 UC Berkeley” 中的”Chapter 13: Stress Effect Model”。 在此所指的佈局相關參數通常係指半導體製程中許多不同層 間的相對距離、疊交的面積或長寬比的參數。 在本發明一實施例或是多個實施例中，計算佈局相關參數可 根據元件種類、元件參數與預估佈局編排所產生。 若在步驟S130中使用者有指定特定端點間的連線，經由連接 線所產生的寄生電容以及寄生電阻可以被計算。 201122869 計算佈局彳目關參數可 在本發明一實施例或是多個實施例中 以由量測特定邊緣的距離的方式產生。 、在本發明-實施例或是多個實施例中，計算佈局相關參 以辅助以查表(L〇〇k-Uptable)或公式的方式產生。 在本發明—實_或是多個實施射，計算柄_夫數可 根據元件_、元雜數與树的合併方式所產生。 在本發明-實施例或衫個實_巾，計算柄相關來數可 根據元件_、元件參數與疫树龍量所產生。 此工具程式可提供使用者佈局侧的參數。使用者可以將复 輸入電路資訊檔案，並進行電路模擬。 一 於本發明之-實施例或是多個實施例中，虹具程式可將佈 局相關的參數賴進電路資輯^ 者可贿収新後 路資訊檔案進行電路模擬。 於本發明之-實施例或衫個實施例中，在預估佈局編排中 的元件位«訊可觀取出。此元件紐魏可提供更進一步的 佈局程序所使用。 多‘、、、第2E圖』，係為將佈局相關的參數更新進電路資訊 檔案『第2A圖』之後的結果。 口月〜、第3圖』’係為本發明之第二實施例之流程圖。此實 關〇括下列步驟.讀取一電路資訊檔案卿⑺，電路資訊檔案包 括複數個το件、該些疋件的複數個元件參數和該些元件的連接關 係；根據電路資訊_產生—_朗者介面(s22G);接收由使用 201122869 者輸入之至少-預估佈局編排(S23〇);判斷是否完成預估佈局編排 _)’·若完成預估佈局編排，則執行下述步驟：根據預估佈居編 排’產生佈局相關參數(S250);使用佈局相關參數進行電路模擬 ⑹⑽續進行預估佈局編排阳⑺，若是判斷結果為 繼續進行預估佈局編排時’則回到步驟(S23〇)，重新接收由該使用 者輸入之預估佈局編排。 明參照『第4圖』’係為本發明之第三實施例之流程圖。此實 施例包括下列步驟··讀取一電路資訊檔案_)，電路資訊播案包籲 括複數個元件、元件的複數個元件參數和該些元件的連接關 係；根據電路資訊職產生一圖形使用者介面;接收由使用 1至> 預估佈局編排(S330);判斷是否已完成佈局編排 ⑻4〇) ’·若已完成佈局，則執行下述步驟々據預估佈局編排，產 生佈f相Μ參數(S35G);伽佈局糊參數妨冑賴擬(s36〇)丨 判斷疋否需要改動電路資訊槽案(S37〇)，若是判斷結果為需要改動 電路資訊職時’對電路資訊檔案做合適的修改(S380)，並回到步癱 驟(S310) ’餘更新後的·#訊播案。 在此^施例中，重新回到步驟(_)後。再接續執行步驟(S32〇) 時’可先喊原先的佈局編排。並根_先的佈局 讀取的電路資訊槽案對照後，產生新的佈局編排。在新的佈局編 排中’新增的件可被用制的記號標示。 本發明係另揭露-種之·佈局輔助系統，請參照『第5圆』。 此系統包括檔案讀取模組10、介面產生模組20、指令接收模組 12 201122869 30、判斷模組40、參數產生模組5〇。 _讀取模組10，用以讀取電路資訊齡，該電路資訊播幸 包括複數個元件、聽該些元件的概麵件她和料元件的 連接關係。介面產生模組2G，用蝴_路纽檔案產生圖形 使用者介面。指令接收模組30，用以接收由該使用者輸入之預估 佈局編排。判斷模組40，肋判岐否已完成該預估佈局編排。 參數產生 50，用財若已完成該難佈局編排，則根據該預 馨估佈局編排’產生對應該些元件的一佈局相關參數。 於本發明之—實施例或是多個實施例中，其中在職讀取模 組10中，電路資訊檔案為一電路圖。 於本發明之-實補或是多個實_巾，其巾在檔案讀取模 組中10，其中該電路資訊檔案為一電路連線列表。 於本發明之—實施例或是多個實施例中，其中在介面產生模 組20中，包括下述步驟：挑選出複數個可佈局元件，並根據該複 數個可佈局元件的該f路資訊齡，產生_圖形介面。 於本發明之一實施例或是多個實施例中，其中在指令接收模 、、且30中’包括接收該使用者由鍵盤輸入之指令。 於本發明之一實施例或是多個實施例中，其中在指令接收模 組30中’包括接收該使用者由滑鼠輸入之指令。 於本發明之一實施例或是多個實施例中，其中在指令接收模 、、且30中，包括接收該使用者選取、移動、轉動、合併、或分離圖 示的元件以達成預估佈局編排。 13 201122869 於本發明之一實施例或是多個實施例中，其中在指令接收模 組30中，只少兩個元件之間的至少一距離可由使用者修改。 於本發明之一實施例或是多個實施例中，其中在指令接收模 組3〇中，包括接收該使用者在至少一元件加上至少一啞元件的步 驟。 於本發明之一實施例或是多個實施例中，其中在判斷模組4〇 中，為接受該使用者之編排完成訊號。這使用者之編排完成訊號 可以是該使用者點選特定的按鈕或輸入文字指令。 根據本發明之一實施例，其中在參數產生模組5〇中，該佈局 相關參數包括擴散層長度效應參數。 根據本發明之一實施例，其中在參數產生模組5〇中該佈局 相關參數包括井區鄰近效應參數。 根據本發明之一實施例，其中在參數產生模組5〇中，該佈局 相關參數包括連接線的寄生電容以及寄生電阻。 根據本發明之一實施例，其中更包括檔案修改模組6〇，用以 將參數產生模组5〇產生之該佈局相關參數放入電路資訊檔案中之 合適位置。 根據本發明之一實施例’其中更包括檔案修改模組6〇，用以 將參數產生模組50產生之該佈局相關參數放入電路資訊檔案中之 合適位置，並儲存為一新電路資訊檔案。 根據本發明之晶圓佈局辅助方法、系統以及電腦可讀取之記 憶媒體’可在佈局之前使用一個預估佈局編排來預估佈局後的佈 201122869 局相關的參數，從而在電路模擬時考慮這些佈局_的參數，以 減少佈局前電频擬的結果與佈局後祕模_結果的差異。 雖然本發明以前述之實施例揭露如上，然其並咖以限定本 發明。在不脫離本發明之精神和範圍内，所為之更動與潤飾，均 屬本發明之專利保護朗^關於本發明所界定之保護範圍請參考 所附之申請專利範圍。 【圖式簡單說明】 第1圖係為本發明之第一實施例之流程圖。 第2A圖係為本發明之一示意用之電路連接表。 第2B圖係為本發明之一示意用的電路圖。 第2C圖係為本發明之第2B圖產生的圖形介面。 第2D圖係為本發明之一圖形介面輸入的佈局編排。 第2E圖係為本發明之一寫入佈局相關參數後的電路元件列 表。 第3圖係為本發明之第二實施例之流程圖。 第4圖係為本發明之第三實施例之流程圖。 第5圖係為本發明之一系統方塊圖。 【主要元件符號說明】 10....................檔案讀取模組 20....................介面產生模組 30....................指令接收模組 40 判斷模組 201122869 50....................參數產生模組 60....................檔案修改模組Transistor ’ M〇SFET _ M〇s transistor), the parameters that the user needs to define are the type of semiconductor, the Gate degree, the width, and the Finger number. As the technology of semiconductors changes with each passing day, the process of integrated circuits continues to evolve. During the evolution from the deep SUb micronmeter process to today's nanometer process, many non-ideal effects have accompanied the shrinking of component sizes. The towel has many non-ideal effects related to the layout of the components and the relative position. Here, _ with the length of the ship (LengthGfdiffijsiGn L〇D) 201122869 effect parameters into the train. The layer length effect is known as the Sq 〇W-Trench-Is〇lati〇nStressEffect, which is the characteristic of the M〇s transistor and its gate to the edge of the diffusion layer (Edge 〇 The length of f the Diffiisi〇n is related. Here we usually need layout-related parameters from sb to improve the accuracy of the circuit simulation, from the distance between SB and the gate of the transistor to the edge of the two regions. Since we (4) share a diffusion layer in the component package, the relative position and layout method of the transistor may greatly change these parameters. The layout and relative position of the component will be in the layout P after the circuit simulation. The segment will be determined. In the circuit display phase, the layout-related parameters will not be known, and the influence on the circuit will not be known. [Invention] In view of the above, the present invention proposes And the system. This method is used by the (4) road designer to design the circuit, and the parameters are closed. The wafer support method includes: (A) reading - f road information job, the circuit information broadcast package pure oil element , the elements of the components of the dragon and the multiple connections _; (B) according to the job: # 难难 - _ _ interface interface 'for the user to estimate the layout layout (Qing ^ (10) 咖 柳 伽(C) receiving at least one estimated layout arranged by the user; (9) determining whether the estimated layout has been completed '· and (E) if the estimated layout has been completed, the following steps are performed: according to the component type, The component parameters and the difficult-area rows are generated, and the layout-related parameters are generated. According to the above, the wafer layout assisting method according to the present invention can be used before the layout 201122869 2 - _ _ _ _ Layout Layout Layout Layout Layout-related parameters , : In the circuit mode (4) consider these layout phase _ parameters to reduce the difference between the results of the circuit simulation before the layout and the results of the circuit simulation after the layout. Second, the description of the hair _ 容 容 and the following description of the implementation The spirit and principle of the present invention are explained and explained, and the scope of the patent application of the present invention is further explained. [Embodiment] The detailed features and advantages of the present invention are described in detail below in the embodiments. The content is sufficient for any "skilled artist to understand the technical axis of this (4) and implement it" and according to the contents disclosed in this specification, the scope of the patent and the schema, anyone familiar with the relevant art can understand the hair _ The purpose and advantages of the following embodiments are as follows: An electronic device having a computing function. The social programming program is not limited to any programming language, and the computer is not limited to any platform. The computer-readable recording medium proposed by the present invention is a hard disk, a compact disc, a disc or a memory. ", the other touches the money. The computer code in the storage media of this store is the same as the above-mentioned cylinder program. The month ... the first circle" is a flowchart of the first embodiment of the present invention. This is a sub-step j. Read a circuit information file (8) (9), the circuit information Tan file includes a plurality of components, _ components, several tree parameters and component connections. 201122869 = Generate - _ user interface Jia Shuaiyi (10) Lion Receiving at least one estimated layout arrangement input by the user, judging (4) into the estimated layout arrangement ((4); and, the bureau layout, performing the following steps. The secret is _ 丨神. According to the estimated layout, the generation Layout related parameters (S150). In step S11, the 'circuit information file is a schematic diagram (Schematic) or a circuit connection table (Ne (four). The circuit_ is a connection table including a plurality of navigation parts, a plurality of component parameters corresponding to 7L pieces and A plurality of connections _. The above components are metal oxide semiconductor field effect transistors, double carrier junction transistors, etc. (4) plus Transistor '_, resistors, capacitors, inductors, diodes, ridges, electric lions, current Source, shouting source, grounding, etc. Each component corresponds to at least the side component parameters. Taking oxidized metal semiconductors as an example, these component parameters are _ length, width, index, etc. Please refer to Figure 2A for one. Show Use the circuit connection table. This circuit is connected to the internal and external parameters of the table. For example, the component parameters used in the circuit design ±f _ 6 (Short-channel IGFET Model) circuit model are taken as an example. This circuit is made of -P type. The oxidized metal semiconductor is composed of an N-type oxidized metal semiconductor. The circuit connection table includes the component name, the component parameters, and the connection relationship between the components. FIG. 2B is a schematic circuit diagram for illustrating the circuit. The circuit includes a current source. a resistor R1 'two N-type oxidized metal semiconductors, _2, nm3 and a P-type oxidized metal semiconductor PM1 and a ground. In step S120, 'the graphical interface is based on component parameters (such as length or width), 201122869 The geometry of the relatively sized components can be displayed in the shape interface. In addition, in the graphical interface, different colors can be marked for different attributes. Users can quickly distinguish different attributes according to different colors. The user's face includes instructions for completing the box, storing the layout, or reading the layout graphic, etc. - Embodiments of the present invention This utility will first classify all components into layout elements -- and non-layout components (n〇nphysicai , vlce ). Layout components can be formed on the wafer during half-material processing, such as oxymetals, Double-carrier junction transistor crystal core juncti〇n Transi_, BJT) resistor, electric valley, inductor, diode (diGde). Non-layout components are voltage source, current source, signal source, ground, ideal resistor, ideal capacitor, ideal inductor, ideal electronic component, parasitic electronic tree. Next, the jade program displays only the configurable components on the graphical interface. "2C" is a graphic interface generated according to "2B". In the circular interface, the fabric elements are -R1, three N-type oxidized metal semiconductors, NM2, NM3, and a p-type oxidized metal semiconductor pM1. On this circle, the P-type oxidized metal semiconductor PM1 shows the well area of the thief. In the embodiment of the present invention, when the circuit information file has a multi-level structure (Hierarchy), the _ can select whether or not the estimated layout of all the wrong layer structures is arranged or a specific time and line (Sub_circui sub-layer circuit block) (Sub bl〇c_ Estimated layout orchestration. It is also acceptable here to accept that the layout has been completed as part of the new estimated layout. 201122869 In step S130, at least one estimated layout is input by the user. The estimated layout of the user input includes the position of the component and the placement angle of the component. In an embodiment of the present invention, the estimated layout may include adding a dummy device around the component, or two The above components are combined using interleaving, or two or more components are combined in a side-by-side manner, or the well of the component is enlarged. The user can input the estimated layout by using a mouse or a keyboard or a touch screen input device or the like. In step S130, 'otherly selectable layout elements can be received by the user. a plurality of combination relationships. That is, the user can select, move, rotate, merge, or separate the illustrated components to achieve an estimated layout. In step S130, in another embodiment of the present invention, at least one The configurable component can be removed from the estimated layout. In another embodiment of the present invention, one or a parameter user interface can be generated at the same time. The user interface can display information of the component. The interface can provide a convenient input interface for the user to achieve the estimated layout. In another embodiment of the present invention, the user interface can have a text input space, a pull-down window, or a click button. In step S130, in another embodiment of the present invention, when the user selects a certain component, the related component is displayed on the graphic maker interface or the user interface. In step S130, in the present embodiment, In another embodiment of the invention, when the user selects a component, it will be marked on the circuit information file (HighUght). 201122869 "Monthly reference to the 2D figure It is arranged according to the estimated layout input by the graphic interface. In this embodiment, the direction of the resistor R1 is rotated by ninety degrees, and the N-type oxidized metal semiconductor ΝΝΠ and NM2 are combined in a staggered manner. In the connection relationship, the well region of the P-type oxidized metal semiconductor PM1 is enlarged on both sides of the N-wei metal semiconductor surface 3. In step S130, another embodiment of the present invention is implemented. In the example, the user can specify the connection between the special endpoints, and calculate the layout-related parameters related to the connection on the connection line when calculating the layout-related parameters. Then, step S140 is performed. After completing the estimated layout, the circuit designer will confirm the estimated layout programming completion instruction according to the user interface. After receiving the estimated layout layout completion instruction, it is judged that the estimated layout is completed. If the estimated layout is completed, the corresponding layout related parameters can be generated according to the estimated layout. The layout parameters include the diffusion layer length effect parameter, the well neighboring effect parameter section 1BSM4 (Lai), and the method of generating the layer length effect parameter, which can be referred to "BSIM4.4.0 Manual Copyright © 2004 UC Berkeley", "Chapter 13: Stress-Dependent Model. The layout-related parameters referred to herein generally refer to the relative distances, overlapping areas, or aspect ratio parameters of many different layers in a semiconductor process. In an embodiment or embodiments of the invention Calculating the layout-related parameters may be generated according to the component type, the component parameters, and the estimated layout. If the user specifies the connection between the specific endpoints in step S130, the parasitic capacitance and parasitic resistance generated via the connection lines may be The calculation of the layout parameter can be generated in a manner or in a plurality of embodiments by measuring the distance of a particular edge. In the present invention, an embodiment or a plurality of embodiments, The calculation of the layout-related parameters is aided by means of a look-up table (L〇〇k-Uptable) or a formula. In the present invention - real _ or multiple implementations The calculation handle _ number can be generated according to the combination of the component _, the elemental number and the tree. In the present invention - the embodiment or the hood, the calculation of the shank related number can be based on the component _, the component parameter and the disease tree dragon This utility program can provide parameters for the layout side of the user. The user can input the circuit information file and perform circuit simulation. In the embodiment of the present invention or in various embodiments, the rainbow program The layout-related parameters can be subordinated to the circuit resources, and the new back-end information file can be bribed for circuit simulation. In the embodiment of the present invention or the shirt embodiment, the component position in the estimated layout is This component can be used to provide further layout procedures. Multi',, and 2E diagrams are the results of updating the layout-related parameters into the circuit information file "2A". ~, Fig. 3' is a flow chart of the second embodiment of the present invention. The actual steps include the following steps: reading a circuit information archive (7), the circuit information file includes a plurality of το pieces, the pieces Multiple The component parameters and the connection relationship of the components; according to the circuit information _ generated - _ Lang interface (s22G); received by the use of 201122869 input at least - estimated layout orchestration (S23 〇); determine whether to complete the estimated layout _ )··If the estimated layout is completed, perform the following steps: Generate layout related parameters according to the estimated layout arrangement (S250); use the layout related parameters to perform circuit simulation (6) (10) Continue to estimate the layout layout (7), if it is judged As a result, when the estimation layout is continued, the process returns to the step (S23〇), and the estimated layout of the input by the user is re-received. The reference to "Fig. 4" is the third embodiment of the present invention. flow chart. This embodiment includes the following steps: reading a circuit information file _), the circuit information broadcast package includes a plurality of components, a plurality of component parameters of the components, and a connection relationship of the components; generating a graphic use according to the circuit information job Receiver: Receive from 1 to > Estimated layout (S330); Determine whether layout has been completed (8) 4〇) '· If the layout has been completed, perform the following steps to estimate the layout, and generate the f phase ΜParameter (S35G); gamma layout paste parameter 胄 胄 ( (s36〇) 丨 judge whether it is necessary to change the circuit information slot case (S37〇), if the judgment result is to change the circuit information job time 'do appropriate for the circuit information file Modification (S380), and return to step (S310) 'Remaining updated ## broadcast case. In this example, return to step (_). When the step (S32〇) is continued, the original layout can be called first. Parallel _ first layout After reading the circuit information slot case, a new layout is generated. In the new layout, the new items can be marked with the symbols used. The present invention is also disclosed in the "5th Circle". The system includes a file reading module 10, an interface generating module 20, an instruction receiving module 12 201122869 30, a determining module 40, and a parameter generating module 5〇. The reading module 10 is configured to read the age of the circuit information. The circuit information broadcasts a plurality of components, and listens to the connection between the components of the components and the material components. The interface generation module 2G generates a graphical user interface using the Butterfly_Lun file. The command receiving module 30 is configured to receive an estimated layout arranged by the user. The judging module 40 determines whether the estimated layout has been completed. The parameter generation 50, if the difficult layout is completed, the layout-related parameters corresponding to the components are generated according to the pre-optimization layout. In the embodiment or embodiment of the present invention, wherein the in-service read module 10, the circuit information file is a circuit diagram. In the present invention, the actual complement or the plurality of real wipes are in the file reading module 10, wherein the circuit information file is a circuit connection list. In the embodiment or the embodiment of the present invention, wherein the interface generating module 20 includes the following steps: selecting a plurality of configurable components, and according to the f-channel information of the plurality of configurable components Age, resulting in a graphical interface. In one or more embodiments of the invention, wherein the instruction receiving module, and 30' comprises receiving an instruction entered by the user by the keyboard. In one or more embodiments of the invention, wherein in the command receiving module 30 'includes receiving an instruction entered by the user by the mouse. In an embodiment or embodiments of the present invention, wherein the instruction receiving module, and 30, includes receiving, selecting, moving, rotating, merging, or separating the components of the user to achieve an estimated layout. Orchestration. 13 201122869 In one or more embodiments of the invention, wherein in the command receiving module 30, at least one distance between only two of the elements is modifiable by a user. In an embodiment or embodiments of the present invention, wherein the command receiving module 3 includes receiving a step of the user adding at least one dummy component to at least one component. In an embodiment or a plurality of embodiments of the present invention, in the determining module 4, the completion signal is accepted for accepting the user. The user's programming completion signal may be that the user clicks on a particular button or enters a text command. According to an embodiment of the invention, wherein in the parameter generation module 5, the layout related parameter comprises a diffusion layer length effect parameter. According to an embodiment of the invention, wherein the layout related parameters in the parameter generation module 5A include well neighborhood proximity effect parameters. According to an embodiment of the invention, wherein in the parameter generation module 5, the layout related parameters include parasitic capacitance of the connection line and parasitic resistance. According to an embodiment of the present invention, the file modification module 6 is further included to place the layout related parameter generated by the parameter generation module 5 into a suitable position in the circuit information file. According to an embodiment of the present invention, the file modification module 6 is further included, and the layout-related parameters generated by the parameter generation module 50 are placed in a suitable position in the circuit information file, and stored as a new circuit information file. . The wafer layout assisting method, system and computer readable memory medium according to the present invention can use an estimated layout arrangement before the layout to estimate the layout-related parameters of the layout 201122869, thereby considering these in the circuit simulation. Layout_parameters to reduce the difference between the layout of the pre-layout and the layout of the secret _ results. Although the present invention has been disclosed above in the foregoing embodiments, it is intended to limit the invention. All of the modifications and refinements of the present invention are within the spirit and scope of the present invention. The scope of protection defined by the present invention is set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a first embodiment of the present invention. Fig. 2A is a circuit connection table schematically used in one of the inventions. Fig. 2B is a circuit diagram for illustrating one of the inventions. Figure 2C is a graphical interface produced in Figure 2B of the present invention. The 2D drawing is a layout arrangement of one of the graphic interface inputs of the present invention. Fig. 2E is a circuit element list after writing layout-related parameters in one of the inventions. Figure 3 is a flow chart of a second embodiment of the present invention. Figure 4 is a flow chart of a third embodiment of the present invention. Figure 5 is a block diagram of one of the systems of the present invention. [Main component symbol description] 10....................File reading module 20................. Interface generation module 30.................... command receiving module 40 judgment module 201122869 50............ ........Parameter generation module 60....................File modification module
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