201121187 六、發明說明： 【發明所屬之技術頜域】 [0001] —種後級穩歷迴路的監控電路，特別指一種控制與保飞 的電路，且應用於控制電源供應器中的後級穩厘迴路 【先前技術】 [0002] ❹ 電源供應器具有不同電壓位準的多個輪出為習知的技術 ，而常見的電源供應器配置方式是將變壓器二次側區八 為至少一主輸出迴路以及連接於主輸出迴路的一後級穩 壓迴路（post regulation)。其中該主輪出超路係在 變壓器二次側透過繞組感應的方式先形成佔輸出功率比 例較高的主輸出電力’該後級鞔壓迴路苒由該主輪出電 力降歷形成電壓與功率較低的附屬感出f力》以供應— 般桌上型電腦的電源供應器為作丨，功奉與電流佔整體輸 出比例較大的為主輸出電力12V、5V ’ φ此使用兩繞組分 別供應主輸出電力12V、5V，再過後級穩壓迴路（ post regulation)產生3. Q [0003] 基於上述的習知技術，具備後級穩壓的習知電路可見於 圖1，其中該電源供應器具有一變壓器，該變壓器一次侧 10通過的電流受控於一脈寬調變電路（PWM control-1 e r )以及一組開關’而變麽器二次側具有多個主輸出迴 路11、12分別透過相異的繞組產生感應電力，其中該電 力經過複數開關（Q1與Q2、Q3與Q4)做同步整流，並經 過電感、電容穩定電力波形後形成兩個主輸出電力（12V 及5V)。再者，一組開關元件131、132、電感133、電 容與電阻等元件構成一組後級穩壓迴路13而連接於該主 098142000 表單編號A0101 0982072079-0 201121187 輸出迴路12，藉由該開關元件131、132的運作而調壓構 成3. 3V的一附屬輪出電力。其中該開關元件131、132是 透過一後級控制電路（圖中未示）控制，並且該決定該 開關元件131、132導通週期的方式是將流經該電感133 的電流積分所得之電壓，經由放大器放大為驅動訊號來 控制該些開關元件131、132的導通週期。 [0004] [0005] 由於現今後級穩壓迴路的控制機制係監測該後級穩壓迴 路中的電感電流，並將電感電流積分得到相應的電壓藉 以調變該組開關元件的導通週期β而後級穩壓迴路的保 護機制是設定一電流的上限值，當電感電流達到該上限 值時強迫減縮該脈寬調變電路的駆動脈波後緣’以避免 電流過尚。但疋附屬輸出電力端發生短路時，電流上升 的速度極快，即使已縮減了驅動脈波的後緣，該後級穩 壓迴路中的電感電流會瞬間驟升（大約#2~3個時脈内） 而產生如圖2中的過電流波形91 ’由於過電流波形9ι流量 過大，該後級穩壓迴路所連接的主輸出迴路會產生逆電 流波形92而_整流元件。因此不只後級穩壓迴路益法 運作，更連帶紐該後級漏迴路料接的讀出迴路 〇 【發明内容】 由於前段所述的習知技術中1後級穩壓迴路在短路時 不僅自身麟，並連帶產生逆電流損毀了所連接的主輸 出迴路。本案要達到的目的即在於提供_種控制與保^ 電路，除了控制該後級穩壓迴路的運作以外，更進， 抑制後級穩壓迴路本身過高的電流，該主輸出迴路不^ 098142000 表單編號Α0101 第4頁/共18頁 201121187 [0006] Ο201121187 VI. Description of the invention: [Technology of the invention] [0001] A monitoring circuit for a post-stage stable circuit, in particular a circuit for controlling and maintaining flying, and applied to the control of the power supply in the latter stage. PCT [Prior Art] [0002] 多个 Power supply has multiple turns of different voltage levels as a conventional technique, and a common power supply configuration is to set the secondary side of the transformer to at least one main output. The loop and a post regulation connected to the main output loop. The main wheel out-of-pass system is formed on the secondary side of the transformer through the winding induction method to form a main output power that accounts for a higher proportion of the output power. The post-stage rolling circuit generates voltage and power from the main wheel. The lower accessory sense of f force is based on the supply of the power supply of the desktop computer, and the main output power of the main output is 12V, 5V 'φ. The main output power is supplied at 12V, 5V, and then the post regulation is generated. 3. Q [0003] Based on the above-mentioned prior art, a conventional circuit having a post-stage voltage regulation can be seen in FIG. The device has a transformer, and the current passing through the primary side 10 of the transformer is controlled by a PWM control circuit (PWM control-1 er) and a set of switches, and the secondary side of the transformer has a plurality of main output circuits 11, 12 Inductive power is generated through different windings, wherein the power is synchronously rectified by a plurality of switches (Q1 and Q2, Q3 and Q4), and two main output powers (12V and 5V) are formed after the power waveform is stabilized by the inductor and the capacitor. Furthermore, a set of switching elements 131, 132, an inductor 133, a capacitor and a resistor constitute a set of post-stage voltage stabilizing circuits 13 and are connected to the main 098142000 form number A0101 0982072079-0 201121187 output loop 12, by which the switching element The operation of 131, 132 and voltage regulation constitutes a subsidiary of 3. 3V. The switching elements 131 and 132 are controlled by a post-stage control circuit (not shown), and the way to determine the on-period of the switching elements 131 and 132 is to integrate the current flowing through the inductor 133. The amplifier is amplified to drive signals to control the on-period of the switching elements 131, 132. [0004] [0005] Since the control mechanism of the current stage voltage regulator loop monitors the inductor current in the post-stage voltage regulator loop, and integrates the inductor current to obtain a corresponding voltage to modulate the turn-on period β of the set of switching elements. The protection mechanism of the voltage regulator loop is to set an upper limit value of the current. When the inductor current reaches the upper limit value, it is forced to reduce the trailing edge of the radial wave of the pulse width modulation circuit to avoid current excess. However, when the auxiliary output power terminal is short-circuited, the current rises at a very high speed. Even if the trailing edge of the driving pulse wave is reduced, the inductor current in the subsequent voltage-stabilizing circuit will rise suddenly (about #2~3) In the pulse), the overcurrent waveform 91' in FIG. 2 is generated. Since the overcurrent waveform 9ι is excessively flowed, the main output loop connected to the subsequent regulator circuit generates a reverse current waveform 92 and a rectifying element. Therefore, not only the post-stage voltage regulator loop operation, but also the readout loop of the post-stage leakage loop material 〇 [Abstract] In the prior art described in the prior art, the post-stage voltage regulator loop is not only itself in the short circuit. Lin, and associated with the reverse current damage to the connected main output loop. The purpose of this case is to provide a control and protection circuit. In addition to controlling the operation of the post-stage voltage regulation loop, it is more advanced to suppress the excessive current of the post-stage voltage regulation loop itself. The main output loop is not ^ 098142000 Form No. 1010101 Page 4 of 18 201121187 [0006] Ο
GG
[0007][0007]
該後級龍迴料路㈣響而象續工作。 本案為—種後級穩壓迴路的監控電路，用於 源 供應器產生的附屬輪出雷士 ^ 电原 出電力，其中該電源供應器中具有 -變壓器’該變壓器具有至少一二次側線圈以及該二次 侧線圈所連接的主輪出迴路，職級顏轉連接該主 輸出、路並取得遠主輪出迴路的—主輸出電力，且㈣ 級穩壓迴路包含—組開關單元將該主輪出電力調變成一 附屬輸出電力’而—監控電路控制該開關單元的工作時 序該監控電路包括一脈波產生單元、一電力監測單元 以及-邏輯單元，該脈波產生單元齡—第—脈波至該 邏輯單元，㈣電力監測單元狀-異常位準，並自該 後級穩壓迴路取得1測電力與該異常位準作比較，^ 得輸出-狀態訊號以表示該偵測電力是否越過該異常位 準，該狀態t遠被送㈣邏輯單元。最後，該邏輯單元 依該狀態訊號決定是否依解第τ脈波的波形而輸出二 驅動脈波，或者停止輪出該驅動脈波 的工作時序。藉由上述電路的動作，具雜的二 級穩壓迴路的電感電流造成主輸出迴路產生逆電流之吁 抑制該開關單元的運作，因此即使該後級穩壓迴路已叫 路或相壞，該主輪出迴路也不會產生逆電流，達到後級 穩壓迴路具有獨立保護機制的有益效果。 【實施方式】 本案一種後級穩壓迴路的監控電路，係應用於一種具有 後級穩壓迴路的電源供應器。請參閱圖3，該電源供應。 的變壓器—次側1 〇將電力傳送至變壓器二次側的兩主T 098142000 表單編號A0101 第5頁/兴18頁 〇982〇?2〇79、〇 201121187 出k路11 12 ’並由该主輸出迴路η、12分別透過開關 單元111、121調變出12V與5V的主輪出電力，而一後級 穩壓迴路13則連接於其中一主輸出迴路12上，該後級穩 壓迴路13可取得該主輸出迴路12的”主輸出電力且該 後級穩壓迴路13利用兩開關元件ι31、132所構成的一組 開關單元將該主輸出電力調變成3. 3V的一附屬輸出電力 。除了該開關元件131、132以外，該後級穩壓迴路13還 可包括一電感133、一電容以及一電阻，其中圖3所示為 一概略之示意圖，該後級穩壓迴路13的細部具體電路當 然不限於圖中所示之態樣；再者該電感133、電容等元件 的功效為該技術領域具有一般知識者所熟知的習知技術 ’故不再贅述。 [0008] 請再同時參閱圖3與圖4，本案之特點在於該後級穩壓迴 路13受控於一監控電路2，該監控電路2自該附屬輸出電 力取得一回授訊號（3. 3VJB)，以及自該開關單元取得 一偵測電力214，該監控電路2藉由該回授訊號調整一驅 動脈波24的工作週期视duty cycle)，並且藉由該偵測 電力214而決定是否縮減該驅動脈波24的前緣而達到保護 的作用。該監控電路2詳述如下，該監控電路2包括一電 力監測單元21、一脈波產生單元22以及一邏輯單元23， 其中該脈波產生單元22利用一脈寬控制比較器222取得一 鑛齒波訊號223以及一脈寬位準訊號224，並比較兩者大 小而輪出一具有高、低準位的第一脈波225。而為了要具 備回授控制的功能，該脈波產生單元22更佳的實施結構 是在該脈寬控制比較器222之外更包括一回授校正放大器 098142000 表單編號A0101 第6頁/共18頁 0982072079-0 201121187 221，該回授校正放大器221取得一參考電壓)以 及自附屬輸出電力取得該回授訊號（3 3V_FB)，依據該 參考電壓與該回授訊號的電M差異而決定該脈寬位準訊 號224的位準。因此該回授訊號的大小改變脈寬位準訊號 224，更進一步的透過該脈寬位準訊號224與該鋸齒波訊 號223的大小變化而改變該第一脈波225。該電力監測單 元21設定一異常位準用於判斷該附屬輸出迴路13與該主 輸出迴路12之間的電力是否異常，以判斷執行保護機制 的時序。其中該電力監測單元21主要包含一直流電流源 211、一比較器212，其中該比較器212之一輸入端取得 一電位作為異常位準，而在圖4中的較佳態樣係令該比較 器21 2的一輸入端接地，以電壓(μ_作為異常位準。該直流 電流源211與該比較器212之間具有一線路連接該後級穩 壓迴路13而形成該偵測電力214，一併參閱圖3與圖4可見 ’該直流電流源211與該比較器212之閭的線路連接至兩 開關元件131、132之間’而擷取流經該開關單元的主輸 出電力，作為該偵測電力214，該偵測電力214的變化量 與該附屬輸出電力的變化量成比Θ關係。藉此該電力監 測單元21可監測流入該附屬輸出迴路13的電力，以盡快 檢知與避免產生逆電流。該直流電流源211係受一過電流 訊號（0CP)驅動而提供一緩衝電力，並在一電容216中 形成穩定的直流位準，進而提高該偵測電力214之直流位 準，因而增加該偵測電力214與該異常位準之間的差距而 避免誤動作。該比較器212則比較該異常位準以及該偵測 電力214，並得透過一反相器213而輸出一狀態訊號215 ，該狀態訊號215的低、高準位表示該偵測電力214是否 098142000 表單編號Α0101 0982072079-0 201121187 越過该異常位準。而該邏輯單元23取得該第一脈波225以 及該狀態訊號215，如圖4辛所示，該邏輯單元23可包括 一及閘（AND)接收該第一脈波225與該狀態訊號215， 並依該狀態訊號215決定是否依據該第一脈波225的波形 而輸出一驅動脈波24。更具體的說，該狀態訊號215與該 第_脈波2 2 5皆為高準位時才輸出該驅動脈波2 4，若該電 力監測單元21判定該偵測電力214出現異常時則停止輸出 該狀態訊號215，使得邏輯單元23截止該驅動脈波24而限 制該開關單元的工作時序。當該開關單元如圖3所示具有 兩開關元件131、132時，則該邏輯單元23可包含一分支 線路利用反相器產生一反向驅動脈波25，使該開關元件 131、132受該驅動脈波24、反向驅動脈波25驅動而交錯 導通。 ： : [0009] 請參閲圖3、圖4的電路’再一併參閱圖5的節點波形，在 圖5中可見，當3. 3V的附屬輸出電力正常哼，該狀態訊號 215 (OC一Lock)波艰是常態的位於高準位，使該第一脈 波225完全不被邏輯事元23限縮的形成該驅動脈波24與反 相驅動脈波25。而在正常狀態下，通過該開關元件丨31、 132的電力（VDS)進入該電力監測單元21，並加上該直 流電流源211提供的直流位準而透過該電容216形成圖5中 所看到的债測電力214 (Vset)波形。如圖5所示，該债 測電力214在正常狀態下應為正（高於該異常位準），由 於該偵測電力214是由兩開關元件131、132之間取得， 因此會隨著開關元件131、132的導通週期而波動。 [0010] 當該附屬輸出電力（3. 3V)短路時，每個充電週期中電 098142000 表單編號A0101 第8頁/共18頁 0982072079-0 201121187The latter-level dragon returning road (four) sounded like a continuous work. The present invention is a monitoring circuit of a post-stage voltage regulation loop, which is used for the auxiliary wheel of the source supply to output the NVC electric power, wherein the power supply has a transformer - the transformer has at least one secondary side coil And the main wheel outlet circuit connected to the secondary side coil, the grade turn connection connects the main output, the road and obtains the main output power of the far main wheel output loop, and the (four) stage voltage regulator loop includes the group switch unit to the main The turn-off power is converted into an auxiliary output power' and the monitoring circuit controls the operation timing of the switch unit. The monitoring circuit includes a pulse wave generating unit, a power monitoring unit, and a logic unit, and the pulse wave generating unit age-first pulse Wave to the logic unit, (4) power monitoring unit-abnormal level, and obtaining 1 measured power from the rear-stage voltage stabilization loop to compare with the abnormal level, and obtaining an output-state signal to indicate whether the detected power is crossed The abnormal level, the state t is sent to the (four) logic unit. Finally, the logic unit determines whether to output the two driving pulse waves according to the waveform of the τ pulse wave according to the state signal, or stop the working timing of the driving pulse wave. By the action of the above circuit, the inductor current of the mixed secondary voltage stabilizing loop causes the reverse current of the main output loop to suppress the operation of the switching unit, so even if the post-stage voltage stabilizing circuit is called or damaged, The main wheel output circuit will not generate reverse current, which has the beneficial effect of the independent protection mechanism of the latter voltage regulation loop. [Embodiment] A monitoring circuit of a post-stage voltage stabilization loop is applied to a power supply with a post-stage voltage stabilization loop. Please refer to Figure 3 for the power supply. Transformer - the secondary side 1 〇 transmits power to the secondary side of the transformer. The two main T 098142000 Form No. A0101 Page 5 / Hing 18 pages 〇 982 〇 2〇 79, 〇 201121187 Out k Road 11 12 ' and by the Lord The output circuits η, 12 are modulated by the switch units 111, 121 to output the main wheel output power of 12V and 5V, respectively, and a post-stage voltage stabilization circuit 13 is connected to one of the main output circuits 12, and the post-stage voltage stabilization circuit 13 The main output power of the main output circuit 12 is obtained by the set of switching units of the two switching elements ι 31 and 132. In addition to the switching elements 131 and 132, the post-stage voltage stabilization circuit 13 may further include an inductor 133, a capacitor, and a resistor. FIG. 3 is a schematic diagram showing details of the post-stage voltage stabilization loop 13 The circuit is of course not limited to the one shown in the figure; in addition, the functions of the inductor 133, the capacitor and the like are well-known techniques well known to those skilled in the art, and therefore will not be described again. [0008] Please refer to it at the same time. Figure 3 and Figure 4, the characteristics of this case The monitoring circuit 2 is controlled by a monitoring circuit 2, and the monitoring circuit 2 obtains a feedback signal (3.3 VJB) from the auxiliary output power, and obtains a detection power 214 from the switching unit. The circuit 2 adjusts the duty cycle of the driving pulse wave 24 by the feedback signal, and determines whether to reduce the leading edge of the driving pulse wave 24 by the detecting power 214 to achieve the protection function. The circuit 2 is detailed as follows. The monitoring circuit 2 includes a power monitoring unit 21, a pulse wave generating unit 22, and a logic unit 23, wherein the pulse wave generating unit 22 uses a pulse width control comparator 222 to obtain a mine tooth signal. 223 and a pulse width reference signal 224, and compare the size of the two to rotate a first pulse 225 having a high and a low level. The pulse wave generating unit 22 is better in order to have the function of feedback control. The implementation structure is further including a feedback correction amplifier 098142000 in addition to the pulse width control comparator 222. Form No. A0101, page 6 / 18 pages 0982072079-0 201121187 221, the feedback correction amplifier 221 obtains a reference voltage)And obtaining the feedback signal (3 3V_FB) from the auxiliary output power, and determining the level of the pulse width level signal 224 according to the difference between the reference voltage and the electrical M of the feedback signal. Therefore, the size of the feedback signal changes. The wide-level signal 224 further changes the first pulse wave 225 by changing the size of the pulse width level signal 224 and the sawtooth wave signal 223. The power monitoring unit 21 sets an abnormal level for determining the auxiliary output. Whether the power between the loop 13 and the main output loop 12 is abnormal is used to judge the timing at which the protection mechanism is executed. The power monitoring unit 21 mainly includes a DC current source 211 and a comparator 212. One of the comparators 212 takes a potential as an abnormal level, and the preferred embodiment in FIG. 4 makes the comparison. An input end of the device 21 2 is grounded, and the voltage (μ_ is used as an abnormal level. The DC current source 211 and the comparator 212 have a line connecting the rear-stage voltage stabilization circuit 13 to form the detected power 214. Referring to FIG. 3 and FIG. 4 together, it can be seen that 'the DC current source 211 and the line between the comparators 212 are connected between the two switching elements 131 and 132' and the main output power flowing through the switching unit is taken as the Detecting the power 214, the amount of change of the detected power 214 is proportional to the amount of change of the auxiliary output power, whereby the power monitoring unit 21 can monitor the power flowing into the auxiliary output circuit 13 for detection and avoidance as soon as possible. A reverse current is generated. The DC current source 211 is driven by an overcurrent signal (0CP) to provide a buffered power and form a stable DC level in a capacitor 216, thereby increasing the DC level of the detected power 214. Thus increase The difference between the detection power 214 and the abnormal level avoids malfunction. The comparator 212 compares the abnormal level with the detected power 214, and outputs a status signal 215 through an inverter 213. The low and high levels of the status signal 215 indicate whether the detected power 214 is 098142000. The form number Α0101 0982072079-0 201121187 crosses the abnormal level. The logic unit 23 obtains the first pulse 225 and the status signal 215, such as As shown in FIG. 4, the logic unit 23 can include an AND gate to receive the first pulse 225 and the status signal 215, and determine whether to output according to the waveform of the first pulse 225 according to the status signal 215. a driving pulse wave 24. More specifically, the driving pulse wave 24 is output when the state signal 215 and the first pulse wave 2 25 are both at a high level, and if the power monitoring unit 21 determines the detected power When an abnormality occurs in 214, the output of the status signal 215 is stopped, so that the logic unit 23 cuts off the driving pulse wave 24 to limit the operation timing of the switching unit. When the switching unit has two switching elements 131, 132 as shown in FIG. The logic The unit 23 can include a branch line to generate a reverse drive pulse 25 by the inverter, and the switching elements 131, 132 are driven by the drive pulse 24 and the reverse drive pulse 25 to be turned on and turned on. : : [0009] Please refer to the circuit of FIG. 3 and FIG. 4 again. Referring again to the node waveform of FIG. 5, it can be seen in FIG. 5 that when the auxiliary output power of 3.3 V is normal, the status signal 215 (OC-Lock) is difficult. The normal state is at a high level, so that the first pulse wave 225 is not confined by the logic element 23 at all to form the driving pulse wave 24 and the inversion driving pulse wave 25. In the normal state, the power (VDS) passing through the switching elements 丨31, 132 enters the power monitoring unit 21, and the DC level provided by the DC current source 211 is added to form a capacitor 216 to form a view as seen in FIG. The incoming power measurement 214 (Vset) waveform. As shown in FIG. 5, the debt test power 214 should be positive (above the abnormal level) in the normal state, and since the detected power 214 is obtained between the two switching elements 131, 132, it will follow the switch. The conduction periods of the elements 131, 132 fluctuate. [0010] When the auxiliary output power (3.3 V) is short-circuited, each charging cycle is powered 098142000 Form No. A0101 Page 8 of 18 0982072079-0 201121187
感電流ULp〇st)非常快速的上升，但由於回授訊號的電 壓過低，該脈波產生單元22反而提高第一脈波225的工作 週期’因此無法快速的排除故障。當該電感電流（IThe sense current ULp〇st) rises very rapidly, but since the voltage of the feedback signal is too low, the pulse wave generating unit 22 instead increases the duty cycle of the first pulse wave 225', so that the fault cannot be quickly eliminated. When the inductor current (I
Lpost )驟升到一定的電流量時，該偵測電力214會低於該異常 位準（0V)，代表該後級穩壓迴路13端已出現異常。該 偵測電力214低於該異常位準時，該比較器212的輸出轉 態，透過該反向器213使得該狀態訊號215變為低準位， Ο 因此該邏輯單元23限縮該驅動脈波24的前緣，直到該偵 測電力214高於異常位準為止。在圓5中可見，該電感電 流（ILP〇st)驟升時，該偵測電力214 (Vset)隨著降低 ，甚至低於異常位準（波形下降到原點以下），此時狀 態訊號215 (〇c_Lock)轉態而限缩該驅動脈波24的前緣 ，直到偵測電力214 (Vset)回復正常（波形回復到原點 以上）^短路的狀況沒排除之前，電感電流（1When Lpost is suddenly increased to a certain amount of current, the detected power 214 will be lower than the abnormal level (0V), indicating that an abnormality has occurred at the end of the post-stage voltage regulator circuit 13. When the detected power 214 is lower than the abnormal level, the output of the comparator 212 is turned, and the state signal 215 is changed to a low level through the inverter 213, so the logic unit 23 limits the driving pulse. The leading edge of 24 until the detected power 214 is above the abnormal level. It can be seen in the circle 5 that when the inductor current (ILP〇st) suddenly rises, the detected power 214 (Vset) decreases, even lower than the abnormal level (the waveform falls below the origin), and the status signal 215 (〇c_Lock) transitions and limits the leading edge of the drive pulse 24 until the detected power 214 (Vset) returns to normal (the waveform returns to the original point) ^ The condition of the short circuit is not eliminated before the inductor current (1
Lposty ^ ❹ [0011] 法恢復正常，但該監控電路2可透過該大幅的減縮該驅動 脈波24的前緣而使得逆電流的慘況得到控制，即使後級 穩壓迴路13無法正常工作，亦不會對所連接的主輪出迴 路12造成任何損壞，達到獨立保護的積極功效。 雖然本發明已以較佳實施例揭露如上，然:其並非用以限 定本發明’任何熟習此技藝纟，在不脫離本發明之精神 和範圍内而所作之些許更動與潤飾’皆應涵蓋於本發明 中’因此本發明之保護範圍當視後附之申請專利範圍所 界定者為準。 [0012] 098142000 綜上所述，本發明較習知之電路增進上述功效，應已充 分符合新酿及進步性之法定賴補要件，t依法提 表單編號A_ 苐9頁/共18頁 0982072079-0 201121187 出申請，懇請貴局核准本件發明專利申請案，以勵創作 ，至感德便。 【圖式簡單說明】 [0013] 圖1為習知具有後級穩壓迴路的電源供應器電路示意圖。 [0014] 圖2為圖1的習知電路各節點波形圖。 [0015] 圖3為本案之電路示意圖。 [0016] 圖4為該監控電路之架構示意圖。 [0017] 圖5為本案電路之各節點波形圖。 【主要元件符號說明】 [0018] 10 · ·—— ••變壓器一次側 [0019] 11 ' 12 · · •...主輸出迴路 [0020] 111 、 121 · .....開關元件 [0021] 13 · · · · ••後級穩壓迴路 [0022] 131 、 132 · .....開關元件 [0023] 133 · · · · ..電感 [0024] 2..... •監控電路 [0025] 21 · · · · ••電力監測單元 [0026] 211 · · · · ••直流電流源 [0027] 212 · · · · ••比較器 [0028] 213 · · · · ••反向器 098142000 表單編號A0101 第10頁/共18頁 0982072079-0 201121187 [0029] 214 · .....偵測電力 [0030] 215 · .....狀態訊號 [0031] 216 · .....電容 [0032] 22 · .....脈波產生單元 [0033] 221 · .....回授校正放大器 [0034] 222 · .....脈寬控制比較器 [0035] 223 · ❹ [0036] 224 · .....脈寬位準訊號 [0037] 225 · [0038] 23 · .....邏輯單元 [0039] 24 · .....驅動脈波 [0040] 25 · .....反向驅動脈波 [0041] 91 · .....過電流波形 〇 [0042] 92 · .....逆電流波形 098142000 表單編號A0101 第11頁/共18頁 0982072079-0Lposty ^ ❹ [0011] The method returns to normal, but the monitoring circuit 2 can control the magnitude of the reverse current through the large reduction of the leading edge of the driving pulse wave 24, even if the post-stage voltage stabilization circuit 13 cannot work normally. It will not cause any damage to the connected main wheel out circuit 12, and achieve the positive effect of independent protection. Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and it is intended to be limited to the details of the invention. In the present invention, the scope of the invention is therefore defined by the scope of the appended claims. [8141] In summary, the conventional circuit of the present invention enhances the above-mentioned functions, and should fully comply with the statutory requirements for new brewing and progressiveness, and submit the form number A_ 苐9 pages/total 18 pages 0982072079-0 according to law. 201121187 Applicant, I ask you to approve the application for this invention patent, to encourage creation, to the sense of virtue. BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIG. 1 is a schematic diagram of a conventional power supply circuit having a post-stage voltage stabilization loop. 2 is a waveform diagram of each node of the conventional circuit of FIG. 1. [0015] FIG. 3 is a schematic circuit diagram of the present invention. 4 is a schematic structural diagram of the monitoring circuit. [0017] FIG. 5 is a waveform diagram of each node of the circuit of the present invention. [Main component symbol description] [0018] 10 · ·—— •• Transformer primary side [0019] 11 ' 12 · · •... main output circuit [0020] 111, 121 · ..... switching element [0021 ] 13 · · · · •• Rear-stage voltage regulator circuit [0022] 131 , 132 · ..... Switching element [0023] 133 · · · · .. Inductance [0024] 2..... • Supervisory circuit [0025] 21 · · · · • Power Monitoring Unit [0026] 211 · · · ·•• DC Current Source [0027] 212 · · · ·•• Comparator [0028] 213 · · · · •• Reverse器098142000 Form No. A0101 Page 10/Total 18 Page 0982072079-0 201121187 [0029] 214 · ..... Detecting Power [0030] 215 · ..... Status Signal [0031] 216 · .... Capacitor [0032] 22 · ..... Pulse wave generating unit [0033] 221 · ..... Feedback correction amplifier [0034] 222 · ..... Pulse width control comparator [0035] 223 · 224 [0036] 224 · ..... pulse width level signal [0037] 225 · [0038] 23 · ..... logic unit [0039] 24 · ..... drive pulse [0040] 25 · ..... Reverse drive pulse [0041] 91 · ..... Overcurrent wave Square [0042] 92 098 142 000 * ..... reverse current waveform form Page number 11 A0101 / 18 Total 0982072079-0