201120897 六、發明說明： 【發明所屬之技術領域】 本發明係有關於資料儲存系統與方法，特別應用於具 有拷貝回存（copyback)操作之記憶體。 ” 【先前技術】 除了盤式硬碟、光碟…等，現今已發展出其他資料： 存技術。以固態式硬碟(Solid State Disc，SSD)為例，龙： 利用NAND Plash(反及閘快閃記憶體)作為儲存單元，^ 代傳統之盤式硬碟。此外，攜帶式電子裝置，例如市^取 常見的mp3隨身聽…等，亦常使用反及閘快閃記憶體 存資料。 … 餘 反及閘快閃記憶體具有一拷貝回存(C〇PybaCk)操作也 可以稱為内部拷貝操作（Internal Copy )。第1圖以方塊圖 圖解一反及閘快閃記憶體之架構，並示意其中一種拷貝。 存操作。 ° 如圖所示，反及閘快閃記憶體100具有複數個區塊 (blocks ’ 編號為 block。、block!、···、blockn)、以及一緩衝 器102。區塊block〇…blockn提供物理空間儲存資料，各自 更可劃分為複數個頁（pages);例如，區塊bl〇ck〇包括複數 個頁卩汪河0,0)、卩3如(0，1卜_’區塊|31〇〇]^包括複數個頁 page(l，0)、page(l，l)…’區塊bl〇ckn包括複數個頁201120897 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a data storage system and method, particularly to a memory having a copy-back operation. [Prior Art] In addition to disk hard drives, CDs, etc., other materials have been developed today: Storage technology. Solid State Disc (SSD), for example, Dragon: Using NAND Plash (anti-gate fast) As a storage unit, it is a traditional disk-type hard disk. In addition, portable electronic devices, such as the city's common mp3 player, etc., often use anti-gate flash memory to store data. The reverse flash memory has a copy-back memory (C〇PybaCk) operation, which can also be called internal copy operation. Figure 1 is a block diagram illustrating the architecture of the gate flash memory. One of the copies is illustrated. Store operation. ° As shown, the inverse flash memory 100 has a plurality of blocks (blocks 'numbered block., block!, . . . , blockn), and a buffer 102. Block block〇...blockn provides physical space to store data, each of which can be divided into a plurality of pages; for example, block bl〇ck〇 includes a plurality of pages, Wang He 0, 0), 卩 3, such as (0) , 1 Bu_'block|31〇〇]^ includes a plurality of pages page(l,0), Page(l,l)...’ block bl〇ckn includes a plurality of pages
Page(n，0)、Page(n，l)···。於讀/寫操作中，主機端(h〇st)程序 (program)所使用的位址資訊稱為「邏輯位址」，需先經映 射表（mapping table)轉換為「物理位址」才能對應至反及閘 快問5己憶體100上的物理空間（上述區塊、或頁、或更小的 VIC09.0010/0608-A42140-TW/Final 4 201120897 儲存單位）冑衝II 1()2則是設計來供拷貝回存操作使用。 -邏輯位址之資料可能自反及間快閃記憶體綱的一 :理空間二移至另一物理空間’其一操作即拷貝回存操 作。拷貝回存操作有多種型式，例如，執行垃圾收集(g collection)釋玫儲存空間時’通常會大量運用到拷貝回存摔 作。垃圾收集通常以「區塊」作為空間釋放的單位。以釋 放第1圖區塊bi〇ckl為例，需先將區塊Page(n,0), Page(n,l)···. In the read/write operation, the address information used by the host (h〇st) program is called a "logical address", and needs to be converted into a "physical address" by a mapping table to correspond to To the opposite gate, ask about the physical space on the body 100 (the above block, or page, or smaller VIC09.0010/0608-A42140-TW/Final 4 201120897 storage unit) 胄冲 II 1()2 It is designed for use in copy-back operations. - The data of the logical address may be reflexive and the one of the flash memory class: the second space is moved to another physical space', and one operation is a copy-back operation. There are many types of copy-and-restore operations. For example, when performing garbage collection (g collection), the storage space is usually used in large quantities to copy and save. Garbage collection usually uses "blocks" as the unit of space release. Taking the block diagram of the first picture block bi〇ckl as an example, the block needs to be first
蝴貝至另一區塊，如區塊一，方 block,之健存空間釋放並將其標示為可用空間；其卜搬 移有效資料之技術即㈣回麵作的—㈣式。貝一 頁page(l，0)至另一頁為例，拷先 頁page(l，G)⑽存之資料送至緩衝 把 傳遞至頁pageh，！）；整個資料傳 〆-盗102 記憶體議内部，外界不得窺^過程限制於反及閉快閃 ^了目丨㈣之技術，拷心麵 =頁二搬移資料。此型式之拷貝回存操 頁的4域_該頁内部的緩衝器，再由 該頁的另一區域；其資料傳送過程同樣也是限制在反及閑 快閃記憶體内部。 &取利隹汉及閘 ，二操作之資料傳送過程限制於反及閘快閃 ,己憶體内和其間若發生拷貝錯誤也無法得知 拷貝錯誤會累積至無法校正的程度。 旯吾者 【發明内容】 又 及方法。 包括：一第一記憶體、 本發明提供一種資料儲存系統以 本發明所揭露之資料儲存系統， VIC09-0010/0608-A42140-TW/Final ς 201120897 計次模組、以及一校錯模組 、_ 控制器 第，己憶體具有-拷貝回存操作。控制 記憶體㈣計次模組以及校錯模組。計次、責將第〜 記憶體複數個邏輯位址之拷貝回存操作進行一二貴對第〜 且據以判斷上述邏輯位址是否滿足-校錯條件，操作， 負責接收自第-記憶體讀出的滿足校錯條件的、罐3錯模舨 資料’朗料校錯斜的邏輯健之^位址之 本發明所揭露之資料儲存方法應用於且錯。 操作的-第-記憶體上。此資料儲存方法包括回存 f體複數個邏輯位址之拷貝回存操作進行—計次摔記 =以判斷上述邏輯位.址是否滿足一校錯條件；以 記憶體讀出的滿足校錯條件的邏輯位址之資 滿足該校錯條件的邏輯位址之資料進行校錯，以 2 一記憶體。 茲第 本發明尚有許多實施方式。以下舉例說明之。 【實施方式】 第2圖圖解本案資料儲存系統的一種實施方式，其中 包括·一第一記憶體202、一控制器204、一計次模組2〇6、 一校錯模組208與一第二記憶體21〇。 第e己憶體202可施行拷貝回#(COpyback)操作，且其 物理儲存空間乃動態地配置給複數個邏輯位址（主機端程 序所使用之位址資訊)使用。在一種實施方式中，第一記憶 體202可以一反及閘快閃記憶體(NANd Flash)實現。控制 益204將第一記憶體202輕接計次模组206、校錯模組208 以及第二記憶體21〇。计次模組206對第一記憶體202所 VIC09-0〇l〇/〇6〇8-A42140-TW/Final 6 201120897 對應之各邏輯位址的拷貝回存操作進行一計次操作，且根 據該計次操作的結果判斷上述邏輯位址是否滿足一校錯條 件。校錯模組208負責接收自第一記憶體202讀出的滿足 該校錯條件的邏輯位址之資料，對滿足該校錯條件的邏輯 位址之資料進行校錯，以訂正該第一記憶體202。第二記 憶體210則用於暫存該計次模組206上述計次操作的結 果’可由動態隨機存取記憶體(DRAM)實現。 上述計次操作乃用來反應各邏輯位址發生拷貝回存操 • 作的頻度’可有多種實施方式。 在一種實施方式中’上述計次操作包括：計數第一記 憶體202所對應之各邏輯位址發生拷貝回存操作的次數。 該計次操作的結果由第二記憶體210紀錄，第3圖以表格 顯示其内容。如第3圖所示，各邏輯位址LBA(0)".LBA(p) 對應一計次紀錄;計次紀錄mQ...mp為各邏輯位址 LBA(0)，"LBA(p)發生拷貝回存操作的次數。根據第二記憶 體210所暫存之計次紀錄mQ…mp，計次模組2〇6判定拷貝 • 回存操作發生次數超過一上限值的邏輯位址滿足校錯條 件，需要自第一記憶體202讀出以進行校錯。以上限值為 8為例，計次紀錄πν.·ιηρ需各佔至少三位元的空間。由於 第一記憶體202之物理儲存空間所對應的邏輯位址的數量 可能很大，因此如果每個邏輯位址都佔用三位元的空間， 則要求第二記憶體210必須具備很大的儲存空間，為善用 第二記憶體210之空間，計次操作可採用其他實施方式。 在另-種實施方式中，上述計次操作包括：於每次拷 貝回存操作發生時，根據一概率為對應之邏輯位址設定1 \aC09-0010/0608-Α42140-TW/Final 7 " 201120897 頻=示。上述頻度標示可為-位元資料，常態值為，〇，。 以下舉例說明之。假設使用者 :拷貝:存操作即有，機率進行一次校錯，則; 貝回，以概率χ變化該頻度標示 ”、、 八 ;、0又定為1-OP%)八（ι/η)。若使用者希 望同-邏輯位址每發生1G次拷貝回存操作即有9q%的機率 進行-次校錯（即n，，P%=9G%)，則概率χ的理想設定 範圍約為0.226〜讓，為了工程方便，可設定概率乂為 〇·25，意即，針制—邏輯位址，拷貝回存操作發生其上 一次時，計次模組206會以概率〇 25嚐試把該邏輯位址之 頻度裇示自0變化為’Γ，如此一來，從較大的樣本空間上 看，一邏輯位址上平均發生拷貝回存操作10次，則進行校 錯的機率可達90%。各邏輯位址之頻度標示同樣可由第二 記憶體210暫存為第3圓之表格，在此實施方式中，叶次 紀錄πι〇··.ιηρ即各邏輯位址LBA(0)."LBA(p)之頻度標示。 根據第二記憶體210所暫存之頻度標示m〇...mp，計次模 2 0 6判定其中滿足一特定值（如資料’ 1’）的頻度標示所對應 之邏輯位址滿足校錯條件，需要自第一記憶體2〇2讀出進 行校錯。 在另一實施例中，概率設定邏輯位址之頻度標示可藉 由在該計次模組206中設置一隨機數產生器來實現，其產 生隨機數的值可為0〜99 :使用者可以當前的系統時間、中 央處理器的時間標記、或硬體實現的隨機數產生器得到一 高斯白噪音隨機數，並藉由對該高斯白噪音隨機數取^莫數 (除以100求餘數），即可得範圍為0〜99的隨機數。而後， VIC09-0010/0608-A42140-TW/Final 8 201120897 藉由比較_機數與—臨界值（舉例而 25)，若隨機小於>+、姑 界值议疋為 度標示由，〇,設置為t該臨界值，則將該邏輯位址的頻 邏輯位址的頻声^ ，若隨機數大於該臨界值，則維持該 回存操作時二、ΓΓ。如此’當一邏輯位址發生一次拷貝 置為，1，；、輯位址的頻度標示會以25%的概率被設 的可能性進值為，Γ，則代表該邏輯位址有90% 定該邏輯位址滿足校^貝回存操要作，=計次模組206會判 進行校錯。 、日條件，需要自第—記憶體202讀出 種為錯用之校錯技術可有多種實施方式，其中- ^ ^ and correcting *ECC) 〇 校錯模組‘括^儲H包㈣Μ，且第2圖之 久資料」，控制器204自第-記憶體皿 ❹待权錯貧料」，並將其暫存至第二記憶體210以 供校錯模組208進行ECC校錯。 待校錯資料可有多種來源，第4A#4Bffl舉例說明之。 /參，第4A圖’待校錯資料為相關拷貝回存操作「完成 後」之資料·將> 料由頁？喂(1，())送至緩衝器術再寫入 頁page(n，l),待此拷貝回存操作「完成後」，該邏輯位址 即滿足校細條件，貝ij当此拷貝回存操作完成後，相關邏輯 位址之資料方自頁page(n，”被控制器2〇4讀出第一記憶體 202之外作為待校錯資料暫存於第二記憶體21〇,以由校錯 才果組208進行校錯。若校錯模組2〇8顯示待校錯資料有錯 誤，則進行校正，此時校錯結果必須被寫回第一記憶體2〇2 VIC09-0010/0608-Α42140-TW/Final 9 L 二」 201120897 中，當第一記憶體202為反及閘快閃記憶體(nand f 時，由於反及間快閃記憶體的特性必須先擦除後方能寫 入’因此只能由控制器崩新分酉己—閒置的物理位址，如 M〇ckn之未寫入資料的物理頁㈣⑽，以寫入該校錯結 果訂正所對應之邏輯位址資料，圖中以虛線表示此訂正 作。反之，若校錯模組208顯示待校錯資料沒有錯誤 可略過此次校正和寫回程序，無須訂正第—記憶體2〇 内容。 參閱第4B圖，其中，待校錯資料為相關拷貝回存操作 :執行前：之貧料。即是說’當下的拷貝回存操作執行之 前’該邏輯⑽已經狀校錯騎，制足校錯條件之 輯位址當下的拷貝回存操作（虛、線所示）將被此校錯動督 線所示）取代。頁page(l，0)將被控制器2〇4讀出第—記 202之外作為待校錯資料暫存於第二記憶體21〇中，： 由校錯模組2G8進行校錯。*論待校錯資料有 生，校錯結果都將重新寫人第—記憶體逝填人 體202的-閒置空間，例如頁page(n l)，以取代虛線所= 之拷貝回存操作，即是說滿足校錯條件之邏輯位址，^ 收到另-次拷貝回存操作的指令時，並不執行之，反: 上述校錯動作取代。 圖2的計次模組206與校錯模組2〇8除了用獨立於 制器204的模組實現外’還可以用控制器2〇4内部的模ς 實現。此外’第2圖之計次模組2〇6與校錯模組除了 可以硬體電路實現、由控制器204操控外，更可以軟體方 式（例如作為第一記憶體202之控制韌體，即控制器From the shell to another block, such as block one, square block, the storage space is released and marked as available space; the technology of moving the effective data is (4) the face-by-(4). For example, page one (page, 0) to another page, copy the page page (l, G) (10) and save the data to the buffer and pass it to the page pageh! ); the entire data transmission 盗 盗 102 memory inside the internal discussion, the outside world can not peek ^ process limited to the reverse and close flash ^ Sight (4) technology, copy the heart = page 2 move data. This type of copy back memory page 4 field _ the internal buffer of the page, and then another area of the page; its data transfer process is also limited to the inside of the anti-free flash memory. & take advantage of the Han and the gate, the data transfer process of the second operation is limited to the flash of the reverse gate, and it is impossible to know if the copy error occurs in the body and between them. The copy error will accumulate to the extent that it cannot be corrected.旯吾者 [Summary of the Invention] and methods. Including: a first memory, the present invention provides a data storage system, the data storage system disclosed in the present invention, VIC09-0010/0608-A42140-TW/Final ς 201120897 counting module, and a correction module, _ Controller, the memory has a copy-back operation. Control memory (4) counting module and error correction module. Counting and rescuing the copy-back operation of the plurality of logical addresses of the memory to be performed one or two pairs and determining whether the above logical address satisfies the condition of the error-correction, operation, and receiving from the first-memory The data storage method disclosed in the present invention is applied to the error-correcting condition, and the data storage method disclosed in the present invention is applied to the wrong data. Operational - first - memory. The data storage method comprises: performing a copy-back operation of storing a plurality of logical addresses of the f-body; counting the countdown = determining whether the logical bit address satisfies a fault-correcting condition; and satisfying the error-correcting condition read by the memory The logical address of the logical address that satisfies the wrong condition of the school is misclassified to 2 memory. There are many embodiments of the invention. The following examples are given. [Embodiment] FIG. 2 illustrates an embodiment of the data storage system of the present invention, including a first memory 202, a controller 204, a counting module 2〇6, a calibration module 208, and a first Two memory 21〇. The first memory 202 can be copied back to # (COpyback) operation, and its physical storage space is dynamically configured for use by a plurality of logical addresses (address information used by the host program). In one embodiment, the first memory 202 can be implemented in a reverse flash memory (NANd Flash). The control device 204 connects the first memory 202 to the counting module 206, the error correction module 208, and the second memory 21A. The counting module 206 performs a counting operation on the copying and returning operations of the logical addresses corresponding to the first memory 202 of the first memory 202, VIC09-0〇l〇/〇6〇8-A42140-TW/Final 6 201120897, and according to The result of the counting operation determines whether the logical address satisfies a correcting condition. The error correction module 208 is responsible for receiving the data of the logical address that satisfies the error correction condition read from the first memory 202, and correcting the data of the logical address satisfying the error correction condition to correct the first memory. Body 202. The second memory 210 is used to temporarily store the result of the counting operation of the counting module 206, which can be implemented by a dynamic random access memory (DRAM). The above-mentioned counting operation is used to reflect the frequency at which each logical address is copied back to and stored. There are various embodiments. In one embodiment, the above-described counting operation includes counting the number of times that each logical address corresponding to the first memory 202 is subjected to a copy-back operation. The result of this counting operation is recorded by the second memory 210, and the third drawing shows the contents in a table. As shown in Figure 3, each logical address LBA(0)".LBA(p) corresponds to a count record; the count record mQ...mp is the logical address LBA(0), "LBA( p) The number of times the copy-back operation occurred. According to the counting record mQ...mp temporarily stored in the second memory 210, the counting module 2〇6 determines that the logical address of the copying/recovering operation occurrence exceeding the upper limit value satisfies the error correction condition, and needs to be from the first The memory 202 is read out for error correction. The above limit value is 8 as an example, and the count record πν.·ιηρ needs to occupy at least three bits of space. Since the number of logical addresses corresponding to the physical storage space of the first memory 202 may be large, if each logical address occupies a space of three bits, the second memory 210 is required to have a large storage. Space, in order to make good use of the space of the second memory 210, the counting operation can adopt other embodiments. In another embodiment, the counting operation includes: setting, according to a probability, a corresponding logical address setting 1 \aC09-0010/0608-Α42140-TW/Final 7 " 201120897 Frequency = indication. The above frequency indication can be -bit data, and the normal value is 〇. The following examples are given. Assume that the user: copy: save operation, the probability of making a correction, then; Bayesian, change the frequency with probability ”, ", eight; 0 is also set to 1-OP%) eight (ι / η) If the user wants the 9-percent copy-recovery operation for the same-logical address to have a 9q% chance of error-correction (ie, n, P%=9G%), the ideal setting range of the probability χ is approximately 0.226~ Let, for the convenience of engineering, the probability 乂 can be set to 〇·25, that is, the needle-logic address, when the copy-back-storing operation occurs last time, the counting module 206 will try to use the probability 〇25 The frequency of the logical address changes from 0 to 'Γ, so that from the larger sample space, the average copy copy operation occurs on a logical address 10 times, and the probability of error correction is up to 90. The frequency indication of each logical address can also be temporarily stored by the second memory 210 as a table of the third circle. In this embodiment, the leaf record πι〇··.ιηρ is the logical address LBA(0). "LBA(p) frequency indication. According to the frequency of temporary storage of the second memory 210, m〇...mp, the secondary mode 2 0 6 determines that it is full The logical address corresponding to the frequency indication of a specific value (such as data '1') satisfies the error correction condition, and needs to be read out from the first memory 2〇2 for error correction. In another embodiment, the probability setting logic bit The frequency indication of the address can be implemented by setting a random number generator in the counting module 206, and the value of the generated random number can be 0 to 99: the user can use the current system time, the time stamp of the central processing unit Or a hardware-implemented random number generator obtains a Gaussian white noise random number, and by taking a random number of the Gaussian white noise random number (divided by 100 to obtain a remainder), a random range of 0 to 99 can be obtained. Then, VIC09-0010/0608-A42140-TW/Final 8 201120897 by comparing the number of machines with the - threshold (for example, 25), if the random is less than > +, the value of the boundary is the degree, 〇, set to t the critical value, then the frequency of the logical address of the logical address of the logical address ^, if the random number is greater than the critical value, then maintain the recovery operation when the second, ΓΓ. So 'when a logical bit The address is copied once, and the frequency of the address is marked. The probability of 25% probability is set to be the value of Γ, which means that 90% of the logical address is fixed, the logical address is satisfied, and the counting module 206 is judged to be correct. The day and day conditions need to be read out from the first memory 202. The error correction technique can be implemented in various ways, of which - ^ ^ and correcting *ECC) 〇 〇 模组 ' ' ' 储 储 储 储 储 四 四 四And in the second picture, the controller 204 waits for the right memory from the first-memory container and temporarily stores it in the second memory 210 for the error correction module 208 to perform ECC correction. There are many sources of information to be corrected, and 4A#4Bffl exemplifies it. / Participation, Figure 4A's information to be corrected is the data of the relevant copy-restore operation "after completion". Feed (1, ()) to the buffer and then write to the page page (n, l), after the copy restore operation "after completion", the logical address meets the fine-grained condition, and the ij is copied back. After the save operation is completed, the data side of the relevant logical address is temporarily stored in the second memory 21 from the page page (n, " read by the controller 2 〇 4 as the data to be corrected and read. Correction is performed by the wrong group 208. If the error correction module 2〇8 displays an error in the error correction data, the correction is performed, and the error correction result must be written back to the first memory 2〇2 VIC09-0010 /0608-Α42140-TW/Final 9 L 2" In 201120897, when the first memory 202 is a reverse flash memory (nand f, the characteristics of the reverse flash memory must be erased first) Write 'so can only be broken by the controller - idle physical address, such as the physical page (4) (10) of M〇ckn unwritten data, to write the logical address data corresponding to the correction result correction The correction is indicated by a broken line in the figure. Conversely, if the error correction module 208 displays that the data to be corrected is correct, the correction and write back procedure may be skipped. There is no need to correct the contents of the first memory. See Figure 4B, where the data to be corrected is the relevant copy and restore operation: before the execution: the poor material, that is, 'before the copy copy operation is executed' The logic (10) has been wrongly ridden, and the current copy-back operation of the address of the correct error condition (shown by the imaginary line is replaced by the school's wrong line). Page page(l,0) It will be temporarily stored in the second memory 21〇 as the data to be corrected by the controller 2〇4, and the error correction data will be misinterpreted by the error correction module 2G8. The result of the correction will rewrite the human-first memory-filled space of the human body 202, such as the page page(nl), instead of the copy-back operation of the dotted line = that is, the logical bit that satisfies the error-correcting condition Address, ^ When the instruction of another copy-back operation is received, it is not executed. Instead: the above-mentioned corrective action is replaced. The counting module 206 and the error-correcting module 2〇8 of Fig. 2 are independent of the system. The module implementation of the device 204 can also be implemented by the internal module of the controller 2〇4. In addition, the second module of the second figure 2〇6 and In addition to the hardware module fault circuit implementation, controlled by the controller 204, but also can be software manner (e.g., as a first memory control firmware of the body 202, i.e., controller
VIC09-001〇/〇608-A42140-TW/Final 1〇 J 201120897 韌體）實現、由控制器204執行之。或者，計次模組2〇6與 校錯模組208亦可採用軟硬體共同設計實現。 除了以上「資料除存裝置」，本發明更揭露「資料儲 存方法」，應甩於第2圖之第一記憶體2〇2上。此資料儲 存方法包括.對第一記憶體202所對應之複數個邏輯位址 之拷貝回存操作進行一計次操作；根據上述計次操作的結 果判斷上述邏輯位址是否滿足一校錯條件；以及接收自該 第一 s己憶體202讀出的滿足該校錯條件的邏輯位址之資 # 料，並對滿足該校錯條件的邏輯位址之資料進行校^，以 訂正該第-記憶體202。其中，上述方法同樣可】用曰^ 二記憶體(如第2®之第三記㈣21G)暫存上述計次操作的 結果。此外’此方法所應用之計次、校錯技術，皆可以前 述說明書内容實現。本發明之資料儲存方法有多種實施方 式，參閱第5A與5B圖，分別對應第4A圖與仙圖舉例說VIC09-001〇/〇608-A42140-TW/Final 1〇 J 201120897 Firmware) is implemented by controller 204. Alternatively, the counting module 2〇6 and the error correction module 208 can also be designed and implemented by using a software and a hardware. In addition to the above "data storage device", the present invention further discloses a "data storage method", which should be placed on the first memory 2〇2 of Fig. 2. The data storage method includes: performing a counting operation on the copying and returning operation of the plurality of logical addresses corresponding to the first memory 202; determining whether the logical address satisfies a correcting condition according to the result of the counting operation; And receiving, by the first snd memory 202, a resource address that satisfies the logical address of the error correction condition, and correcting the data of the logical address satisfying the error correction condition to correct the first- Memory 202. In the above method, the result of the above-mentioned counting operation can be temporarily stored by using the second memory (e.g., the third (4) 21G of the second). In addition, the counting and error correction techniques applied by this method can be realized by the contents of the foregoing description. There are various implementation methods for the data storage method of the present invention. Referring to Figures 5A and 5B, respectively, corresponding to Figure 4A and the sacred figure,
輯位2接目第4A圖：首先，對應一邏 = = (例如’由第4A圖之頁_) =貝貝至頁卿⑽）後對該邏輯位址 ） 作進行-計次操作（S5G1A) ; *貝口存插 否滿足-校錯條件；該校錯條件，、舉例而言位址是 位址在第二記憶體21G中所對 。疋據該邏輯 輯位址發生拷貝回存操二應欠儲數存=:紀錄判斷該邏 (⑽A);如果滿足該校錯條件=否超過—上限值 讀出該邏輯位址對應之待校錯 」自第—讀體观 其暫存至第二記憶體21〇以進行 ^pa_，i))並將 VIC09-0010/0608-A42140-TW/Final 日=、校驗’判斷該待校錯 11 201120897 資料是否錯誤（S5 供H士 、b503A);如果S503A之校驗顯示該待校 (曰S貝504A)誤鈇則對該待校錯資料進行校正（如ECC) 介Η η ，然谈將校錯結果寫回第一記憶體202 一閒置 = “#iPage(I1，k)) (S5〇5A);如果⑽从之錯誤校 校正和寫回程序t 則可略過35附與咖5八的 跳至步驟咖从热脚正第一記憶體2〇2的内容，直接 S502判斷到滿及分仃，無論錯誤校驗結果如何，只要步騾 所對應儲存之條件，最後均將第二記憶體训中 接下來來^ 果清零（S5〇6A)。 -邏輯位址的η圖’並一併參照第4B圖··首先，對 然後判斷上述她作（s_); 舉例而言是根據該邏輯位址在第夂^校錯條件 存之計次紀錄判斷該邏輯位址發生拷=:所對應， 否超過-上限值（S5G2B) ^拷貝回存㈣的次數是 斷是否收到該邏輯位址另一次滿足該校錯條件，則匈 要特别说明的是，在等待另―、回存操作的指令；這裡 时，控制器204還會達行其它“ ^存=指令的同 (S503B)，·當接收到對该邏輯=乍，此處略去不表 作指令（例如，欲將頁page(i 0)拷Y 一次拷貝回存操 時，並不執行該拷貝回存操作’，而:回存至頁Pagefn，！)） 出該邏輯位址對應之待校錯資料=自第—記憶體202讀 其暫存至第二記憶體2!〇以進行鋩^取頁Page(1，0))並將 待校錯資料有錯誤，則對該待校錯資 〜.a誤奴驗顯不該 YIC09.〇010/0608-A42l4〇.TW/Fiml n 進行校正（如 EC€) 201120897 (S505B) ’接著將校錯結果寫回第一記憶體搬 閒置空間:例如頁刚η，υ)，這裡校錯結果可為寫第至: 圖之校錯杈組208輸出的資料（S5〇6B);如果 錯誤校驗顯示待校錯⑽沒有錯誤，則可略過校正= ㈣5B ’直接執行步驟S5〇6B將未校正過的_ 1Alignment 2, Figure 4A: First, corresponding to a logic = = (for example, 'Page 4 of Figure 4A' = Babe to Page (10)) after the logical address) - Counting operation (S5G1A) * * Bayesian memory insertion is satisfied - error correction condition; the school error condition, for example, the address is the address in the second memory 21G. According to the logical address, the copying back to the memory operation should be owed to the storage number =: the record judges the logic ((10)A); if the error condition is satisfied = no more than - the upper limit value reads the logical address corresponding to "correction" from the first-reading body view to the second memory 21〇 for ^pa_, i)) and VIC09-0010/0608-A42140-TW/Final day =, check 'determine the school to be Wrong 11 201120897 Is the data wrong (S5 for H, b503A); if the check of S503A shows that the school (曰S Bay 504A) is wrong, correct the data to be corrected (such as ECC) η, Talk about writing the wrong result back to the first memory 202. Idle = "#iPage(I1,k)) (S5〇5A); if (10) corrects and corrects the program from t, it can skip 35 5 8 jump to the step coffee from the hot foot is the first memory 2 〇 2 content, directly S502 judges full and bifurcation, regardless of the error check results, as long as the corresponding storage conditions of the step, the final will be In the second memory training, the next step is to clear the value (S5〇6A). - The η map of the logical address' and refer to the 4B figure together. First, then judge the above-mentioned her (s_); For example, according to the logical address of the logical address, the logical address is determined to be copied. The corresponding number of times is greater than the upper limit value (S5G2B). If the logical address is received and the error condition is met another time, then Hungary specifically states that it is waiting for another instruction to return the operation; here, the controller 204 will also reach the other "^ save=" The same as the instruction (S503B), when the logic = 乍 is received, the instruction is omitted here (for example, if you want to copy the page page(i 0) back to the save operation, the copy is not executed. Return operation ', and: restore to page Pagefn, !)) Out of the logical address corresponding to the error correction data = read from the first memory 202 to the second memory 2! 〇 to 铓 ^ If the page (1,0) is taken and the error correction data is incorrect, the error will be corrected. The error is not corrected. YIC09.〇010/0608-A42l4〇.TW/Fiml n is corrected. (eg EC€) 201120897 (S505B) 'Next write the wrong result back to the first memory to move the idle space: for example, page just η, υ), here the wrong result can be written to: The error correction data group 208 output from the prongs (S5〇6B); if the error check to be displayed error correction ⑽ no error correction can skip ㈣5B = 'will not perform Step S5〇6B corrected _ 1
記憶體202 (如頁ρ_η，υ);無論錯誤校驗結果如^ 只要步驟S5G2B判咖滿足該校錯條件，最後均將 憶體2Η)中所對應儲存之計次齡的結果清零（咖 第5Β圖實施例之方法較之第5Α圖實施例，不° 在於當-邏輯位址滿足一校錯條件時，第5Β圖實施例之二 法並不立即對其進行錯誤校驗和校正而是待收到下 拷貝回存操作指令時，直接將待校錯資料讀出第—記^ 202進行錯誤校驗和校正，無論錯誤校驗顯示該待校^次 料是否正確，均將校錯結果（已校正、或無校正）寫回第二 記憶體202中’而並不執行拷貝回存操作。帛5β圖實施 之優勢在於減少了拷貝回存操作的次數，即減少了對第一 記憶體202的寫入次數’可延長第一記憶體繼的使用喜 命。而第5Α圖實施例在拷貝回存操作未出現錯誤（即待$ 錯資料正確）的情形下，可略去將校錯結果(無校正發生）寫 回第-記憶體202的動作’因此第5Α圖實施例在拷貝回 存操作錯誤率低的情形下會顯現效率。 、 以上說明書敘述僅列舉本發明的某些實施方式，並非 用來限定本發明範圍。本技術領域者根據本發明與現有技 術戶 :衍伸出來的任何變形與改良皆涉及本發明技術範圍。 申請專利範圍並非僅限定於說明書實施例内容，更包括本^ VIC09-0010/0608-Α42140-TW/Finai 13 ^ 201120897 技術領域者依照其敘述所能想像到的任何變形 【圖式簡單說明】 v 第1圖以方塊圖圖解一反及閘快閃記情體 示意其中一種拷貝回存操作； _ /、構’並 第2圖圖解本案資料儲存系統的一種實施方 第3圖以表格顯示本案計次操作之結果， 案第二記憶體210中；以及 可暫存於本 第4A與4B圖圖解待校錯資料的多種來源。 第5A與5B以流程圖圖解本案資料儲存方 施方式。 法的多種實 【主要元件符號說明】 100〜反及閘快閃記憶體；1〇2〜緩衝器. 2〇2〜第一記憶體； 204〜控制琴· 206〜計次模組； 208〜校錯模組； 210〜第二記憶體； v ’ 402〜緩衝器；Memory 202 (such as page ρ_η, υ); regardless of the error check result such as ^ As long as step S5G2B judges that the error condition is satisfied, the result of the counted age of the corresponding storage is cleared. The method of the fifth embodiment is different from the fifth embodiment, and the second method of the fifth embodiment does not immediately perform error checking and correction when the logical address satisfies a miscorrection condition. When the copy-restore operation instruction is received, the error-corrected data is directly read out to the error check and correction, and the error correction indicates whether the material to be corrected is correct or not. The result (corrected, or no correction) is written back to the second memory 202' without performing a copy-restore operation. The advantage of the 帛5β map implementation is that the number of copy-restore operations is reduced, that is, the first memory is reduced. The number of writes of the body 202 can extend the life of the first memory. However, in the case of the fifth embodiment, if the copy-recovery operation does not have an error (ie, the correct data is correct), the school can be omitted. Wrong result (no correction occurs) write back to the first memory 202 Therefore, the fifth embodiment is effective in the case where the copy-and-restore operation error rate is low. The above description describes only certain embodiments of the present invention and is not intended to limit the scope of the present invention. The invention and the prior art households are not limited to the contents of the specification, but also include the present invention. VIC09-0010/0608-Α42140-TW/Finai 13 ^ 201120897 Any deformation that can be imagined by the technical field according to its description [Simple description of the schema] v Figure 1 illustrates the reverse flash and flash flashing in a block diagram to indicate one of the copy-back operations; _ /, construct Figure 2 illustrates an embodiment of the data storage system of the present invention. Figure 3 shows the results of the case operation in the table, in the second memory 210; and temporarily stores the data to be corrected in the 4A and 4B drawings. A variety of sources. 5A and 5B illustrate the data storage method of the case in the flow chart. Various methods of the law [main symbol description] 100 ~ anti-gate flash memory; 1〇2~buffer. 2〇2~first memory; 204~ control piano·206~counting module; 208~correction module; 210~second memory; v'402~buffer;
Mock〇、block!、…、blockn〜區塊； LBA(0)."LBA(p)〜邏輯位址； m〇•••nip〜計次紀錄；以及 page(i,j)〜頁，i與j為變數。 VIC09-0010/〇608-A42140-TW/Final 14Mock〇, block!,..., blockn~block; LBA(0)."LBA(p)~logical address; m〇•••nip~ count record; and page(i,j)~page, i and j are variables. VIC09-0010/〇608-A42140-TW/Final 14