201119390 、發明說明： 【發明所屬之技術領域】 是一種多螢幕訊號處理裝 本發明係關於一種處理震置，特別 置以及多螢幕系統。 【先前技術】 多螢幕顯示祕已被肢的使用於各種場合，比如利用多個 螢幕組合成-大型電視牆看板’用於公共場合以顯示的資訊或是 廣告。 請參照『第i圖』，係為習知技術之系統方塊圖。習知技術係 為-電齡統’包括中央處理器81、北橋晶片82以及多侧形處 理器83。 中央處理器81經由北橋晶片82與外界的元件相連。多麵 形處理器83可插於細_，並藉由周雜件互聯响㈣ Component Interconnect，^1)^^^ G_cs PGrt，AGP)與北橋晶片82相連。每個_處理㈣個 別連接至-顯讀幕4域理器81將影像資料逐—地傳送至多 個圖形處㈣83，__ 83分卿於這些影像資料進行解 碼，並分別操取出顯示的畫面。經由同時連接多個圖形處理器幻 的架構，電腦可輸出畫面至多個螢幕。 然而，-般《主機板上可擴充插槽的數目有限。也就是說， 藉由此電腦所能連接至的螢幕的數目也受的了_。除此之外， 201119390 因為每個圖形處理器分別 執行大量的運算。因此，碼的步驟’且影像解碼需要 地輪出。並蝴=爾像峨難以被同步 源的消耗 -叫知雜觸，切成許多能 『第2圖Μ ·技媽使雜齡^請參昭 第㈣』，料習知技街之多螢幕顯示系統的處 ：201119390, invention description: [Technical field to which the invention pertains] is a multi-screen signal processing apparatus. The present invention relates to a processing shake, special arrangement and multi-screen system. [Prior Art] Multi-screen display has been used by various limbs in various occasions, such as the use of multiple screens to form a large-scale video wall billboard for public information to display information or advertisements. Please refer to the "figure i", which is a system block diagram of the prior art. The prior art system includes a central processing unit 81, a north bridge wafer 82, and a multi-sided processor 83. The central processing unit 81 is connected to external components via a north bridge wafer 82. The multi-face processor 83 can be inserted into the thin _ and connected to the north bridge wafer 82 by means of a peripheral component interconnect (4) Component Interconnect, ^1) ^^^ G_cs PGrt, AGP). Each _ processing (four) is connected to the - reading screen 4 processor 81 to transmit the image data to a plurality of graphics (four) 83, __ 83 minutes to decode the image data, and respectively operate the displayed image. The computer can output images to multiple screens via an architecture that simultaneously connects multiple graphics processors. However, the number of expandable slots on the motherboard is limited. In other words, the number of screens that can be connected to this computer is also affected. In addition, 201119390 because each graphics processor performs a large number of operations. Therefore, the step of the code' and the image decoding need to be rotated. And the butterfly = 峨 峨 峨 峨 峨 峨 同步 同步 - - - 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 叫 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第Where the system is:
塊圖。此系統包括中央處理，北橋晶片8心 幻以及橋接介面84。多個_處理㈣細橋接介面^接 藉以擴充圖形處理器83的數目。 、然而，使用橋接介面84會使系統較為複雜並大幅增加成本， 並且多個H 83域f要侧精解碼。錢解竭造成的 能源的消耗依舊懸而未決。 【發明内容】 鑑於以上關題，本發明係提出一種錢幕訊號處理装置， 用以解決f幕數目受限、難以同步化以及线複雜的問題。 本發明所提出之多螢幕訊號處理裝置，係包括一主圖形處理 斋以及複數個子圖形處理器。主圖形處理器分別電性連接至複數 .個子圖形處理器。 主圖形處理器用以承接一外部影像資料，且主圖形處理器可 將外部影像資料解碼並輸出大小為可視範圍的—晝面資料。每個 該子圖形處理器分別同步地擷取該晝面資料的一部份，並且輸一 播放訊號。 201119390 其中主_處理扣及多舒_處理器顧綱 上。此電路板可為一印刷電路板。 队 根據本發賴料錢幕訊號處理裝置，可配合制於一個 人電腦之中。因為不受擴充插槽的數目的限制，明時與多 幕相連。並且只使用單一麵形處理器進行解碼的步驟，不僅 驟 較容易地畔化抑螢幕_的晝面，更可以節省重複解瑪/ 所耗費的能源以及大幅降低所需要的系統資源。 乂 以上之關於本發明内容之說明及以下之實施方式之說明係用 以示範與解釋本發明之雜與顧，並錢供本發明之專利申往 範圍更進一步之解釋。 ^ 【實施方式】 以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其 内容足以使任何熟f相随藝者了解本發明之技㈣容並據以實 施’且根據本說明書所揭露之内容、申請專利範圍及圖式，任何 熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之 實施例係進-步詳細制本發明之觀點，但非雜何觀點限制2 發明之範·。 請參照『第3圖』’係為本發明之-實施例之方塊圖。本發明 所提出之多螢幕訊號處理錢’係'包括—主圖形處理器ig以及複 數個子圖形處理器20。主圖形處理器1〇分別電性連接至複數個子 圖形處理器20。 主圖形處理器1〇用以承接—外部影像資料，且主圖形處理器 201119390 可將外4办像資料解碼並輸出晝面資料的大小為可視晝面的一 晝面貧料。可視晝面係為實際儲存有影像資料的區域。—般來說， 可視旦面的大小即為顯示螢幕的解析度。比如說，解析度為1· Χ1200的顯不螢幕’此顯示螢幕對應的可視晝面大小即為19施 1200。 其中’外部影像資料為壓縮後的影像格式，舉例可為Η264 2(Moving Picture Experts Group » MPEG2) ° 也就是說’主圖形處理器1〇會執行上述格式所對應的解碼步驟。 此外，主圖形處理器1G另可對於影像進行合成的步驟。比如說將 影像與字幕合成一新的影像。 每個子圖形處理器20分別同步地擷取畫面資料的一部份，並 且輸出大小為規格範圍的一播放訊號。 其中，主圖形處理器10與複數個子圖形處理器2〇之間可透 過數位影像輸出(Digital Video Output，DVO)介面相互連接。主圖 形處理器10以及複數個子圖形處理器2〇電性連接至一週邊元件 連接(Peripheral Component Interconnect，PCI)匯流排或一高速週邊 元件連接(Peripheral Component Interconnect Express，PCIE)匯流 排。 請參照『第4圖』，係為播放訊號以及晝面資料大小的示意圖。 播放訊號的大小可為視訊電子標準協會Electronics Standards Association，VESA)所制定的晝面訊號標準。舉例來說， 對於一個1920x1200的晝面而言，水平軸上的總晝素為水平可視 201119390 區間卿個晝素)加上水平空白區間_個晝素广也就是施 個晝素。水平可視區_崎存晝面顯示的資料。水平空白區間 用提供電蝴_所需科間。同樣地，垂直軸上的總晝素為 垂直可視區間_個晝素)加上垂直空白區間(42個畫素)，也就是 ⑽個里素。垂直可視區間用以儲存晝面顯示的資料。垂直空白 區間用提供電視掃描換列所需的時間。 從上可知’雖然-個播放訊號的大小為2592χΐ242個晝素， 但是實際有贿可从只有測Μ·〗目晝素。也就是 說’在播放訊號中，大約只有百分之七十的晝素是實際存有資料， 其他百分之二十的畫素則只儲存空白資料。 此外，在VESA所制定的標準下，播放訊號晝面切換頻率 (frame rate)為60赫芝(Hz)。然而，一般影像格式的切換頻率只有 24Hz。也就是說，只需要保留晝面切換頻率為24Hz的資訊，即可 完整顯示一般的影像。 因此’當主圖形處理器1〇接收外部影像資料並且對其進行解 碼之後。主圖形處理器1〇只會傳送可視晝面大小的資料給子圖形 處理器20。並且，主圖形處理器10會對於解碼後的晝面資料進行 縮減取樣(down-sampling)的動作，也就是將60Hz的切換頻率轉換 成 24Hz。 灵進一步的說’播放訊號的大小為2592x1242，且切換頻率為 6()Ηζ。因此，播放訊號對應的晝素時脈(pixel clock)大約為 193MHz。另一方面，只擷取可視範圍的畫面資料大小為1920x1200 201119390 個畫素，且切換頻率降為24Hz。此時，4面資料對應的晝素時脈 (pixel clock)大約只有56MHz，也就是原本的3〇%左右。因此，在 主圖形處理器10與子圖形處理器20之間所需的頻寬，也只需要 原本的30%左右。藉由只擷取可視範圍的晝面資料以及縮減取 樣，多螢幕訊號處理裝置所需要的系統資源可大幅的減低。 母個子圖形處理器20根據晝面資料存放的記憶體位置，同步 的擷取晝面資枓。每個子圖形處理器2〇再將擷取晝面資料放大之 • 後，並且每個子圖形處理器20會對擷取的資料進行提升取樣 (up_sampling)的動作，也就是將24Hz的切換頻率轉換成6〇Hz ?最 後’每個子圖形處理器20輸出一播放訊號至多個螢幕。 此時，因為播放訊號為實際傳送至螢幕之訊號，所以播放訊 號需要為螢幕所能接受的訊號。也就是說，播放訊號的大小為視 訊電子標準協會(Video Electronics Standards Association，VESA)所 制定的畫面訊號標準。 ® 此時’因為播放訊號為實際傳送至螢幕之訊號，所以播放訊 號需要為螢幕所能接受的訊號。也就是說，播放訊號的大小為視 訊電子標準協會(Video Electronics Standards Association，VESA)所 制定的晝面訊號標準。 請參照『第5圖』，係為本發明之一賣施例之多螢幕訊號處理 裝置外觀實體圖。主圖形處理器1〇以及多個子圖形處理器20係 可位於同一電路板40上。電路板40係可為一顯示卡。 本發明係所提出的多螢幕訊號處理裝置可運用於一多螢幕系 201119390 統’晴參照『第6圖』。此多螢幕系統5係包括一主圖形處理器ι〇、 複數個子圖形處理器2〇以及複數個螢幕3〇。主圖形處理器騎 別電ϋ連接至複數個子圖形處理器2〇。複數個榮幕％係以一對一 方式電性連接至複數個子圖形處理器20。 其中，複數個螢幕30可為但不限於液晶顯示螢幕、電漿顯示 螢幕發光—極體顯*螢幕、陰極射線管顯示螢幕或其他可播放 影像的裝置。這些複數靖幕3G可·成_四謂的螢幕陣列， 比如說2x2或是3x3 _列。此時，若是將四個五十对的顯示榮 幕陣列以2x2的方式排列，排列後的螢幕陣列即可以視為一個一 百吋的螢幕。 請參照『第7圖.』，係為本發明之一實施方式之示意圖。此處 以將-個主晝面分誠_子晝面(A、B、c以及D)，且顯示器 从2x2的方式排列為例。一外部影像資料送入多螢幕訊號處理装 置後’首先主圖形處理器10將主畫面解碼。接著，子圖形處理器 20分職取四個子畫面(A、B、c以及D)，每個圖形處理器14分 別將每個子晝醜大錢幕3G可齡之晝面，麟子晝面送至每 個螢幕30.:播放。·成2χ2的螢幕3〇則可分職放四個子畫面 (A、B、C以及D)，藉以達成將晝面放大播放的功效。、 '根據本發明提出的多螢幕訊號處理裝置，可酡合使用於一個 人電腦之φ。ϋ為不受航簡的數目雜制，_時與多個榮 幕相連b並且只使用單一個圖形處理器進行解碼的步驟，不僅可 較容易地辭化不膽細示的晝面，更可以節省重複解碼步驟 201119390 所耗費的能源以及大幅降低所需要的系統資源。 雖然本發明以前述之實施例揭露如 發明。在不麟本㈣之精神域㈣，所以限定本 所附之申請專利範圍 【圖式簡單說明】 屬本發明之專·護範圍。關於本發明所界定之保護範=參:Block diagram. This system includes central processing, North Bridge Chip 8 and Bridge Interface 84. A plurality of _ processing (four) fine bridge interfaces are used to expand the number of graphics processors 83. However, the use of the bridge interface 84 makes the system more complex and adds significant cost, and multiple H83 domains f are to be side-decoded. The energy consumption caused by the depletion of money is still pending. SUMMARY OF THE INVENTION In view of the above, the present invention provides a money screen signal processing device for solving the problem that the number of screens is limited, difficult to synchronize, and complicated. The multi-screen signal processing apparatus proposed by the present invention comprises a main graphics processing and a plurality of sub-graphics processors. The main graphics processor is electrically connected to a plurality of sub-graphics processors, respectively. The main graphics processor is configured to receive an external image data, and the main graphics processor can decode the external image data and output the data in a visible range. Each of the sub-graphics processors simultaneously captures a portion of the page data and inputs a playback signal. 201119390 Among them, the main _ processing deduction and multi-shu _ processor Gu Gang. This board can be a printed circuit board. The team can work with a personal computer in accordance with the money screen processing device. Because it is not limited by the number of expansion slots, it is connected to the multi-screen in the future. And the step of decoding using only a single polygon processor not only makes it easier to stabilize the screen, but also saves energy and reduces the amount of system resources required. The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the invention and the scope of the invention. [Embodiment] Hereinafter, the detailed features and advantages of the present invention are described in detail in the embodiments, which are sufficient to enable any skilled person to understand the skill of the present invention and to implement 'and according to the present specification' The related objects and advantages of the present invention can be readily understood by those skilled in the art, and the scope of the invention. The following examples are based on the detailed description of the present invention, but are not intended to limit the scope of the invention. Please refer to FIG. 3 for a block diagram of an embodiment of the present invention. The multi-screen signal processing money set by the present invention includes a main graphics processor ig and a plurality of sub-graphics processors 20. The main graphics processor 1 is electrically connected to a plurality of sub-graphics processors 20, respectively. The main graphics processor 1 is used to receive external image data, and the main graphics processor 201119390 can decode the external image data and output the size of the surface data to a visually poor surface. The visible face is the area where the image data is actually stored. In general, the size of the visible surface is the resolution of the display screen. For example, the resolution of the screen is 1· Χ 1200. The size of the visible screen corresponding to the display screen is 19 1200. Wherein the external image data is a compressed image format, for example, 264 2 (Moving Picture Experts Group » MPEG2). That is, the main graphics processor 1 执行 performs the decoding step corresponding to the above format. In addition, the main graphics processor 1G may further perform a step of synthesizing the images. For example, combine images and subtitles into a new image. Each sub-graphics processor 20 synchronously captures a portion of the picture data and outputs a playback signal having a size range. The main graphics processor 10 and the plurality of sub-graphics processors 2 are connected to each other through a Digital Video Output (DVO) interface. The main graphics processor 10 and the plurality of sub graphics processors 2 are electrically connected to a Peripheral Component Interconnect (PCI) bus or a Peripheral Component Interconnect Express (PCIE) bus. Please refer to "Fig. 4", which is a schematic diagram of the size of the playback signal and the size of the data. The size of the broadcast signal can be the standard for the signal standard developed by the Electronic Standards Association (VESA). For example, for a 1920x1200 facet, the total element on the horizontal axis is horizontally visible. The 201119390 range is a bit of a singularity. The horizontal visible area _ the information displayed on the surface. Horizontal blank section Provides the electric butterfly _ required section. Similarly, the total element on the vertical axis is the vertical visual interval _ a single element) plus the vertical blank interval (42 pixels), which is (10). The vertical viewing interval is used to store the data displayed on the face. The vertical blank interval is the time required to provide a TV scan. It can be seen from the above that although the size of a broadcast signal is 2592χΐ242 昼, the actual bribe can only be measured from the test. That is to say, in the broadcast signal, only about 70% of the pixels are actually stored, and the other 20% of the pixels only store blank information. In addition, under the standard established by VESA, the frame rate of the playback signal is 60 Hz. However, the switching frequency of the general image format is only 24 Hz. In other words, you only need to keep the information with the switching frequency of 24Hz, and you can display the normal image completely. Therefore, when the main graphics processor 1 receives the external image material and decodes it. The main graphics processor 1 will only transmit data of the visible size to the sub-graphics processor 20. Moreover, the main graphics processor 10 performs a down-sampling operation on the decoded face data, that is, converts the 60 Hz switching frequency to 24 Hz. Ling further said that the size of the playback signal is 2592x1242, and the switching frequency is 6 () Ηζ. Therefore, the pixel clock corresponding to the playback signal is approximately 193 MHz. On the other hand, only the visual data size of the visual range is 1920x1200 201119390 pixels, and the switching frequency is reduced to 24Hz. At this time, the pixel clock corresponding to the four sides of the data is only about 56 MHz, which is about 3% of the original. Therefore, the required bandwidth between the main graphics processor 10 and the sub-graphics processor 20 is only about 30% of the original. By extracting only the visible data of the visible range and reducing the sampling, the system resources required for the multi-screen signal processing device can be greatly reduced. The parent sub-graphics processor 20 acquires the face assets synchronously according to the memory location stored in the face data. Each sub-graphics processor 2 then zooms in on the extracted data, and each sub-graphics processor 20 performs an up_sampling operation on the captured data, that is, converts the switching frequency of 24 Hz into 6 〇 Hz ? Finally 'each sub-graphics processor 20 outputs a playback signal to multiple screens. At this time, since the playback signal is the signal actually transmitted to the screen, the playback signal needs to be a signal acceptable to the screen. That is to say, the size of the broadcast signal is the picture signal standard established by the Video Electronics Standards Association (VESA). ® At this time, because the playback signal is the signal actually transmitted to the screen, the playback signal needs to be a signal acceptable to the screen. In other words, the size of the broadcast signal is the standard for the signal signal developed by the Video Electronics Standards Association (VESA). Please refer to "figure 5", which is a physical diagram of the appearance of a multi-screen signal processing device according to one embodiment of the present invention. The main graphics processor 1A and the plurality of sub-graphics processors 20 can be located on the same circuit board 40. Circuit board 40 can be a display card. The multi-screen signal processing device proposed by the present invention can be applied to a multi-screen system 201119390 system "clear reference" Figure 6. The multi-screen system 5 includes a main graphics processor ι〇, a plurality of sub-graphics processors 2〇, and a plurality of screens 3〇. The main graphics processor is connected to a plurality of sub-graphics processors. The plurality of honor screens are electrically connected to the plurality of sub-graphics processors 20 in a one-to-one manner. The plurality of screens 30 can be, but are not limited to, a liquid crystal display screen, a plasma display screen, a polar body display screen, a cathode ray tube display screen, or other device capable of playing back images. These complex screens can be used as a screen array, such as 2x2 or 3x3 _ columns. At this time, if four display pairs of display arrays are arranged in a 2x2 manner, the arranged screen array can be regarded as a one-hundred screen. Please refer to FIG. 7 for a schematic view of an embodiment of the present invention. Here, the main 昼 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ After an external image data is sent to the multi-screen signal processing device, the main graphics processor 10 first decodes the main picture. Next, the sub-graphics processor 20 takes four sub-pictures (A, B, c, and D), and each of the graphics processors 14 sends each sub-small screen to the 3G-aged face, and the lindock face is sent to Each screen 30.: play. · The screen of 2χ2 can be divided into four sub-pictures (A, B, C, and D) to achieve the effect of zooming in and out. The multi-screen signal processing device proposed according to the present invention can be used for φ of a personal computer. ϋ 不受 不受 不受 不受 航 航 航 航 航 航 航 航 航 航 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与Saves the energy required to repeat the decoding step 201119390 and significantly reduces the system resources required. Although the invention has been disclosed as the invention in the foregoing embodiments. In the spiritual domain (4) of Linben (4), the scope of the patent application attached hereto is limited. [Simplified description of the drawings] is the scope of protection of the present invention. Regarding the protection scope defined by the present invention = reference:
第1圖以及第2圖係為習 置的系統方塊圖。 知技術之多螢幕顯示系統的處理裝 第3圖係為本發日月之一實施例之方塊圖。 第4圖係為本發明之播放訊號以及晝面資料大小的示意圖。 第5圖係為本發明之—實施例之多螢幕峨處理裝置外觀實Figures 1 and 2 are schematic block diagrams of the system. The processing device of the multi-screen display system of the prior art Fig. 3 is a block diagram of an embodiment of the present day and the month. Figure 4 is a schematic diagram of the playback signal and the size of the face data of the present invention. Figure 5 is a view showing the appearance of the multi-screen 峨 processing device of the present invention.
第6圖係為本發明之一實施例之擷取晝面資料的示意圖。 第7圖係為本發明之一實施方式之示意圖。 【主要元件符號說明】 10主圖形處理器 2〇 子圖形處理器 30螢幕 40電路板 81中央處理器 11 201119390 82 北橋晶片 83 圖形處理器 84 橋接介面Figure 6 is a schematic diagram of the captured data of an embodiment of the present invention. Figure 7 is a schematic illustration of one embodiment of the invention. [Main component symbol description] 10 main graphics processor 2 〇 sub graphics processor 30 screen 40 circuit board 81 central processing unit 11 201119390 82 North bridge chip 83 graphics processor 84 bridge interface