TW201114224A - NoC-centric system exploration platform and the parallel application communication mechanism description format used in the exploration platform - Google Patents

Abstract

Network-on-Chip (NoC) is a popular solution to solve the performance bottleneck of communication in System-on-Chip, and the performance of the NoC significantly depends on the application traffic. The present invention establishes a system framework across multiple layers from a system viewpoint, and defines the interface function behaviors and the traffic patterns of layers. The system-level simulation is used to simplify any unnecessary detail. The present invention provides an application modeling in which the task-graph of parallel applications is described in a text method, called Parallel Application Communication Mechanism Description Format (PACMDF), accordingly reducing the overhead of coding. The present invention further provides a system level NoC simulation framework, called NoC-centric System Exploration Platform, which defines the service spaces of layers in order to separate the traffic patterns and enable the independent designs of layers. Accordingly, the present invention can simulate a new design without modifying the framework of simulator or interface designs. Therefore, the present invention increases the design spaces of NoC simulators and design flexibility, supports a wider design space of NoC simulation, simplifies the design flow before constructing a new NoC design, and provides a modeling to evaluate the performance of NoC at the design stage.

Description

201114224 VI. Description of the Invention: [Technical Field] The present invention relates to a Network-on-Chip (NoC), and more particularly to a system exploration platform for a single-chip network; The layers are segmented and the simulation models are made independent of each other; the exploration platform uses textual methods to describe the working diagram of the parallel application. [Prior Art] System-on-Chip is becoming more and more complicated due to advances in the process of ultra-large integrated circuit (VLSI). Increased number of components such as multi_c〇re processors, ip units, and function controllers (c〇ntr〇llers) 'calculates the performance bottleneck of the original system chip (perf〇rmance bottleneck) The transfer of circuits (compUtation circilits) to communication circuits' also causes communication bottlenecks (c〇mmunicati〇n bottleneck) to become more and more serious, making communication circuits the key to system chip design. Network-on-Chip (NoC) is a popular solution for communication bottlenecks, making it an emerging research area. The single-chip network takes the design of the system's chips in a computation-oriented, steering-oriented manner. The single-chip network solves many of the problems in today's mainstream buss architecture, such as scalability (w), and low-throughput. However, single-chip networks often use more network resources, such as buffers and switches, and must consider more complex and power-hungry circuit designs, such as routing units. Therefore, the exploration and simulation of the design becomes more important before the actual construction of the single-chip network. The conventional single-chip network research, the simulation environment and process are shown in Figure i. The application model (application m〇del) block U is used to describe the traffic model 201114224 (traffic pattern), and the single-chip network design (NoC design) block 12 is used to describe the components of the single-chip network, Computation nodes and adaptors. The message characteristics 13 are used to describe a bus transaction, a packet format, or a flow control unit. These blocks are input to a single-chip network simulator 14, and a simulation report (rep〇rt) i5 is output after the simulation is completed. However, the conventional analog environment of FIG. 1 does not have a uniform specification for describing the input of the application block U, the single-chip network design block 12, and the message characteristic block 13, so different designs are needed once needed. When a block is replaced, the originally established block has poor reusability and small design flexibility, and the design exploration space is thus limited. In addition, CoWare's CoWare Convergence SC and ARM's SoC Designer provide a complete framework for handling component entanglements, intellectual units, and busses. However, because the framework uses a cycle-accurate hardware model and an instruction-accurate software model, it is time consuming to simulate a more complex single-chip network. In addition, these conventional techniques take a lot of effort to construct a new application with executable code as input, and spend a lot of effort to describe a new single-chip network in the bus interface. In order to improve these burdens, 'Xu et al. in the EE paper, ' a Meth〇d〇1〇gy f〇r to _,

Modeling, and Analysis of Networks-on-Chip», Circuits and Systems, 2005, ISCAS 2005, using a computational traffic pattern (communication network model) (deleted (4) this (10) face network network modd). However, the simulated environment age provided by it is cut into many different codes, S. —·· 4 201114224 'Each step uses different simulation tools and evaluated measurement standards, and there is information loss between steps and steps (informati 〇ni〇ss), so I can't get information about the entire system. In addition, Kangas et al. at " UML-based multiprocessor SoC design

Framework, ACM transaction on Embedded Computing SyStems (TECS), 2006, Vol. 5, 2, using a Universal Modeling Language (UML), which inputs work-based applications and NoC modules (modules) ). However, the provided environment does not directly follow the simulation model established by SystemC s. (simuiati〇n m〇(jeiing), but

SystemC is a language often used in hardware-software co-simulation. SUMMARY OF THE INVENTION One object of the present invention is to provide a system-standard design framework, which is not a complete single-chip network simulator, and the network design simulation is simplified to have little effect on the performance. Single (9) network part of the fine simulation speed. The system discovery platform of the single-chip network of the invention simplifies the system design and construction, the process, and can be customized (cust0Blize) design, and does not need to consider the system design trivial = detail problem. In particular, the present invention is used in the early stages of system design to explore the design space of a single wafer, a circuit, before software and hardware specifications have been developed. The purpose of the secret i〇=P is to expand the domain to prepare the environment (Si Fu this plus (10) painting bile t), so that the space for exploration and exploration increases. The models (mQdels) and Ιϊϋτ/Γτ·10 of the present invention have no side to the programming language, so that another object of the present invention is to provide an application definition. The present invention uses a task graph-based application model called Parallel Application Communication Mechanism Description Format (PACMDF) to generate traffic similar to the instruction simulator. The pattern (traffic pattern), but the screen divides the precise complexity of the instructions, thus reducing the burden of coding. A further object of the present invention is to provide a system framework that can simultaneously evaluate performance at the time of design. The design of the screen transfer RTL (register transfer level) does not use a Cycle-accurate design, but takes a cycle. Approaching

Event-driven event driven design. The invention also adopts a fully parameterized hysteresis model (full_parameterized latexncy modelj design) to quantitatively evaluate the benefit of each design link to the entire system. Single f-chip network design must carefully consider various design trade-offs, and select the pair The most efficient design of the system (ad_hQG design), not just the application of all kinds of network design on the chip, because the resources of the single-chip network are more limited than the traditional network environment. Through simulation, one can be evaluated. The communication structure design is optimal for the whole wafer network, and the cost-effective (6) st_perf_nee is selected. The simulation framework provided by the present invention (simulati〇n framew〇r positive single-chip network design, but not after the design is completed. More specifically, the present invention can be mixed without _ level, different fineness (granularity) Simultaneous verification and redesigning the 'layered design of the road system' to pass the wealth of the job to test the framework f! Dan = real application of the traffic pattern generated by the application, for the convenience of explanation and understanding, the manual The implementation is divided into sections 'detailed separately: 戍1. System discovery platform for single-chip network; 2. Performance evaluation; 3. System layering; 201114224 4. Application modeling; 5. Parallel application communication machine 6. Intermediate layer modeling and [system exploration platform for single-chip network] "system exploration definition" of the present invention

LevdModding) The sub-level model (the effect of the overall performance of the Transaction Road). The platform counts the single-chip network ii; '"The platform is used for simulation

The Platf〇Lt film exploration platform (10) is the Nocsep between the coffee s_ __ platform} ', and the N 〇 CSep system is synonymous with the second cable platform, and the system of the invention is alternately made. The system of the chip network explores the platform rather than being built, more refined === difference. The invention uses the "1" door invention and the general single-chip simulator ri "1 unexplained situation, and through the systemization, regulation, and slab-type board revision and correction, to explore the possibility of a single-chip network Design space. After that, according to the performance of the various implementations of the design m, the final design is 3 2 and then the name of the invention "system" exploration platform is to use the system design target to intervene unnecessary simulation. Details, pre-planned feasible N〇c design. The Noes printing entity of the present invention is divided into three parts, and the brief description is as follows: 1. Model design: NoC-centric system, required software model, hardware model, and communication information (communication message) model. It performs a network cross-layer and a multi-layer abstraction layer (muWple North Gaby (10) levd) for the N〇c system. It can be further divided into two modules' including: a. NoC service (services): contains a communication information model to describe the content of the request sent to the network service and the control and protocol information of the network resource interface; the so-called service 201114224 Represents all information flowing between hierarchies and between hierarchies; and b. NoC service handlers: Contains NoC software models, hardware models, to describe the way in which NoC services are generated or processed . 2. System firamework design: Establish a system framework that simplifies the cross-network level from the system specification, defines the function behavior of each level interface and the transmission method of NoC communication information. The purpose is to establish the traffic pattern from the top to the bottom of the system level (trag|C p such as 3. The simulation environment: the simulation environment of the Nocsep model and the Nocsep system framework according to the system chip, and The simulation and performance evaluation are provided according to the established NoC system. Figure 2 shows the simulation environment diagram of N〇Csep. Under the conventional architecture of Figure 1, this month 2 knows: the unified specification description input, including N 〇csep application Regulations 21, Nocsep service handler Regulations 22, and N〇csep service rules (semce^gUlatoins) 23, constructing the framework of the present invention (framew〇rk) 24, and then according to these unified input description simulation, and finally the simulation of the newspaper shakes = the towel will be described in the 'bribery job position 21 job in the parallel application communication mechanism description format pACMDF" mode, Describe the work diagram of parallel bribery (shown in the table..., after the details of 5 £=$_范23麟 should be issued 0 kinds of information layering" Nocsep's unified specification description has the following advantages: The scale can be extended to the system level one 2· 3.:=:= two simulator implementations 'so no need to change 201114224 [performance evaluation]: a new NoC system, you must understand its effectiveness; the general way is to The NoC system evaluates the total execution time required for an application. Most of the existing simulators are based on the delay time and simulation behavior of "NoC traffic generation to its end" to estimate the design efficiency of n〇C. The NoC's average throughput, average transmission hysteresis (c〇mmunicati〇n iatency), and average contention rate are all indicators of estimation. The general simulation method is based on the statistical characteristics of an application (statistical feaUires "To carry out random number simulation. However, in fact, most of the application behavior is not random. Real program traffic must consider the interaction between different levels, for example, 'for example, chip computer architecture (0CCA, 〇 The request sequence issued by n_chip c〇mputer Architecture is affected by the multi-task mode of multiple system processing units. Therefore, the Nocs of the present invention Ep does not only consider the single-layer network single-level design concept. It incorporates higher-level models of the network, such as tasklayer, thread layer, node layer, and transit. The adaptor's design covers the software level and arrives at the CCA level, enabling the N〇csep software model to produce traffic patterns that are closer to real-world applications. In evaluating the performance of a single-chip network, Nocsep adds the application's working operations to the simulation time hysteresis' using a combination of hysteresis functions to approximate the real life of the hardware for the job. ~ The present invention estimates the execution time of an application by breaking the behavior of the application into a number of services' and retaining the context between the services, inputting to a plurality of service handlers. A single-chip network system. The above services represent all the information flowing in the hierarchy and between the levels, including hardware interface specifications, hardware control signals, software data content, firmware work or tasks. In addition, different network levels use different levels of abstraction services. The above service handler refers to software or hardware that can process services or deliver services. In other words, the total execution time is estimated to be equal to the sum of a plurality of service handling latencies. If there is 9 201114224 late 1, (laten'y 〇 veria_ the situation 'this invention will also _ _ will also - and consider. The material space of the single-chip network _ is a lot of blocks, and to compare: π,:, the details of the body are wrapped in a stranded hard package. As in the microscopic view, it is still modelinT)4!tJt^J (cycle-aPProximati〇n latency mtnS^Tt 5 handling) >For;:乂: 2仃, may also be carried out in order. Each of the sub-behaviors can be grouped with people to ^ ^ 仏 仏. Some sub-behaviors must wait for an event or an event to occur after the occurrence of the event. The wait time is also . Therefore, a tree-like structure can be formed, which is the sum of the hysteresis in the tree _, 丄 ^ tree. The s 仃 迟 迟 · 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间 时间The representation behavior can be decomposed into many sub-behaviors, expressed as 1^two as} 'where the communication exchanger passes the time, '...}, and the switch passes the time elapsed by the switch, the switch elapses time = {route , the resource is equipped with two, and 0 J is decomposed, which is expressed as: Forming a tree-like structure, the uppermost layer is delayed when the behavior is delayed, and the hysteresis of the structure is summed. The locating system is through this complex tree. In the present invention, the limit cycle approach model is not used (d〇ck_edge(10)t) to describe the behavior, the fine and the weekly edge event (cyde-accurate tra job ti〇n Wd coffee == In the protocol level model, the clock signal is recorded as a recording event. In the cycle approaching the model period, it is a simplified non-synchronous circuit description. From a hardware point of view, the hysteresis model of the week is not simulated. The second detail fully estimates the delay of the service. For example, one, only need to simulate to routing, may generate new, ° computing components through the exchange ^ cry ^ exchanger (routip Qin, 201114224 C^put=), it is also possible to use the source route in the message segment (s_2 for the path* component model of the present invention, no matter what kind of production mode is white, the direct delay is delayed, and then the information scale is given information. [NocseP System Layering], close to a more realistic traffic pattern, the present invention in addition to the single-chip network level, = consider the higher-level model of the network, such as the working layer shouting), thread Layer Layer), node layer (n〇de layer), and adapter layer (four) qing h (four).

Therefore, 'this hair duck-a single-chip network is divided into five layers, as shown in Figure 3. The characteristics are as follows: 1. Task iayer 3 〇: This level uses the work diagram (task level 叩 "description Applying 耘-type features, including computing services, communication service generation values and generation conditions, and virtualizing external I/O behavior; working in the present invention to describe the source of all services of the system (sources) are included in the working layer In the executor layer; 2. Threading layer (Ding 111^(1_1')31: Using the thread module (^11^111〇(11116) to describe communication between work rooms, task grouping, and thread assignment (thfead mapping) 'and program parallelization model (paraUelismm〇del); 3. node layer 32: use node module (node m〇dule) to specifically describe task arbitration and schedule ), the multi_tasking strategy of the operating system, the capability of the computing unit (c〇mputing power) and the behavior of the communication unit (communicati〇n behavi〇r); 4. the adapter layer (adaptor layer) 33. Adapter module (ada Ptor module), which specifies the on-chip communication architecture (CCA) interface, the circuit-switch network, the packet-switch network, and the convergence. Different OCCA components such as BUS-like communication architecture; and 5. On-chip communication architecture layer 34: All objects and sub-objects that construct OCCA are set at this level. Communication architecture design of single-chip network system; Οη-φίρ Ί 201114224 communication architecture means that this level supports NoC and also supports general communication architecture. Figure 3 is a schematic diagram of service model layering of Nocsep. The squares shown represent the different levels defined by Nocsep, and the arrows between the squares represent the traffic formats. The input to job 30 in Figure 3 is the source of all traffic, the plural shown in Figure 3. "Channels", including Block 36, Box 37, and Block 38, can be considered as different designs in the hardware. Face "all the elements below the real dagger will do it for this interface function. If you need to simulate different hardware designs in the same network level, as long as you support the same interface, the hardware models of other levels do not have to be changed. Work 3 is contained within threads 31 and passed to node 32 in a "messages" traffic format. The information is converted to a different traffic format in each level of Figure 1. When a message is converted by the node 32 into a plurality of "stream" traffic formats, the stream arrives at the adaptor layer 33 through the process channel 36. The program channel is a virtual, (pseudo) channel concept 'can be actually constructed to constitute a thread-to-thread channel, node-to-node channel, or adapter-to-arulator channel. The stream passes through the adapter layer 33 and is converted into a "transferpackage" traffic format. The real network channel 37 is the access interface of the chip communication architecture layer (〇ccAlayer) 34. After the wafer communication architecture layer 34, the transport package is converted into a physical ehannel unit' to the physical layer 35 through the lowest level physical channel (i〇west_ievei phySicai c|iannel) 38'. When the traffic of the upper level of Fig. 3 is converted into the traffic unit of the lower level, the plurality of traffic units of the lower level collectively own all the contents of the source parent communication format. This issue divides the single-chip network into a system design space by "network layering" to construct a standardized single-chip network view. Then, each network layer design creates different simulation models with different abstract levels, and completes finer simulations one by one. The layering objective of the present invention is to enable each level of service design space to be independent of each other so that 'different kinds of service handlers can only know the information of their corresponding levels. ' 201114224 Under the layered design of the present invention, since the service design space of each level is independent, it is only necessary to use the same service model (service m〇dd) to achieve a simulation by causing a part of the undesired hierarchy to be disabled. The purpose of a particular level. Under this concept, the frame or interface design of the no-reader simulator can be used to simulate the new service design and use its hardware only by directly changing the data structure corresponding to the service. Therefore, the coding burden of the present invention can be reduced, and the design space and flexibility can be increased. See Table 1 below for examples of service types and service content at each level.

Table level service type (service type) service content (task layer) task trace line (trace line of task) 1. job type (task type) 2. calculation service content (computation service Content) 3. Communication service content node layer message (task group ID) adapter layer (adaptor layer) stream (stream) 1. stream data size 2. High-level protocol information 3. QoS constraints 4. Reserved virtual network identifier 0CCA layer (OCCA layer) packet (packet), flow control unit (flit) 1. Packetization 2. Routing information 3. Flow unit priority 4. Retain the physical layer of the real network resource (such as virtual channel) (physical layer) ) physical channel unit, buffer item 1_ time-division multiplexing unit 2. interrupt rate (broken rate And the correction overhead (detailed design in bit level), for example, the first 5 bit record routing, the last 25 bit record content, the last 2 bit error debugging . 13 201114224 In the present invention, 'services' means all information flowing in and between levels, including hardware interface specifications, hardware control signals, software data contents, and chapters of the blade. Work or task, etc. Different abstraction levels of services are used at different network levels. A service handler is software or hardware that can handle a service or deliver a service. [application modeling]

The task layer is contained within the thread layer, the task is the basis, and the traffic source is defined as all execution periods. The input cNoC related to the system simulation is defined by The external input software and hardware resources are included in the work information (or trace line information), such as the application at the top of the network level, or the system input and output components.曰 斗斗八 shows the application model (10) of the present invention (4). There are three ways of generating traffic for threads: random traffic, appiicati〇n_driven traffic, and event-oriented traffic, Cevent-triggered traffiO. Figure 4A shows the above three types of intersection generation, including application-oriented traffic G1, random traffic G2, and event guidance = traffic G3. The random traffic G2 is a health or hardware service generated by green, which is generated according to the parent's traffic statistical features. The event-oriented traffic 1 is generated by the town, and it is the root of the _adS) ^ Some of the events received are generated, for example, (four) training requirements (data which (four). Application ^ guide traffic G1 by In the present invention, it is described by using parallel, New-style through-the-loop PACMDF, and Rong Lin is a detailed description of the hybrid synthesis - a group of powers (four) glOUp), the group All have the same = group identification code. As shown in Figure 4A, the application-oriented traffic (1) consists of a circle of three work groups representing the computational work (C〇mputationtasks), while the arrow and the second knife are used to represent the communication work (c〇mmunicati〇n tasks). Execution 啫 is separated by f guards. Figure 4 shows five threads!!, T2 3, T4, T5, where 执行1Τ2, Τ3 all contain multiple work groups. The application traffic (applicati affic) is generated from the "work" and transmitted through the execution of the 201114224 layer and the node layer. For the transmission of the content and the process, please refer to the detailed description of the N〇cs system layer of the implementation system. Figure 4A shows four nodes Nl, N2, N3, N4 at the same time. The knot, point N3 contains two threads T3, T4; the node layer (n〇de layer) is described in detail later. [Parallel Application Communication Mechanism Description Format - PACMDF]

The present invention also proposes a working diagram for describing a parallel application, that is, a detailed program-oriented traffic G (referred to as Parallel Application Communication Mechanism Description ^nat) hereinafter referred to as PACMDF. In this manual, the parallel application communication mechanism description format is equal to the PACMDF system and is used interchangeably. The parallel application communication mechanism description format of the present invention, pACMDF, is used in a parallel application to describe the "communication" flag _em). It will show the parallel application's image _) in a defined description, so it is easy to write and change the feeding. As far as the system is concerned with the implementation of the program, it is highly detailed. Therefore, in addition to the hardware model, there must be a software application model that is applied to each other as a simulation of software and hardware integration. A line of text is used to describe a task, which removes the input code of the program by dividing the heartbeat in the pattern. PACMDF divides the working diagrams of the application into eight categories, as shown in Table 2. Table 2 classification calculation work '(computation task) sub-category" calculation work stone ~~ (computation task) Content calculation unit" • 1^ SIU-1 (communication task) data sending task The size of the data transferred to the thread. Notification sending task Sending non-data messages, such as receiving packets, or controlling packets. 15 201114224 Memory read Reads a memory address, read address, data Volume Write memory (memory write) Write a size of a certain address of the memory, including the read address, the amount of data. Task graph control thread re-run is not obvious in the work diagram, it is divided into ^^ repeated execution (conditions that can be specified or repeated), unlimited execution, And a limited number of iterations and the end of the entire work diagram. Supplemental information for the previous job. The thread forced to idle for a while causes the thread to temporarily stop for a period of time without occupying the single-chip network resources. The PACMDF includes multiple fields, and each of the work categories listed in Table 2 should have different fields for the PACMDF. The columns for PACMDF are listed in Table 3. Table 3 ~~~~ ~PACMDF^~ Mark --- Participate in the statement of the main or execution Fan ^ # : The behavior note. ~~~~ ;: This line must be executed. Type of work Type of work type busy: Represents calculation '~~~—(computation) or I/O access (access) ° send : stands for message, including data instruction. One ---------- Work Ctrl: Control signal. ------ oOlirCc Destination Source Job Endpoint Work number. ~~一' work number; used to notify T Ak: work feature Size/Execution size/execution time Calculated operation value Id The byte size of the work transfer" Work code. ~ Trigger feature iriggcring source The source of the job needs to perform the feature 1 riggering task id Trigger the job number -- points to the work code that caused the trigger. LII6CI1V6 Dependent Describe the validity of the work, for example, the probability of the job, the condition of the execution control ~~~-___ ------, etc. ~~ — ” 201114224 The need for miscellaneous is only the basic block of enumeration. In actual use, it can be used as a PACMDF_ for non-use of ^3, and it can be used as a sample. Computational work 笪 41, calculation red work 42, calculation work 43, calculation work ^, ίί ϋ calculation work 46, calculation work 47, and calculation work 48, representative; representative arithmetic unit and operation value. Lift the ship Ming,. ρ = 1_ C is the initial addition. In Figure 4, each line segment represents a pass.

The number I follows represents the length of the transmitted data (in low units), the byte. The calculation guard 41 is triggered by itself, and is calculated by the calculation work 45, 46 or 47 before the calculation. _ A single line should be a program (parallel pipeline appiication) in the calculation work 48 after 4 1UUU * ^ stop. = indicates the representation of PACMDF in Figure 4B. For the sake of convenience, in Table 4, the number of columns that do not correspond to the number of columns is not included. In actual use, the first column of the number of columns can be used to represent a job. Among them, busy is ¥ ^ for the work of the program, send for the Type represents the communication work, and c for the Type represents the control signal. In Table 4, related to the calculation work, it can be decomposed into eight jobs, corresponding to each, and four from eight to eight columns. The first column starts with #, which means it is an annotation (c〇mmentf ..., must be executed. The second column is the initialization of a calculation work, and then the third is the execution of the nose in the box. 〇〇〇 'that is to add 1000 operations. After the operation of the work element, in the fourth column, it means to transfer a 64-bit data to the destination block of 42. The fourth column of the Id block is The s before S2,2 indicates that it will trigger the work of another column. The Triggering task id field 彳2,1 is the 13th column, 19th column and 25th column corresponding to Table 4, indicating that Hi must wait for the 4th column. The work is finished, and the Effective field in column 4 is pi, indicating that the absolute probability of executing the column is 1. In the Effective field 'for example, column 52, 3000, the corresponding value represents the number of times the column is repeatedly executed. In the 49/51 column Size/Executiontime block i

ί C 201114224 indicates the characteristics of the work, its appearance, w corresponds to Figure 4B, must wait for the calculation work 45 to be f-execution, one of the work 47 - after arrival, the calculation of the work is calculated

Tnggering — _Plex representation in the id block: etc.: Start with 8 columns. For example, the 48th column waits for the "w" condition in the 49th-th column. The work chart of the ^ can be expressed as a table using PACMDF. 4 _ The description of the text, corresponding to the table 4 δ to understand Table 4, so will not repeat them. Table 4 column number Mark Type Sourc e Destinati on Size / Execution Time Id Triggerin g, source Triggerin g, task id Effectiv e 1 # task T41 2 9 busy 41 1 1 Initial 3 9 busy 41 i叩1000 1 Initial 4 9 send 41 42 64 S2 pi 5 9 send 41 43 64 S2 pi 6 > send 41 44 64 S2 pi 7 > busy 41 inplOOO 1 pi 8 Ctrl 41 end 3 1000 9 # taskT42 4 10 9 busy 42 1 1 Initial 11 9 busy 42 i叩1000 5 Initial 12 send 42 45 64 S6 pi 13 ? busy 42 inplOOO 5 2 pi 14 5 Ctrl 42 end 7 1000 15 # Task T43 8 16 busy 43 1 1 Initial 17 5 busy 43 inplOOO 9 Initial 18 > send 43 46 64 SI 0 pi 19 3 busy 43 inplOOO 9 2 pl 20 5 Ctrl 43 End 11 1000 21 # taskT44 12 22 ? 1 1 Initial 23 busy 44 inplOOO 13 Initial 24 5 send 44 47 64 SI 4 pi 25 ? busy 44 inplOOO 13 2 pl 26 ? Ctrl 44 End 15 1000 27 # taskT45 16 28 5 busy 45 1 1 Initial 29 5 busy 45 inplOOO 16 Initial 30 5 send 45 48 64 SI 8 pi 18 201114224 31 , busy 45 hip 1000 16 6 nl 32 , Ctrl 45 End 19 1000 33 # taskT46 20 34 9 busy 46 1 1 Initial 35 9 busy 46 inplOOO 21 Initial 36 , send 46 48 64 S2 2 pi 37 , busy 46 inplOOO 21 10 pl 38 > Ctrl 46 End 23 1000 39 # taskT47 24 40 , busy 47 1 1 initial 41 busy 47 inplOOO 25 initial 42 9 send 47 48 64 S2 6 pi 43 , busy 47 inplOOO 25 14 pl 44 > Ctrl 47 End 27 1000 45 # taskT48 28 46 > busy 48 1 1 initial 47 > busy 48 inplOOO 29 initial 48 5 busy 48 inplOOO 29 complex pl 49 5 para 48 w or 29 13 18 50 para 48 w or 29 14 22 51 5 para 48 w or 29 15 26 52 9 Ctrl 48 End 31 3000 53 # taskT49 32 54 5 Ctrl 49 End 35 1 55 # END OF TRACE FILE 36 [middle layer modeling] The present invention provides detailed modeling (m〇deiing) in the middle layer, and the so-called middle layer refers to the application layer (application) The hierarchy between layer and NoC 'includes node modeling and adaptor modeling node node system processing eiement structure' and operating system program handling (〇s process handling). The node layer emphasizes the behaviors that can significantly affect traffic, thus reducing many of the details that are not needed in the real world. See Figure 5' for a node modeling. The tasks from the threads enter the request tabie 5l. Request Form 51 A form (iist) that temporarily holds all entering messages (holding all entering message. 19 201114224 temporarily). The request table 51 includes a plurality of expansion slots (9), and an expansion slot 511 is assigned to a fixed thread ID and a specified task priority. Figure 5 also shows three core (c〇res) units 5 5 containing a heterogeneous core (c〇mpUtati〇n c〇re) and two communication cores. A core manager (kemd_ah) 52 is a <body", which is responsible for arbitration and selects a reed* from the request list 51 and assigns it to a core through a work scheduler 54 (c〇re Unit 55, and the information is processed by the unit 55. If the core unit 55 is a computing unit, the computational effort assigned to it will be resolved based on the computational power set by this unit and the delay. At the same time, the relevant status events (status events) are generated. These events are transmitted to the source thread of the § 彳 ce ce ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( (疋—a communication unit that will generate the information required by the job and pass it to the transfer. The connection will communicate with the adapter and convert the data into N〇c in the adapter. The mechanism is described later. The Figure 5 towel contains an event coUector and trigger 53. If there is a need for event triggering, the unit will collect the events to the corresponding thread. A message must be selected by the core manager 52 to be processed. The port in Figure 5 is connected to 埠p〇rts) and is a virtual port. In addition, the node of the present invention is modeled and cumbersome, so the number of core managers in Fig. 5, the computational kernel (10), the number of n(7) calls, and the number of cores can be parameterized. Figure 5 is only intended to illustrate and explain the examples and is not intended to limit the invention. In the node model of Figure 5, traffic distortion (traffic touch occurs in the following cases: L. If the expansion slot H1 is occupied, the information cannot be serviced; 2. If the core gammel managers 53 is insufficient, or the nuclear unit & is insufficient, the information will be idle; 3. Even the core unit's time sharing mechanism (time_sharing Lan (4) (10) will also affect traffic. 20 201114224 Adapter (adaptor) Used to distinguish the traffic between the node and N〇c. Based on the layer, 'and existence', it is possible to compare different NoC designs under the same simulation conditions (slmulati〇nc〇nditi〇ns) Figure 6 shows an adapter model (adaptor modeling). The communication core of node 66 ([, shown in Figure 5) must utilize a manager au〇cat〇r 61 and a buffer. A resource allocator (bufferres〇urceai丨〇cat〇r) 63, to configure (alk) cate) a manager resource 62 and a buffer resource (buffer res〇urce) 64, to determine a = stream system can be transmitted or Waiting for the resource due to insufficient resources. The manager > source 62 contains complex A stream manager (streammanager), which buffer resource 64 includes a plurality of program packet rather left foot column queue). The communication core that gets configured in a stream = Start Transfers node 66 begins to send data to the buffer packet in the buffer resource. In this program queue, the stream is converted to the N〇c transport package type. The so-called Noc transfer package refers to the data structure that N〇c can transmit; for the packet exchange (package_switched) network or the flow control unit basis (flit-based) direct connection to the Internet (10)-touch (9) sink (8), the use of packets Or the flow control unit as a transfer package; and for another circuit exchange (€11_^(^(1))^〇(: or directly connected to the network ((1丨1^_1丨11]^11_〇1) ^, the transaction unit is used as the transfer package. The adapter 6 includes a connection port (p〇rts) 651, and the adapter 6 is responsible for encapsulating the transfer package and sending it by the port 651 The package is connected to the connection bee 652' of the N〇c component 67 and maintains the endpoint-to-endpoint flow control (end_t〇_end.ff〇w control). The NoC connection 埠652 is busy or packaged. In the case of a full line (fUU), the adapter 6 has to wait. If the application is latency-sensitive or the buffer space of the system is very limited, the effect of the adapter 6 on the performance appears. Especially important, traffic thr〇ughput will also be affected. Medium 'package generation rate ^package generati〇n rate), maximum queue length (maximum queue length), handling latency for each step 'and the total number of buffer resources (t〇tai buffer s〇urce) All are parameterized, 201114224 The NoC system design space of the present invention is clearly divided, the system is divided into multiple layers (layers are divided into multiple components (comp〇nents), and the components are further divided into A plurality of abstraction level models are implemented with a plurality of latency parameters. The present invention cuts the design space of a single-chip network into a plurality of design blocks and models them in a hierarchical manner. The so-called abstract hierarchy means that the details of the hardware are wrapped in the elements of the lower level to form a package. As in the microscopic view, it still

Retaining the good features of the hardware design, but can reduce the fineness of the hardware construction and reduce the simulation time. The embodiments disclosed in the present invention are only used to illustrate the features and spirit of the invention, and are used to limit the invention itself. The age of the present invention is subject to the following specifications and the broadest interpretation is given in the specification. The equality of the cover (4) shall be protected by the feet of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The above description of the above and other objects, features, advantages and embodiments of the present invention will become more apparent. 2 is a schematic diagram of a single-chip network simulation environment of the present invention; FIG. 3 is a hierarchical diagram of a single-chip network system of the present invention; FIG. 4A is an application model diagram of the present invention; FIG. 4B is a working example diagram; 5 shows the node model of the present invention; Figure 6 shows the adapter model of the present invention.

22 201114224 [Key component symbol description] 11 ............Application 12 ............Single chip network design 13 ........ ....Information Characteristics 14 ......... Single Chip Network Simulator 15 ......... Simulation Report 21 ......... ...Application Specification 22 ............Service Processor Specification 23 ............Service Specification • 24.......... .. Single Chip Network System Exploration Framework 30 ............Work 31 ............Threads 32 ........... Node 33 ............ Adapter 34 ............ Wafer Communication Architecture 35 ............ Entity 36. ...........Program channel 37............Real network channel 38............lowest level physical channel® 41, 42, 43, 44, 45, 46, 47, 48 .. Calculation work 51 ......... Request form 511............ Expansion slot 52 .. .......... core manager 53 ......... event collection and trigger unit 54 ......... work arranger 55 .. ..........nuclear unit 56 ............connection 埠6............Adapter 61 ...... ... manager allocator 62 ......... manager resource 23 201114224

63 ......... Buffer resource allocator 64 ......... Buffer resources 651, 652 ... ... connection 埠 66 .. ..........node 67 ............single chip network element 24

Claims (1)

201114224 VII. Patent application scope: 1. A system exploration platform for a single-chip network, including: a. — Model design: Modeling a single-chip network-centric system, integrated model...hard acid type, and-view Information model; the pass is a plurality of services describing a single chip, and the hard type is a way of describing the generation and processing of the services; (4) software switching b. - system framework setting ff: fresh "transfer" , defining the functional behavior of each level and the information transmission method. The network system provides a performance evaluation method from the top-level to the bottom-level of the hierarchy, and designs with the model. And the design details of the negligible single-chip network can be neglected, simplifying the management of the single-chip network and providing performance evaluation during the design phase. Inter-segmentation 2. The single-chip network described in Patent Item 1 The system explores the design of a bamboo raft (4), and relies on the layers to be turned into a plurality of jobs - the application, and the description of the squat; each _ at least _ the complex; including the work transferred to The node layer, convert S complex; = : (3) at least - core tube ^ to f a computing core and at least - communication core; (4); (d) at and by - d. transit / layer, package ft for the node Layer output; 3 multiple observation groups; bribes to the transfer layer, steam, *· J 25 201114224 for at least one event; the adapter module contains: = to V official distribution, for configuration — (7) The buffer resource allocator, ^ resource and buffer resource are transferred to the chip communication architecture layer and converted into the process 3. The last lag time of the system described in the second application of the patent scope is ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The picture of Gu Chenghong is made into a text form, a number column, and each column represents a job; the blocks include: work as a computing job, a communication job, or a b. work source, Used to describe the source of the work; c. the end of the work, used in communication work, The transmission end point of the communication work; d·^ is used to describe the transmission byte of the communication work or the nose value of the calculation work; % e. trigger feature ' is used to describe the trigger condition of the work; f execution condition And execution characteristics to describe the number of executions of the job or to perform 26