201113889 六、發明說明： 【發明所屬之技術領域】 本發明係有關—種儲存裝置與其資料處理方法，特別是-種非揮發性 儲存裝置與其資料處理方法。 【先前技術】 儲存裝置中的記憶體具有多種類型，其中快閃記憶體為目前市場的主 •之。快閃記憶體為一種非揮發性的記憶體，應用在儲存裝置上，與傳 鲁、摘硬碟比較’具有省電、重量輕、耐震、工作溫度低、操作安靜與存取 速度快等優點，所以快閃記憶體儲存裝置已於部分可攜式電子裝置上逐新 取代硬碟。 快閃記憶體可分為單階記憶胞(Single Level per Cell，SLC。底下簡稱 SLC)與多階記憶胞動(應邮心㈣辦⑽，㈣。底下簡稱獣)兩 • 類。其中’ SLC的快閃記憶體為快閃記憶體陣列(memory cell array)上每一 個記憶胞(me職y cell)可紀錄一個位元㈣的資料。紅記憶體陣列上相關 釀.# .己匕胞以執灯充電與放電程序來紀錄資料，而SLC記憶體陣列上記憶胞 的電位階分布請參縣.！圖。SLC記鐘陣壯記憶就放電後可分為兩 =靖狀態⑽tage state)，在參考龍㈣她哪)左邊的電位階狀 ..態為記憶體陣壯.軌憶胞被放電後，各躲之記憶朗分布.情況，而該 電位㈣通常贿表示邏«料.“1”。在參考碰右邊_位階狀態為 。己體.陣列上的記舰被充電後.，各電位之記触的分树況，而該電位 狀態常用來表示邏輯資料.。...... ... • * · ' · > 另方面MLC的决閃§己憶體為快閃記憶體陣列上每一個記憶胞可記 201113889 錄-位元以上的資料。請參照第2圖，為2位元說記憶體陣列充放電後 陣列上不同電位之記憶胞的分布圖。2位元說記憶體陣列之記憶胞經充 放電後可分為四個電位階狀態，各電位階狀態係分別表示不同的邏輯資 料。四個電位階狀態係利用三個參考電屋w、να與呢來區分。若記憶 胞的電位小於vn ’也就電壓b在最左邊的電位階狀態，該記憶胞表示二 位元的邏輯資料“u”。若記憶胞的電位落在vh與^間，則表示邏輯 貝料1〇。若記憶胞的電位落在Vr2與Vr3間，則表示邏輯資料“⑻”。 •若記憶胞的電位大於Vr3，則表示邏輯資料“⑴”。電位階狀態所表示的邏 輯資料，視非揮發性記憶體各電位階之編碼方式不同，而可能有不同的邏 輯資料表示，為便於說明係舉上述例子作說明。 由第1圖與第2圖所示可知’同樣—個記憶胞中ic每―個記憶胞 所包含的電位PI減鮮，因此各餘離態之_賴差距較狀記憶 ，胞來的接近。如第2圖所示’其中表示邏輯資料“u，，的電位階狀態中最 高的電壓與表示邏輯資料“10”的電位階狀態中最低的電壓，兩個電壓的 籲 祕相近。所以說記憶胞較容易因儲存電荷茂漏㈣㈣，或讀寫作業 干擾(read/write dis_的影響，使得原本的電位階狀態飄移到另一個非目標 .的電位隨態，結果將造成讀取資W發生錯誤位元的情況。此種情況， .•在2位元的MLC快閃i己憶體的資料正確性已具有一定的影響，若在3位元 的說快閃記憶體’其-個記憶胞包含八個電位階狀態，其更容易受到儲 存电荷的本扃與讀寫j乍.業干擾的影響而造成資料錯誤的情形a如苹a圖所 :示.，在記憶體記:憶月包陣列上，蕞左邊電位階狀.態的記憶胞，:最容易受周圍.： 記憶胞充電的影響而造成電位階狀態飄移的情況。， 201113889 為了維持網記憶體輸上輸㈣料的正雜，通f會糊錯誤修正碼 _㈤如CGde，ECC)來保護·，败可確保輸峨的正 確性’但在資料輪㈣，若㈣包含錯誤位元，將需要花時_行錯誤資 料修復的«。也就是說，若由㈣記㈣所出麵f料包含錯誤位 疋批將需要—些嘛執㈣料修復作f，且當败細位元越多， 修復作業所需要的時間也越長，將影響資料讀取的時間。 、，在胤c快閃記憶體隨著製程的微縮以及記憶胞所包含的電位階狀態 增夕的情況下，記憶胞儲存電荷的能力會越來越差，而越容易造成儲存資 料的錯誤，使得所需的ECC修復能力也就越來越高。咖的修復能力越高 其保護每單位__cc位元數也越多。如此，除了如會影響快閃記 〜版的存取賴外’蝴記髓上也需提供較多的冗餘位元來儲存财。 由於快閃記憶體上的冗餘位元通常是用來儲存—些管理資料，所以佔用太 冗餘捕會影_管理#_的儲存帥，崎鮮理設計的彈 【發明内容】 β有u此本發明提出一種儲存裝置與其資料處理方法。利用本發明所 3 、、或方法針對不同的記憶頁採用不同修復能力的錯誤修正碼。 衅是說，對於較易受辭擾而發生錯誤的記憶頁；使祕復能力較高的 ’:曰 < 正馬崎的，對於較不易受到干擾的記憶頁，則使用修復能力車交 低的錯誤修正’。如此’不僅可維持資料的正確性，更可提升資料讀寫上 的處理速度。 . • * . · 其中記 本發明提*—種儲存裝£包含：記憶胞卩翔及職修正模組， 201113889 憶胞陣列包含複數個記憶胞。利用上述的記憶胞劃分為複數個記憶頁，且 至=兩個記憶頁的資料由同一組記憶胞所儲存。至少兩個錯誤修正模組分 別提供不同的錯誤修正能力之複數個錯誤修正碼，給同一組記憶胞上的吃 憶頁之資料。。. ° ★本翻亦提出-種資料處财法，制題存裝置，該騎袈置包含 後數組記憶胞，每一組記憶胞用以紀錄至少兩個記憶頁的資料，該資料處 方去包3下列步驟：接收資料；依據資料被分配儲存的記憶胃，而產生 籲不_保敎被之複數侧郷正碼；將:#料與對應的錯轉正碼健存 至對應的記憶頁。 有關本發明的較佳實酬及其功效，茲配合圖式說明如后。 【實施方式】 曰為使計擾程度不同的記憶頁受到不同程度的資料保魏力，以下將 提U目關貫施例。相關實施例僅為說明本案相關的實施方$，以便了解本 案技術特徵，而不為本案之限制。 * 叫參照第3 ®，細所示_存裝置[實翻之示意圖。本發明所 提出之館存裝置1包含：轉發性記髓3G、第-錯誤修正模組1G及第二 錯誤修正模組20。 月同日移照第4圖，由圖中所示可知，非揮發性記憶體π具有複數個. ’一己隐頁32與複數個第二記憶頁34。其中，每一個第一記憶頁％與每 第-頁34 ’即構成-記憶頁對(paired_page)，也就是該記憶頁對^斤 .' . '' ' 中’記憶-胞陣列上同一組記憶胞上的電位 p 皆 Jr 7 甘., Ά . * .、不 '、中’第一記憶頁32>係為記憶頁對中實體位址較低的記憶頁（或. 201113889 稱最低有效位綠顧，LSB page)，第二雄頁34係為記憶頁對中實體 位址較高的記憶頁（或稱最高有效位元記憶.頁，MSBpage)。 請同時參照第3圖與第4圖，第-錯誤修正模組1G缺於非揮發性記 憶體30 ’依據將儲存至第—記憶頁32的f料產生第—錯誤修正哪cc ^， 然後將該筆資料與第—錯誤修正碼儲(ECC υ傳送至第—記憶頁Μ儲存。第 二錯誤修正模組2G _於轉發性記憶體3〇，依據將儲存至第二記憶頁 34的資料產生第二錯誤修正碼(ECC 2)，然後將該筆資料與第二錯誤修正碼 (ECC 2)傳送至第二記憶頁34儲存。其中，第一錯誤修正碼的修復 能力大於第二錯誤修正碼的修復能力(孤2)。因此，第—錯誤修正碼⑽ 的位元數大於第二錯誤修正碼(ECC2)的位元數。由第4圖也可清楚看出， 健存於第-記« 32的f料對應的ECC丨所佔用的位元數，_存於第二 記憶頁34的資科對應的ECC 2所佔用的位元數來的多。 由先前技術的說明可知，因為相鄰記憶胞電壓差的影響，電位階較低 的記憶胞較容肢到干擾而發生記憶胞之電位階位移的情況，造成資料讀 取時的錯誤。由料_位階所代表的記憶麵不同，故在ecc修 復能力上，本發明針對電位階受影響程度的不同，對記憶胞上相關電位階 所對應的記憶供不同的Ecc修復能力。舉修細，以第2圖的隱c 快閃記憶體㈣，最左相電位離絲稍财料“u，，^舰最容易受 到干擾’而向右位移到隔壁的電位階(邏輯資料“ 1〇，，），所以莫影響的資料為 記憶’頁對(paired-page)中最低有碑位元記憶頁(LSB卿)的資料，·也就是 說，原本該麟輯“Γ，的位元，但在資料讀取時因為記憶胞之電也向右位移 的關係，變成讀出邏輯“〇,爾等。周此，本發明在資料保護的做法， 201113889 習知技麟對每航憶頁皆使_同修復能力的ECC，喊針對不同的記 憶.頁採用不同修復能力的Ecc。 4 * 以上述例子練’由於最低有效位元記‘隐頁的資料較最高有效位元記 憶頁(MSB page)的資料容易受到干擾，而產生資料錯誤的情形。因此，採 用最低有效位的,ECC修魏力大於最高有胁元記师的抑 _能力。藉此’可提高或維持最低有效位元記憶⑽f料正確性，以及 在最高有效位元記憶頁的資料讀寫上提供較快的處理速度。 凊茶照第5A圖為資料寫入—實施之流程圖(可同時參照第3圖）。儲存 裂置1接收外部資料後’若該筆資料經邏輯/實體位址轉換後被分配寫入非 揮發性記㈣3G巾㈣-記憶頁，聰卿諸(亦即分配寫人至第一記憶 頁的資料)傳送至第-錯誤修正模组10，以產生第一錯誤修正碼(ecc ^「 然後再將該筆資料與ECC 1 -起傳送到非揮發性記憶體3〇，寫入指定的第 一記憶頁中。 另-方面’若儲存裝置1接料經邏輯/實體位址轉換後係被分配 寫入非揮發性記憶體30中的第二記憶頁，則將該筆資難即分配寫入至第 二記憶頁的麵傳送至第二錯誤修正模組㈣產生第二錯誤修正碼(虹 2) ’然後再將該筆資料與ECC 2 -起傳送到非揮發性記憶體3〇 ,寫入指定 的第二記憶頁中。 ’ • . . · 請參照第5B圖為黉料讀取-實施之流程圖(可同時參照第3圖)。在資 料讀取時，若欲讀取第-記憶頁6_，係將第—記憶頁中的資料及與該 資料相關的第〆錯誤修正碼(ECCi)讀取出來，並傳送至第一錯誤修正模組 。然後，第-錯誤修正模組難财r錯誤修正婦cc 侧.由第一記： 201113889 憶頁情取出來的資料是財錯誤，若有錯誤便扣修錢，輸出正顧 -資料，若無錯誤則直接輸出由第一記憶頁中讀取出來的資料。 另一方面，若是讀取第二記憶頁的資料 與第二資料相關的第二錯誤修正碼(ECC 2)讀取出來 則將第二記憶頁中的資料及 ，並傳送至第二錯誤修 正模組20。織1二錯雖正馳2G依_二錯雜正碼(败測 由第二記憶頁中讀取出來的請是否有錯誤，若有錯誤便予以修正後，而 輸出正確的㈣，若紐酬直機出由第二記憶頁情取出來的資料。201113889 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a storage device and a data processing method thereof, particularly a non-volatile storage device and a data processing method thereof. [Prior Art] There are many types of memory in a storage device, and the flash memory is the main one in the current market. Flash memory is a kind of non-volatile memory, which is applied to the storage device. Compared with the transmission and the hard disk, it has the advantages of power saving, light weight, shock resistance, low operating temperature, quiet operation and fast access speed. Therefore, the flash memory storage device has replaced the hard disk on some portable electronic devices. Flash memory can be divided into single-level memory cells (Single Level per Cell, SLC, SLC for short) and multi-level memory cells (should be postal (4) (10), (4). The flash memory of the SLC is a bit (four) of each memory cell on the memory cell array. The red memory array is related to the brewing. #. The cells are recorded by the lamp charging and discharging program, and the potential distribution of the memory cells on the SLC memory array is counted. Figure. SLC clocks and strong memory can be divided into two = Jing state (10) tage state), in the reference dragon (four) she is the left side of the potential step.. The state is the memory matrix strong. After the track memory cells are discharged, each hiding The memory is distributed in a circumstance, and the potential (4) usually bribes to indicate the "material." In the reference touch right _ level state is . The body of the array is charged, the sub-tree condition of the touch of each potential, and the potential state is often used to represent the logic data. ...... ... * · ' · > Another aspect of MLC's flash § 己 体 为 快 快 快 快 快 快 快 快 快 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 Please refer to Fig. 2 for the distribution of memory cells of different potentials on the array after charging and discharging the memory array. The 2-bit memory memory cell of the memory array can be divided into four potential level states after charging and discharging, and each potential level state represents different logic materials. The four potential level states are distinguished by three reference electrical houses w, να and . If the potential of the memory cell is less than vn ', and the voltage b is in the leftmost potential level state, the memory cell represents the logical data "u" of the binary. If the potential of the memory cell falls between vh and ^, it means that the logic material is 1〇. If the potential of the memory cell falls between Vr2 and Vr3, it means the logical data "(8)". • If the potential of the memory cell is greater than Vr3, it means the logical data "(1)". The logic data represented by the potential level state depends on the coding mode of each potential level of the non-volatile memory, and may have different logic data representations. For convenience of explanation, the above examples are illustrated. As can be seen from Fig. 1 and Fig. 2, the potential PI contained in each memory cell in the same memory cell is reduced by the potential PI. Therefore, the gap between the remaining states is close to that of the memory. As shown in Fig. 2, the highest voltage in the potential level state of the logical data "u," and the lowest voltage in the potential level state indicating the logical data "10" are similar to each other. Therefore, memory is said. The cell is more likely to be affected by the storage charge (4) (4), or the read/write operation (read/write dis_, so that the original potential level state drifts to another non-target. The potential will cause the reading to occur. In the case of an error bit. In this case, • The correctness of the data in the 2-bit MLC flash has been affected, if the flash memory in the 3-bit is 'the memory' The cell contains eight potential level states, which are more susceptible to the situation of data errors caused by the stored charge and the read and write j乍. Industry interference, as shown in Fig. A, in memory: remembering the moon On the array of packets, the memory cells on the left side of the potential state are: most likely to be affected by the surrounding memory: the effect of memory cell charging causes the potential level to drift., 201113889 In order to maintain the memory of the network memory (four) Miscellaneous, pass f will paste error correction code _ (five) CGde, ECC) to protect ·, defeat can ensure the correctness of the transmission 'but in the data round (four), if (four) contains the wrong bit, it will take time to repair the wrong data «. That is, if by (four) (4) The f material contained in the material contains the wrong bit. The batch will need to be - some (4) material repair is done as f, and the more the bit is lost, the longer the time required for the repair operation will affect the time of data reading. In the case that the flash memory of the 胤c flash memory increases with the miniaturization of the process and the potential level of the memory cell, the memory cell's ability to store charge becomes worse and worse, and the more likely it is to cause errors in the stored data, The required ECC repair ability is getting higher and higher. The higher the repair ability of the coffee, the more the number of __cc bits per unit is protected. In this case, except for the access that will affect the flash code~ version It is also necessary to provide more redundant bits to store money. Since the redundant bits on the flash memory are usually used to store some management data, it is too redundant to capture the shadow_Management__ The storage of handsome, the design of the savvy design [invention content] β has u this hair A storage device and a data processing method thereof are proposed. The error correction code of different repairing ability is used for different memory pages by using the method, method or method of the present invention. That is, for a memory page that is more susceptible to utterance and error occurs; ':曰< Masaki’s, for memory pages that are less susceptible to interference, use the bug fix for repairing the car. 'This can not only maintain the correctness of the data, but also improve the data. The processing speed of reading and writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divided into a plurality of memory pages, and the data to the two memory pages are stored by the same group of memory cells. At least two error correction modulo components provide a plurality of error correction codes for different error correction capabilities, and give information on the memory pages of the same group of memory cells. . ° ★ This book also proposes - a kind of information in the financial method, the title storage device, the riding device includes a rear array of memory cells, each group of memory cells used to record at least two memory pages of the data, the data prescription to package 3 The following steps: receiving the data; according to the data is stored and stored in the memory stomach, and generating the 吁 _ 敎 敎 敎 敎 敎 敎 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; # # # # 健 健 健 健 健 健 健The preferred remuneration and its efficacy with respect to the present invention are as described below with reference to the drawings. [Embodiment] In order to protect the memory pages with different levels of measurement from different degrees of data, the following will be given. The related embodiments are merely illustrative of the implementation of the present invention in order to understand the technical features of the present invention and are not limiting of the present invention. * Refer to the 3rd ®, the detailed description of the storage device. The library device 1 proposed by the present invention includes a forwarder 3G, a first error correction module 1G, and a second error correction module 20. Referring to Figure 4 on the same day of the month, as shown in the figure, the non-volatile memory π has a plurality of 'one hidden pages 32' and a plurality of second memory pages 34. Wherein, each of the first memory page % and each page-page 34' constitutes a pair of memory pages (paired_page), that is, the same group of memories on the memory-cell array in the memory page. The potential p on the cell is Jr 7 甘., Ά . * ., 不 ', 中 'First Memory Page 32> is the memory page with the lower physical address of the memory page alignment (or. 201113889 called the least significant bit green) Gu, LSB page), the second male page 34 is the memory page with the higher physical address of the memory page alignment (or the most significant bit memory. Page, MSBpage). Please refer to FIG. 3 and FIG. 4 at the same time, the first error correction module 1G is missing from the non-volatile memory 30', according to the material to be stored to the first memory page 32, which error correction cc ^, then The data and the first error correction code are stored (ECC υ transferred to the first memory page Μ stored. The second error correction module 2G _ is in the forward memory 3 〇, according to the data to be stored to the second memory page 34 a second error correction code (ECC 2), and then transmitting the data and the second error correction code (ECC 2) to the second memory page 34 for storage, wherein the first error correction code has a repairing capability greater than the second error correction code The repair ability (orphan 2). Therefore, the number of bits of the first error correction code (10) is larger than the number of bits of the second error correction code (ECC2). It can also be clearly seen from Fig. 4 that the health is stored in the first record. The number of bits occupied by the ECC corresponding to the 32 material f is much larger than the number of bits occupied by the ECC 2 corresponding to the belongings of the second memory page 34. It is known from the prior art that The influence of the voltage difference of the adjacent memory cells, the memory cells with lower potentials are more likely to interfere with the memory cells. In the case of potential displacement, the error in data reading is caused. The memory surface represented by the material_level is different, so in the ecc repair ability, the present invention is different for the degree of influence of the potential level, and the relevant potential level on the memory cell. The corresponding memory is for different Ecc repair capabilities. The repair is fine, with the hidden c flash memory (4) in Fig. 2, the leftmost phase potential is slightly more than the material "u,, ^ ship is most susceptible to interference" Right shift to the potential level of the next wall (logical data "1〇,,"), so the data affected by the memory is the lowest data of the paired-page (LSB Qing), that is, It is said that the original series "Γ, the bit, but in the data reading because the memory cell power is also shifted to the right, the read logic becomes "〇, 尔, etc.. This, the invention is in the data protection Practice, 201113889 知知技麟 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Page information is the most significant bit memory page (MSB pa The data of ge) is easily interfered with, and the data is wrong. Therefore, the ECC is more powerful than the highest evaluator, so that the least effective bit can be raised or maintained. Memory (10) f material correctness, and provide faster processing speed on the data reading and writing of the most significant bit memory page. Figure 5A of the tea photo is a data writing-implementation flow chart (refer to Figure 3 at the same time). Storage Split 1 After receiving external data, 'If the data is converted to a non-volatile record (4) 3G towel (4)-memory page after logical/physical address conversion, Cong Qingzhu (that is, assigning the person to the first memory page) The data is transmitted to the first error correction module 10 to generate a first error correction code (ecc ^ " and then the data is transmitted to the non-volatile memory 3 from the ECC 1 and written to the specified A memory page. In another aspect, if the storage device 1 is transferred to the second memory page in the non-volatile memory 30 after being converted by the logical/physical address, the allocation is written to the second memory. The face of the page is transferred to the second error correction module (4) to generate a second error correction code (Rain 2) 'and then the data is transmitted to the non-volatile memory 3〇 from the ECC 2, and the specified second is written. Memory page. </ br> Refer to Figure 5B for a diagram of the reading of the material-implementation (see also Figure 3). When reading the data, if the first memory page 6_ is to be read, the data in the first memory page and the third error correction code (ECCi) related to the data are read out and transmitted to the first error correction. Module. Then, the first-error correction module is difficult to rectify the error correction of the woman cc side. By the first note: 201113889 Recalling the information from the page is a financial error, if there is an error, the repair will be repaired, the output will be taken care of - information, if not The error directly outputs the data read from the first memory page. On the other hand, if the data of the second memory page is read and the second error correction code (ECC 2) associated with the second data is read, the data in the second memory page is transferred to the second error correction mode. Group 20. Weaving 1 2 wrong, although the 2G is _ 2 wrong mixed code (the wrong one is read from the second memory page, please correct it, if it is wrong, then correct it, and output the correct (four), if the reward The information taken out by the second memory page is taken out.
其中’因為第二錯誤修正鄉〇：2)的資料保護位元數較第—錯誤修正 碼(ECC丨)來的少，如此若讀取㈣料含有錯誤位元，域誤位元數在可修 正的範圍内，㈣第二記憶頁的資料讀取速度會較第—記憶頁的資料讀取 速度快。 請參照第6圖為儲存裳置第二實施例之示意圖。於此，儲存裝置i包 含第-編碼單元12、第—解碼料14、第二編碼單元22、第二解碼單元 24以及非揮發性記憶體30。 * 當寫入資料於非揮發性記憶體30時，若資料透過邏輯/實體位址轉換後 被指定寫人_發性記憶體3G中的第__記憶頁，則該筆資料(亦即分配寫入 至第一記憶頁的資料)便傳送至第一編碼私12，第-編碼單元12根據該 筆資料產生第-錯誤修正碼(ECC D，然後該筆簡及第—錯誤修正碼敗C 1)-起被寫入所指定的第一.記憶頁。另—方面’當資料被指定窝入非揮發性 記憶體30中第二記憶頁，卿筆資料(f即分配寫入至第二記憶頁的資料) 便傳送至、第二編，單元22，第二編碼單元22根據餘筆資料產生第二錯誤修 正碼(ECC 2)，然後該筆資料及第二錯誤修正碼(Ε(χ幻一起被寫入所指定的 201113889 第二記憶頁。 .當由非揮發性記憶體30讀取資料時，若讀取非揮發性記憶體％中第 —記憶頁所儲存的資料，卿由第—記憶頁讀取的資料及第—錯誤修正码 抑I)讀取出來並傳送至第—解碼單幻4，由第—解碼單元糊康第二 ••曰i(ECX 1)制由第憶頁所讀取出來的資料是否含有錯誤位 元，縣錯誤職接輸出鱗·，若有錯誤料崎正後輸出正確的資 料。另—方面，當t_W發性記憶體3Q中第：記憶觸健存的資料，則 ^ _=記_取出來哺料及第二錯誤修正碼(咖2)讀取出來並傳送 至弟“ 24，由第二解碼單元叫艮據第二錯誤修正碼败2)谓測 由第^記憶頁所讀取出來的資料妓含有錯誤位元，若無錯誤職接輸出 该筆貧料’若有錯誤辭以修正後輸出正確的資料。 以第2圖所示的mlC非揮發性記憶體為例作說明 階狀態(位置在最左邊、電壓最小_階狀態），其所影響的磁= 域頁(如前述的第-記憶頁)的資料。或者以另一種方式說明，容易受影 s的貝料為.4筆貝料被分配至記憶胞中最低電位階與次低電位階之間表 示不同資料的記憶頁(最低電位階所表示的邏輯資料為“U”，次低電位階所 表不的邏輯爾‘lr，槪間細曝_獅卩她有效位元 記憶頁）。故以第2圖的例子來說，本發明針對最低有效位元記憶頁的資料 提供較完整_輸力，，賴的正雜。崎的，最高有效位 .产己憶頁(如前述的第二記憶頁)的資料不娜有效位元記憶頁-樣容易 Γ擾，因此™Ecc保護位元數少於最低有效位元晴以進行保. ::㈣此娜故物細度，料仙最高有效位. 10. C S] 201113889 元記憶頁的ECC碼(ECC2)位元數較少，因而有較多的冗餘位元可利用，增 .加了非揮發性記憶體在管理與控制上的彈性。 曰 上述介紹單-個記憶胞可儲存2個位元的相關實施例，但本發明不以 此為限。當-個記憶胞可儲存3個位元時，可提供三組不同修復能力的 • ECC。舉例說明…組記憶胞用於紀錄三個記憶頁中的資料時，假設三個 記憶頁中邏輯位址最小的記憶壯的轉係由記憶胞上電顧低的幾個電 位階所标，浙提供修魏力最_咖給三個記顧巾雜位址最小 >的錢頁。_倾力最小的财提供給三個記憶胃巾賴健最大的纪 憶頁’修復能力介於上述兩者之間的虹，可提供給三個記憶頁中邏輯位 置介於上述兩個記憶頁之間的記憶頁。因此，本發明並不限定單一個記憶 胞所能儲存的位元數。 河述之非揮發性記憶體3〇不限於快閃記憶體，亦可為相變化記憶體 (ase Change Memory·’ PCM )、鐵電隨機存取記憶體(FeRAM)、磁阻記憶 體（MRAM)等。 、 卜本發明不限於别述各電位階的編碼方法。如第2圖所示，從最 :邊(电壓最小)的包位階受干擾位移到其相鄰的電位階(如:左邊數來第二個 电位’其所景々響的資料為最低有效位元記憶頁的資料，但若以其他的編 馬方式最谷易X干擾的記憶頁可能為其他的記憶頁。 · 口此，本發明乃針對容易受干擾的記憶頁，也就是資料由記憶胞上之 ’的^個電赠所表示的記憶頁，雜供修彳^能力較強的助以對其資 ..料作保護；；}；目银沾 . .. 的’較不谷易受干擾的記憶頁，也就是資料由記憶胞上之 車又问的幾個電位階所表示的記憶頁，可提供較少位元的ECC作保護，以加 11 201113889 快該記憶頁的讀取速度，並有較多的冗餘位元可供利用。 再者，上述之第一錯誤修正模組10與第二錯誤修疋模組2〇，或是第一 編碼單元12、第-解碼單元14、第二編碼單元22與第二解碼單元％，係 •可設置於一般儲存裝置中的控制器(c〇咖㈣内，但不以此為限。例如，可 .设置於非揮發性記憶體3〇巾’接收由非揮發性記憶體％外部傳來相關記 憶頁的資料’以執行如前述之資料處理方法來保護相關記憶頁的資料。 上述相關錯誤資料偵測及修復單元(第一錯誤修正模組1〇與第二錯誤 鲁修正模組2G，或是第-編碼單元12與第—解碼單元14、第二編碼單元22 與第二解碼單元24)係不限於用硬體或是軟體來實現錯誤侧與修復的功 能。 λ二錯誤資料偵測及修復單元可利用相同或不同的編碼方式來產生錯 誤I正碼，亦即錯誤修正碼可為同一種錯誤修正碼或不同種的錯誤修正 ^ BCH code, Low density parity check, Hamming code, Reed-Solomon _ , Reed Muller code，Binary Golay code，Convolutional code 和 Turbo code至少其中’。而本發明各錯誤修正碼間主要差異為各個實施的錯誤 G正馬的錯誤修正能力不同，分別用於保護同—組記憶胞上不同記憶頁的 資料。 “ · *於吨翻記錄容量越來越大，.本發明也雜制—記憶頁中包含 入址疏修正碼來保護一記憶頁中的資料。例如：.資料容易受干擾的記 .憶頁(如前述最低有效位元記憶頁），可每似位元i的資料提供n .位元的 • · ECC 1、每1.Κ位元組的資料提供η位元的Ecc、或每2Κ.位元組的資料挺 201113889 供η位元的ECC1來保護該記憶頁的資枓；而較不易受干擾的記恢頁(如寸 述最高有效位元記憶頁），亦可每512位元組的資料提供m位元的ecc 2 每1K位元組的資料提供m位元的Ecc 2或每2K位元組的資料提供瓜位 -元的ECC 2來保護該記憶頁的資料，其中^大於m。 雖然本發明的技術内容已經以較佳實施例揭露如上，然其並非用以限 定本發曰月，任何熟習此技藝者，在不脫離本發明之精神所作些許之更動與 潤倚，皆應涵餘本發_範翻’因此本發明之賴觸當視後附之申 鲁 請專利範圍所界定者為準。 【圖式簡單說明】 第1圖：習知技術之SLC記憶胞電位階分布示意圖 第2 ® .習知技術之狐以憶胞電位階分布示意圖 第3圖：儲存裝置第一實施例之示意圖 第4圖：非揮發性記憶體中記憶頁一實施例之示意圖 第5A圖：資料寫入一實施之流程圖 ， .第5B圖：資料讀取一實施之流程圖 第6圖：儲存裝置第二實施例之示意圖 【主要元件符號說明】 1:儲存裝置 . 10 :第一錯誤修正模組 • · 12 :.第·一編碼單元 ..... ' ' 14..:第一解碼單先’ .... ' • · · · · _ 20 ·第二錯誤修正模組 13 201113889 22 :第二編碼早元 24: .第二解碼.單元. 30 :非揮發性記憶體 .32 :第一記憶頁 .34 :第二記憶頁The number of data protection bits of 'because the second error is corrected by the homesickness: 2) is less than that of the first error correction code (ECC丨), so if the read (four) material contains the wrong bit, the number of domain misplaced bits is Within the scope of the correction, (4) the data reading speed of the second memory page will be faster than the data reading speed of the first memory page. Please refer to FIG. 6 for a schematic view of the second embodiment of the storage device. Here, the storage device i includes a first encoding unit 12, a first decoding material 14, a second encoding unit 22, a second decoding unit 24, and a non-volatile memory 30. * When writing data in non-volatile memory 30, if the data is converted to the first __ memory page in the human-generated memory 3G after the logical/physical address conversion, the data (ie, the allocation) The data written to the first memory page is transmitted to the first coded private 12, and the first encoding unit 12 generates a first error correction code (ECC D according to the data, and then the simple and the first error correction code is defeated. 1) - is written to the specified first memory page. On the other hand, when the data is designated to be inserted into the second memory page of the non-volatile memory 30, the data (f is the data allocated to the second memory page) is transmitted to the second block, unit 22, The second encoding unit 22 generates a second error correction code (ECC 2) according to the remainder data, and then the pen data and the second error correction code (Ε (χ 一起 被 被 所 所 所 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 When reading data from the non-volatile memory 30, if the data stored in the first memory page of the non-volatile memory % is read, the data read by the first memory page and the first error correction code I) Read and transmit to the first-decoding single magic 4, the data read by the first page from the first decoding unit, the second page of the second decoding unit (ECX 1), contains the wrong bit, and the county is in the wrong position. Connect the output scale·, if there is a mistake, the raw material will output the correct data. On the other hand, when the t_W hair memory 3Q is the first: the memory touches the data, then ^ _= remember _ take the feed and the second The error correction code (Caf 2) is read out and transmitted to the younger "24. The second decoding unit calls the second error. Miscorrected code failure 2) The data read by the ^ memory page contains the error bit. If there is no error, the output is the poor material. If there is an error, the correct data is output. The mlC non-volatile memory shown in Fig. 2 is used as an example to illustrate the state of the order (position on the leftmost, minimum voltage - order state), and the data of the affected magnetic field page (such as the aforementioned first memory page). Or, in another way, the bedding material that is easily affected by the image is allocated to the memory page indicating the different data between the lowest potential order and the second low potential level in the memory cell (the logic represented by the lowest potential level) The data is "U", the logic of the second low potential level is not the same, the fine exposure is _ _ 卩 卩 her effective bit memory page. Therefore, in the example of Figure 2, the present invention is directed to the least significant bit The information of the meta-memory page provides a more complete _ transmission power, and the reliance of the singularity. Saki, the most effective position. The data of the production of the memory page (such as the aforementioned second memory page) is not a valid bit memory page - easy Harassment, so the number of TMEcc protection bits is less than the least significant bit to protect. :: (d) The fineness of the object, the most effective bit of the material fairy. 10. CS] 201113889 The number of ECC codes (ECC2) of the memory page is small, so there are more redundant bits available, increased and added non-volatile The flexibility of the memory in management and control. 曰 The above describes a single-cell memory cell can store 2 bits of related embodiments, but the invention is not limited thereto. When a memory cell can store 3 bits Three sets of different repair capabilities can be provided. • ECC. For example... When a group of memory cells is used to record data in three memory pages, assume that the memory of the three memory pages with the smallest logical address is from the memory cell. The power meter has a low number of potential levels, and Zhejiang provides the money page for the repair of Wei Li's most _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The least fortune is provided to the three memory stomachs Lai Jian's largest geek page 'Repair ability between the two of the rainbow, can be provided to the three memory pages in the logical position between the above two memory pages Memory page between. Therefore, the present invention is not limited to the number of bits that a single memory can store. He's non-volatile memory 3 is not limited to flash memory, but also can be phase change memory ( PCM ), ferroelectric random access memory (FeRAM), magnetoresistive memory (MRAM) )Wait. The present invention is not limited to the encoding method of each potential step. As shown in Fig. 2, the data from the most: edge (lowest voltage) packet level is disturbed to its adjacent potential level (eg, the second potential from the left side), and the data of the scene is the least significant bit. The memory page of the meta-memory page, but if the other memory page is the most memory page, the memory page may be other memory pages. · The present invention is directed to a memory page that is susceptible to interference, that is, the data is composed of memory cells. The memory page indicated by the 'Electric Gifts' on the 'suggested by the electric gift, the ability to repair the 彳 ^ is more powerful to protect its resources. The memory page of the interference, that is, the memory page represented by several potential steps asked by the car on the memory cell, can provide ECC with less bits for protection, and add 11 201113889 to read the memory page faster. The first error correction module 10 and the second error repair module 2, or the first coding unit 12 and the first decoding unit 14 are available. The second coding unit 22 and the second decoding unit % are controllers that can be set in a general storage device (c〇 (4) Within, but not limited to this. For example, it can be set in a non-volatile memory 3 wipes to receive data from the non-volatile memory % externally transmitted to the relevant memory page to perform the data processing method as described above. To protect the information of the relevant memory page. The above related error data detection and repair unit (the first error correction module 1〇 and the second error correction module 2G, or the first coding unit 12 and the first decoding unit 14, The second encoding unit 22 and the second decoding unit 24) are not limited to implementing the function of error side and repair by hardware or software. The λ2 error data detecting and repairing unit can generate errors by using the same or different encoding methods. I positive code, that is, the error correction code can be the same error correction code or different kinds of error correction ^ BCH code, Low density parity check, Hamming code, Reed-Solomon _ , Reed Muller code, Binary Golay code, Convolutional code and The Turbo code is at least '. The main difference between the error correction codes of the present invention is that the error correction ability of each implementation error G Zhengma is different, and is used to protect the same group memory. The data of different memory pages. " · * The recording capacity is getting larger and larger in tons. The invention is also miscellaneous - the memory page contains the address correction code to protect the data in a memory page. For example: Interfering memory. Recalling pages (such as the least significant bit memory page mentioned above) can provide n bits for each bit-like data. • ECC 1. Each n. Ecc, or every 2 Κ. The data of the byte is quite good for 201113889 for the ectopic ECC1 to protect the memory page; and the less susceptible to the record page (such as the most significant bit memory page) Each 512-bit data can be provided with m-bit ecc 2 per 1K byte data providing m-bit Ecc 2 or per 2K byte data providing melon-element ECC 2 to protect the memory page Information, where ^ is greater than m. Although the technical content of the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art should make some changes and reliance on the spirit of the present invention. Yu Benfa _ Fan Fan' Therefore, the scope of the patent application is subject to the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the distribution of SLC memory cell potentials of the prior art. FIG. 2 is a schematic diagram showing the distribution of the potential level of the fox in the prior art. FIG. 3 is a schematic diagram of the first embodiment of the storage device. 4: Schematic diagram of an embodiment of a memory page in a non-volatile memory. FIG. 5A: Flow chart of data writing, FIG. 5B: Flow chart of data reading, FIG. 6: Storage device second Schematic of the embodiment [Description of main component symbols] 1: Storage device. 10: First error correction module • · 12:. First coding unit..... ' ' 14..: First decoding single first' .... ' • · · · · _ 20 · Second error correction module 13 201113889 22 : Second code early 24: Second decoding unit. 30 : Non-volatile memory .32 : First memory Page.34: Second Memory Page