TW201113664A - Method of clock synchronization and internet system using the same - Google Patents

Abstract

A method of clock synchronization provides for that a slave node gets a synchronization time from a master node to enable time of two nodes to be in synchronization in internet. The steps of the method includes: sending a synchronization message at a default rate from the master node to the slave node with only one-way time transfer; measuring the synchronization time of the master node sending the synchronization message by a master clock of the master node; measuring a first time and a second time of the slave node receiving the synchronization message respectively by two slave clocks of the slave node; setting two frequencies, two slave clocks running at, is unequal by a clock generation circuit; and estimating a maximum likelihood time estimate between the master clock and two slave clocks by said times and two frequencies to yield two precise slave clocks.

Description

201113664 VI. Description of the invention: [Technical field to which the invention pertains] / The invention relates to a method for clock synchronization and a network system using the same, and particularly to a clock applicable to a distributed measurement and control system The method of synchronization. [Prior Art] In recent years, the clock synchronization problem of network nodes has attracted quite a lot of money, so there are many methods for clock synchronization distributed over the network. The most obvious ones include the network time protocol (netw). 〇rk time pr〇t〇c〇1, ΝΤρ) and its simplified version, namely simple network time protocd' (SNTP). This (4) is widely used in local area networks (L ANs) and the Internet (intemet) + but these agreements can only achieve millisecond accuracy. Therefore, the accurate time agreement of IEEE 1588 is currently applied to (10) t^me protocol, PTP) applied to the clock dispersed in the network to solve the accurate time protocol specified by IEEE 1588. The following objectives can be achieved: Accuracy can reach sub-microsec〇 (sub_microsec〇nd); computational complexity and network, minimum requirements, and can be implemented on simple and low-cost devices; ^ management requirements; and use on Ethernet but also for groups Broadcast network t. - The exact time protocol specified by IEEE 1588 is a master-slave synchronization protocol. After the master-slave hierarchy is established, the time_stamped message is exchanged between the master clock and the slave clock to allow the slave clock to measure the master clock time. Finally, all slave clocks at the network node can be synchronized with the master clock. The method of clock synchronization needs to consider the effect of two _: independent clock q 201113664 between the temples 2 ' therefore will generate a clock offset (clock offset), and do offset correction. $ • " stop, on the other hand, Since the clock may use a different frequency port, this will cause a clock skew (ck) ckskew), and a skew correction is required. Figure 1 shows the method of clock synchronization, which is a four-way message. - Virtual Clear has a complex node 1 〇, and i - 朗点 10 has a clock, and nodes 10 transmit or receive time synchronization messages (time synchro-messages) defined by IEEE 1588.

The first message passing process is performed according to the exact time agreement. A master node 10a has a master clock 2〇a (master d〇ck), and the master clock 2〇& measures its initial time and records as: Tw, 〇, and The master node l〇a can transmit a synchronization message and accompany a supplementary message 22 (f〇llow-Up message) to a slave node 1〇b, wherein when the master node 1〇a transmits the synchronization sfl information 21 The master clock 20a measures a time 1 of the transmission of the synchronization message 21 and stores the value of the time τ^·1 using the supplementary sfL information 22. Further, the slave node 10b has a slave clock 20b (slave clock), and its initial time is measured from the clock 2〇b and recorded as 40 'after receiving the synchronization message 21 from the node l〇b', the slave clock 10b of the slave node 10b Measure and store the time 7 when the synchronization message 21 arrives; '1' and calculate the time τ when the synchronization message 21 arrives; 1 and the difference of the time recorded by the supplementary message 22 7^.1 'This difference is the message transmitted to the master node 1〇a The transfer delay caused by the slave node 10b is recorded as the transfer delay time between the master clock 2a and the slave clock 20b. Similarly, in order to correct the propagation delay (propagation delay), the second message passing process is performed. A delay request message is sent from the node l〇b to the master node l〇a ’ and the transmission time measured from the clock 2〇b 201113664 is recorded as r j . Next, after the master node 1Qa receives the request delay message 23, the master clock 20a records the received time as 1 and stores the time r w.i in a response delay message 24 (dday__ message). Then, the master node 10a should respond to the delay message % to the slave node 10b. The slave node 10b calculates the transmission time Γ of the request delay message 23 and the difference of the reception time 1 stored in the response delay message 24, and records the transmission delay time £2 of the master clock 20a and the slave clock 2〇b.

During the two-way message transmission by clock synchronization, the time difference between the master clock 2 and the slave clock 2Gb is calculated, including the offset: the quantity 〇_ and the transmission delay time H. Thus, the correction of the slave clock 2〇b includes the correction of the offset and the correction of the transmission delay time. Therefore, from the clock 20b, the transfer delay times I and ^ of the master node i〇a to the slave node and the slave node to the point l〇a are calculated, and the one-way delay (OWD) is calculated. Equations (1) to (3) are as follows: ' (1) (2) (3)

Dm2s = TsA - Tm.l Ds2m - T mA - Τ' sl £) — ^s2m w 2 Next, and then estimate the master clock and the slave clock to measure the time, there is a -clock bias between the two The shift amount is 0, so the main static ~, and the offset of the clock θ is calculated (4)

~DW ) m2s - Ds2m 2 2 (4) 6 201113664 : This, the clock 2 〇 b can correct its time to be small, and synchronized with the main clock 20a. The partial Θ Θ Θ Θ Θ Θ Θ Θ Θ Θ Θ Θ 大 大 大 大 大 大 k k k k k k k k k k k k k k k k k k k k : : : : : : : : : : : : : : : : : In the asymmetric keying environment, the synchronization 'how to make the square wire of the steel step _ under the assumption of asymmetric pass ==:=::r, can accurately measure the one-way delay of each bond, and more I! ^#(clock Skew)^^ ± m 攸 &&, is a problem solved in the technical field. SUMMARY OF THE INVENTION [1] The purpose is to provide a dual slave clock and adopt a one-way =: ^ = clock synchronization method, which can accurately measure the propagation delay when the transmission ===clock' and can be used for symmetry And the asymmetry keying neutralization advantage can be obtained from the technology disclosed in the present invention, up to the above-mentioned or some or all of the objectives or other purposes, the present invention - a method of clock synchronization to provide - slave nodes on the network The day-to-day synchronization, in which the master node has a master clock, and the slave node eight has at least two slave clocks 'and the slave node is obtained by the master node—the synchronization time, the method includes: making the master node by one-way transmission Every - cycle time... -·· j 7 201113664

Transmitting a synchronization message to the slave node; when the master node transmits the synchronization message, the master clock provides its synchronization time; when the slave node receives the (four) synchronization message, respectively, the synchronization message arrives at one of the first time and a second time = The n circuit sets the ratio of the two solutions operated by the two slave clocks to be unequal, wherein the (four) rate is an integer multiple or fractional multiple of the other; and the master clock and the two slave clocks are estimated by the dead time and the two frequencies. The mistake of the daring can be estimated by the monthly estimate b to correct the two slave clocks. The maximum estimated value of the towel includes the estimated value in the time offset, the estimated delay value of a transmission delay time (4), and the estimated value of a clock skew (cl〇ckskew). The network is a distributed measurement and control system that has a symmetric scale-symmetric link transmission delay environment. In the example, the main point transmits the synchronization message to the slave node, and further includes the main point length 1 for a supplementary message (like 110^_叩1^5§6), which is transmitted along with the synchronization message. To the slave node, the summary message is used to record the synchronization time measured by the master clock of the master node. In one embodiment, the clock generator circuit includes a uniform energy terminal, a flip-flop (Flip-Flop), and two AND gates, and the enable terminal is electrically connected to the two terminals. The two connections and the two gates are electrically connected to the two slave clocks. The flip-flop is a D-type flip-flop. In one embodiment, the clock generator circuit includes a uniform energy end, a phase locked loop (PLL), and two AND gates, and the enable terminal is electrically connected to the two gates and the 'phase sensitive loop> connection is provided. And the two gates are electrically connected to the two slave clocks. A trigger signal is input from the enable terminal of the clock generator circuit to the two slave clocks, and the two slave clocks are simultaneously activated by the trigger of the trigger signal, so that the two slave clocks have the same one time offset. 201113664 A clock synchronization network system of another embodiment of the present invention includes a slave node and a master point for one or a portion or all of the above or other purposes. The slave point includes a first slave clock, a second slave clock, and a clock generator, wherein the first slave clock and the second slave clock are electrically connected to the clock generator circuit, respectively, and the clock generator circuit is used to adjust the first slave The ratio between clock rates is not one. The master node provides - the same == the same step message is unidirectionally transmitted to the slave node, wherein when the slave node receives the synchronization ❿ and the trigger signal 'trigger signal' simultaneously enables the second number r, the frequency of the clock is the second slave Embodiments of the present invention are capable of achieving a more precise clock than sub-microseconds. Butterfly clock skew is achieved to achieve accurate synchronization when low-speed transmission, not only can reduce the symmetrical link delivery environment. In order to apply to non-embodiment ==: In the detailed description of the preferred embodiment, the directional term mentioned in the following paragraphs can be cleared, for example: up, down, Γ, 刖 or after, only It is a reference to the additional drawing work term is used to explain and _ to the present invention. ° ° m 'Use the name of the chain in the environment of 'Co-::: Two::: The method of clock synchronization in the side of the message ・ Calculate its offset 201113664 Passing the paste (four) p butterfly Gn dei (four) will cause no , '' /, s, difference' take _ two assumptions from the clock-wise symmetric link. According to FIG. 2, the clock synchronization method of the present invention adopts a schematic diagram in which a clock is transmitted in one main direction. In particular, the method of the present invention can obtain a plurality of equations by means of one-way transmission of signals, and the parameters of the unknown and complex numbers are unknown, and thus the offset of the clock (dGMset), J-delay (four) (four)-ddays) And CM skew to get an accurate synchronous clock. There are multiple nodes in the road, and each node is used to transmit each other and receive time synchronization messages (time face 〇 - job poem 1 is decentralized quantity control (10) system, and __ symmetric link transmission delay The environment of "1" is the main node, the point pool, the receiver is two, that is, 1% 'and the main node has a master clock 20a (master dock) 'from The node hall has a first slave clock and a second slave clock, where &z represents the amount when the ith sync message is transmitted, and the first slave clock and The time measured by the second slave clock when the i-th sync message is received. — The one-way message transmission is performed multiple times according to the accurate time protocol. The master node pool ^| 3i (synchronization message) is dedicated to supplement the delta of interest 32 ( F〇ll〇w-up message) to the slave node l〇b 'where the master clock 1〇a transmits the synchronization message w when the master clock is applied, and the synchronization time of the i-th sync message 31 is transmitted, and the supplement讯 w32 stores the synchronization time & ζ· value for the heart, in addition, from the festival After 31, from the first time from "Γ · intestinal receives the first synchronization message nodes move Shu

• * J 201113664 The clock survey and the second slave clock 3〇b respectively (four) step message 31 to the time is I.Z· and the second time heart/. At the rth time, the synchronization time 仏(10) recorded by the first time supplementary message 32 at which the synchronization message 31 arrives is calculated as the time offset of the master clock ^ slave clock 20b, and the second time ^= interest 32 record When synchronizing, the difference is the main clock.

== Turn off. And separately calculate the synchronization message MS, W and the younger one time T; 2 z and the main clock 2〇

The synchronization of the same message J, W,, the difference 'this difference is the main node coffee delivery I to the transfer delay caused by (4) survey, recorded as the main clock two slave clock survey, 30b transfer delay time & And multiple times of one-way message transmission by clock synchronization, the slave clock or master clock applies "delay _ different", its + contains time offset, clock skew and transfer secret τ two t. Thus, the first - slave Correction of the clock and the second slave clock 30b offset, clock skew and transfer delay time. The port is referred to as a circuit diagram of the embodiment of the present invention. Assume = slave clock 3% The frequency of operation is converted and normalized by the Z frequency of the main clock, where ε represents the frequency difference between the main clock and the second slave clock, that is, the clock skew. The circuit of Figure 3 is a clock generator circuit. The clock generates a 〇a such as a frequency divider, the clock generator is electrically connected to the first slave clock 2〇b卩 and the second slave clock, and the generating circuit 100a includes two gates 40, 41 (andgate), - D-type inverter 50a (D-type Fiip_F1〇p), an input terminal 51 and the same can be done "201113664 60" and the 40 and 41 can be used as switches and respectively have two input terminals 40a , 40b and 41a, 41b and an output terminal 4〇c, 41c, D type positive and negative 50a has a clock (Clockrate 'i.e. the clock frequency) input terminal Ck, a data input terminal D and a temporary data output terminal QB.

The electrical connection relationship of the clock generator circuit is as follows: the input terminal 51 is p-connected to the clock input terminal c of the D-type flip-flop 5〇a and the input of the room 41 lb 4lb 'D-type flip-flop 5〇 a data input terminal D electrically connected to the basin temporary storage data output terminal QB and the input terminal of the gate 4; and the enable terminal 6〇, the electrical connection and the input terminal of the gate 40 and the input of the gate 41 41a, and the output terminal 40c of the gate 4 is f-connected to the second slave clock lion, and the 4c input 41c is electrically connected to the first slave clock 2 . In the present embodiment, the frequency of the first slave clock 2〇b is called “the first frequency and the frequency of the second slave clock 3〇b is called the “second frequency”. The clock generator circuit a slave first slave clock survey operates at a ratio of the first frequency to the second slave clock clock, so the second slave is known from the above assumptions. . Second, the clock generator circuit is divided into two from the first cycle of the day and the conversion; therefore, the second frequency of the second-frequency two-T operation is the first frequency of the first slave clock 2〇b The 'first' is first operated from the clock survey - the first input t and input by the input 51. In addition, the enable terminal 60 triggers the signal to simultaneously enable the first-slave clock to be full, and the two slave clocks start simultaneously. Therefore, the two records are θ, Γ b, and 30b have the same time offset. The time offset is referred to as FIG. 3B as another embodiment of the present invention. The clock generator circuit 201113664 is 100b. The clock generator circuit 丨00b includes two gates 40 and 41, a phase-locked loop 50b (PLL) and a uniform energy terminal 60, and the gates 40 and 41 can function as switches and have two inputs respectively. The ends 40a, 40b and 41a, 41b and an output terminal 4〇c, 41c' and the phase locking loop 5〇b have an input terminal In and a wheel terminal utut. The input terminal 5 is electrically connected to the input terminal In of the phase lock loop 50b and the input terminal 41b of the AND gate 41; the output terminal 〇ut of the phase lock loop 50b is electrically connected and the input terminal 4〇a of the gate 4〇; The input terminal 4〇b of the terminal 60 and the input terminal of the gate 41 and the input terminal of the gate 41 are M minutes, where V and slave are integers. Therefore, the clock 30b is shipped __ policy-&, therefore, if the second slave is assumed

The output terminal 41c of the gate 40 is electrically connected to the second slave clock 30b, and the output terminal 41c of the gate 41 is electrically connected to the first slave clock 2〇b. In this embodiment, the clock generator circuit legs set the ratio of the first frequency of the first-slave clock 2〇b to the second frequency of the second slave clock.

> Two slave clocks 20b and the master clock 2〇a "the second slave clock 20b receives the ith sync message transmitted by the master clock 2〇a 201113664, because of the clock skew relationship, the second slave clock 20b Similarly to the time difference generated between the master clock 20a, the time relationship between the first slave clock and the master clock is as shown in FIG. Therefore, after the ith synchronization message is received by the first slave clock and the second slave clock, the clock generator circuit 1 of FIG. 3A is assumed to be the second one of the clocks 30b. The second frequency is illusory, and the first two frequencies from the clock-operated - the first frequency can get the following two equations (3)

Tsl.i = 2^(J+ ^(Tm.i+Dm2J+ φχΑ (5) TS2-i -(7+ £')*(Tm.i+Dm2s)+ Θλ- φ2ι (6) where Α, / and yd Representing the first-time and the second error of the first clock in the specific period and the second slave clock: Qing rs). The handle of the tilt-error heart-function of the Takasaki machine variable α2. The 岣 value is because the second frequency of the second slave clock is the second of the first slave clock, and the second ε of the second slave clock is operated with the first-cycle of the first clock. Twice, because the positive edge of the second slave clock ^ second = period is the first of the first-slave clock - the second of the period of the second clock from the second error of the clock ~ has the value of the first - slave clock 仏Use Equation (6) minus the wire type (7) to get the clock ride (4) The relationship between the error pbz· and the second error: (7+ £)^(Tm.HDm2s) = TsX.i-Ts2.i-¥ φ2^ ^ Insert equation (7) into equation (6): 201113664 (8) ^~2*Ts2.i - Ts\.i + φνι. 2* φ2.\ Because the first-error~• and the second error~ are Gaussian random variables, so 5 hearts ~· is also a Gaussian random variable, which is connected to the slave clock. After receiving the side-step message, the time is reversed: the most second: the measured value (maximum iikelih〇〇d) can be calculated using equation (8): this Θ

N /=1 /=1 (9) Using equation (7), transfer the master clock to 帛i programs minus the master clock to transmit the Wth sync message ^=jin = column equation: the remaining $ ' can serve r; + r ^;>rri2,,rs,r/.7;; +(^2·ΐ- φ 1.(1-1))- (φ\Λ- φν(ΐ.η\ (10) ... because (4)/ π(four)cut_ is also a Gaussian random variable, and equation (10) yields the maximum possible estimate of a clock skew ε: ε

Zt2 ^Λ ~ii£li))^f=2 (Ts2 d - ts2 .〇· -1}) ΣΝ -------- yJ /=2 ~ Tm.(/ - 1)) ~ 1 = Ffi usL· l) - (r..nt\ .n ^~TmA) A 1 (11: Possible =: can be derived from equation (7) - transfer delay time " m2s

D (12) In the embodiment, the above equation can also be written by the relationship of the clock generation r r^- 15 201113664 circuit 100b of Fig. 3B. Therefore, the present invention utilizes a dual slave clock to comply with the IEEE i588 specification to achieve better performance than an accurate time protocol, and utilizes the relationship between the frequency of the two slave clocks as a multiple of a shark or a fractional multiple to propose a time offset. The maximum possible estimate of the amount 0, the clock skew ε, and the transfer delay time 4 allows the two tender clocks 2〇b, 3〇b to correct their time, synchronize with the master clock, and also extend the transmission of the synchronization message. Interval, which in turn reduces the need for transport and network bandwidth. Kaili

In addition, the invention can be applied to the environment of symmetric and asymmetric link transmission delay, and the Wei of the non-dragon link transmission delay is, for example, a decentralized measurement fresh system, and the one-way delay of the communication link is reached (〇ne_way _, speculation) Therefore, it is possible to achieve better control of the instant control and measurement system, not to reduce the amount of calculation, and to reduce the demand of the network thief; low-cost device 'and use for Ethernet or group broadcast' (multicast) in the network. 'The goods mentioned above are only the preferred embodiment of the present invention, when it can not be implemented == month, that is, according to the material of the invention patent application scope Equivalent changes and modifications are still within the scope of the present invention. The invention is not limited to the scope of the present invention. Brief description of the method] The method of the __clock synchronization method presents a two-way message transmission 201113664 The method of the method is a schematic diagram of the method of unidirectional transmission using a dual slave clock. Figure 3A is the implementation of the present invention. Electrical circuit schematic of the embodiment of Figure 3B, the system of the present invention, although a further embodiment shown in FIG. 4 'from between the lines when the master clock and the symbol clock DESCRIPTION The main components of the schematic Intention; and

Master node 10a slave node 10b

Master clock 20a (first) slave clock 20b slave one slave clock 30b sync message 21 supplemental message 22 request delay message 23 response delay message 24 clock generator circuit l〇〇a, l〇〇b two and gate 40, 41 type D Positive and negative device 50a phase lock circuit 5〇b wheel input terminal 51 enable terminal 60 input terminal 40a, 40b, 41a, 41b 201113664 output terminal 40c, 41c (main clock) initial time (from the clock) initial time

(Time at which the master node transmits the i-th sync message synchronization message) rw.z· (the i-th sync message arrives at the slave node) 7;./, Lz: 7; 2./ (Transfer request delay message from the node) ) Transmission time Γ J (request delay message arrives at the master node) Receive time is wide; Transfer delay time D m2s, Ds2m 〇 Offset β One-way delay clock skew £ Clock input Ck Data input D Temporary data output End QB first error %, / second error, / 18

Claims (1)

201113664 VII. Patent application scope: A method for synchronizing clocks, providing - on the network - synchronizing the slave node with a point clock - the master node has a master clock, and at this time ^ has at least two slave clocks, and the The slave node obtains the synchronization time by the master node, and the method includes: ^ the slave node transmits the synchronization message to the node by means of one-way transmission When the (10) forwards the synchronization message, when the clock provides the synchronization, when the (four) point is connected to the (four) step message, the ^ slave clock is separately measured, and the second synchronization H arrives - the first time and the second Using the -clock generation |g circuit to set the two frequencies at which the two slave clocks are operated such that the two frequencies are not equal; and by the synchronization time, the first time, the second time, and the two frequencies = operation _, estimating the maximum possible estimate of the error between the master clock and the two slave clocks to correct the two slave clocks. The method of clock synchronization as described in claim i, wherein the main point transmits a synchronization message to the slave node, and further includes: · Lang.. - know: for a supplement of 5 holes ( The ow_Up message is transmitted to the point of attachment with the synchronization condition. The supplementary message is used to record the synchronization time measured by the master clock of the master node. 3. The method of clock synchronization as described in claim 1, wherein the clock generator circuit comprises an enable terminal, a flip-flop (Flip F1〇p), and two gates (and gates), and The two terminals are electrically connected to the two gates. The flip-flop device 201113664 is connected to the two gates, and the two gates are electrically connected to the two slave clocks. 4. The method of clock synchronization as described in claim 3, wherein the flip-flop is a D-type flip-flop. 5. The method of clock synchronization as described in claim 1 of the patent application, wherein the generation of the subtraction includes - enabling, - locking phase (PLL) and two gates And gate, and the enable terminal is electrically connected to the The two gates are connected to the two gates, and the two slaves are electrically connected to the two slave clocks. 6. The method of clock synchronization as described in claim 3 or 5 of the patent application, further includes: the enabler of the circuit by the tear seam-triggering to the two slave clocks; and two two; The triggering of the delta fine signal is turned off, so that the two slave clocks have the same one time offset. 7. The method of clock synchronization as described in claim i, wherein the most probable estimate comprises an estimate of the time offset, a transfer delay time = pa_〇n delay, or Estimation of a clock bias _ 〇 洗 ( (4) ^ As for the method of applying the steel step as described in the patent Gu Diyu, the middle road system is a decentralized measurement and control system. 4 11 __ The method of clock synchronization described in item 1, the 1 忖 network has a symmetric or an asymmetric link transfer delay environment. ..., week: as the t-clock described in the application for patent scope, the t-clock is operated as its other integer multiple = several times Γ: · 20 201113664 A clock-synchronized network system, including : a slave node 'includes a first slave generator circuit, j: so that the first clock and a clock are connected to the clock Μ 2 the first clock is electrically connected to the second slave clock Recovering the state circuit in the day-to-day seal, at which time the ratio between the frequency of the first and the frequency and the frequency of the second slave clock is not one; Node, providing - synchronizing messages to the slave node, the step message is passed early When the slave node receives the synchronization message, the trigger signal simultaneously enables the first slave clock to be synchronized with the second clock system as described in claim n. , Zhong Zhonghao n circuit includes - Wei end, - forward and reverse device and two and closed: the terminal is electrically connected to the two and the question, the flip-flop is electrically connected to the two gates, and the two two gates and the gates are connected The two slave clocks. 13: If the clock synchronization network system described in Item 12 is applied, the shai positive and negative device is a d-type flip-flop. H. The clock clock generating circuit as described in the U of the patent application scope includes: - the terminal is connected to the two gates, and the circuit is electrically connected to the two gates. The two gates are connected, and the two slave gates are connected to the two slave clocks. 15. The network system for clock synchronization as described in claim 2, wherein the frequency of the first-slave clock is a multiple of an integer multiple of the frequency of the second slave clock.