201112391 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種靜電放電(Electro-Static Discharge; ESD；H$ 護結構，特別是關於一種用於全金屬矽化物輸出入ESD保護的鎮 流結構。 【先前技術】 在互補金氧半(CMOS)積體電路(1C)中’隨著量產製程的演 進，元件的尺寸已縮減到深次微米(deep-submicron)的階段，以增 進1C的性能及運算速度，以及降低每顆晶片的製造成本。但隨著 元件尺寸的縮減，卻出現一些可靠度的問題。 在次微米技術中’為了克服熱載子(hot-carrier)效應而發展出 輕掺雜汲極(Lightly-Doped Drain; LDD)製程與結構；為了降低 CMOS的源極與及極的寄生片電阻(sheetresistance)Rs與Rd，而發 展出金屬矽化物(silicide)製程；為了降低CMOS的閘極的寄生片 電阻Rg而發展出金屬多晶石夕化物(p〇lyCide)製程；在更先進的製 程中把金屬梦化物與金屬多晶砍化物一起製造，而發展出自動對 準金屬矽化物(self-aligned silicide; salicide)製程。 然而，前述製程以及縮小後的元件尺寸，皆導致〇^〇81(：(例 如NMOS和PMOS)對ESD的保護能力大幅降低。在面對外界環 境中產生的靜電時，這些CMOS 1C因ESD而損傷的情形更嚴重。 舉例來說’當一個常用的輸出缓衝級(0utput buffer)元件的通道寬 度(channel width)固定在300微米(μιη)，用2μηι的傳統技術製造的 NMOS可耐壓超過3千伏特，但用1μηι製程加上LDD技術來製 201112391 造的元件，其ES㈣壓度不到2千伏特，肖一製程加上咖 及自動對準金屬石夕化物技術製造的元件，其ESD财壓度僅約（千 伏特而已。在元件尺寸不變的情況下，不同的製程使得元件的 ESD 呆護能力大幅地滑落’許多深次微# cm〇s m都面臨 這個棘手的問題。 ’在自動對準金屬石夕化物製程中，由於加上金屬石夕化物的 擴散區域的片電阻值很低，導致汲極區域的鎮流電阻不夠，因此 自動對準金屬雜物製程對ESD保護電路造成嚴重的威脅，又因 為鎮流電阻太小，造成ESD的超高電壓直接落在汲極接近閘極 處’因而造成閘極乳化層抽傷或丨及極和源極之間的短路。為了在 金屬矽化物CMOS製程裡改進MOSFET的ESD強勃度 (robustness)，現有最直接的解決方式是多加一道自動對準金屬石夕 化物阻隔光罩(Salicide Blocking; SB)，此技術透過避免ESD保護 元件的區域形成金屬石夕化物而改善ESD強勃度。在CMOS製程 中’二氧化石夕形成金屬石夕化物的溫度比矽高，因此可在金屬矽化 φ 物的沉澱之前透過在規劃區域上放置氧化物當作阻隔光罩。該氧 化物把矽及金屬隔開，避免金屬在之後的退火過程中矽化。由於 封鎖了金屬的矽化且恰當增加和閘極間隔的接觸，MOSFET的 ESD強韌度因鎮流電阻的增加而改善。但SB技術會增加一道光 罩及相關製程步驟，造成製造成本增加。故其他使用高鎮流電阻 (ballast resistance)的鎮流技術就被提出來。 由於ESD是一種大電流的現象，電流的聚集將對ESD保護元 件造成衝擊，而增加ESD鎮流元件(MOSFET)的鎮流電阻可以使 ESD電流路徑深入基板(substrate)以改善ESD強韌度，再者，不同 201112391 距離的接地保護環(groundedguardring)造成不對稱的基板電阻，使 得多指(multi-fmger)NMOS元件承受不均分的導通，由於ESD保 護元件上的電壓差VdrQp為ESD電流IESD乘上導通電阻心。201112391 VI. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge (Electro-Static Discharge; ESD; H$ protection structure, in particular to a ballast for full metal telluride output into ESD protection [Prior Art] In the complementary MOS (CMOS) integrated circuit (1C) 'As the mass production process evolves, the size of the component has been reduced to the deep-submicron stage to enhance 1C. Performance and speed of operation, as well as reducing the manufacturing cost per wafer. However, as component size shrinks, there are some reliability issues. In sub-micron technology, 'to overcome the hot-carrier effect Lightly-Doped Drain (LDD) process and structure; developed a metal silicide process in order to reduce the source and polarity parasitic sheet resistance Rs and Rd of CMOS; The metal polycrystalline phosphatide (p〇lyCide) process is developed by reducing the parasitic sheet resistance Rg of the gate of the CMOS; in the more advanced process, the metal dream compound is fabricated together with the metal polycrystalline cleavage compound, and A self-aligned silicide (salicide) process is exhibited. However, the above-mentioned process and the reduced component size result in a significant reduction in the ESD protection of 〇^〇81 (: (for example, NMOS and PMOS). In the face of static electricity generated in the external environment, these CMOS 1C damage is more serious due to ESD. For example, 'When a commonly used output buffer level (0utput buffer) component's channel width is fixed at 300 micron (μιη), NMOS can be made with a conventional technology of 2μηι with a withstand voltage of more than 3 kV, but with the 1μηι process plus LDD technology to make the components made by 201112391, the ES (four) pressure is less than 2 kV, Xiao Yi process With the addition of coffee and components that are automatically aligned with metal-lithium technology, the ESD financial pressure is only about a thousand kilovolts. With the same component size, different processes make the component's ESD retention ability drop dramatically. 'Many deep sub-micro# cm〇sm are faced with this thorny problem. 'In the process of automatic alignment of metallization, the sheet resistance of the diffusion region of the metal-lithium compound is very low. The ballast resistance in the bungee region is not enough, so the automatic alignment of the metal debris process poses a serious threat to the ESD protection circuit, and because the ballast resistance is too small, the ESD ultra-high voltage directly falls on the bungee close to the gate. 'There is a short circuit between the gate emulsification layer and the 极 and the source and the source. In order to improve the ESD robustness of the MOSFET in the metal bismuth CMOS process, the most straightforward solution is to add one more Automated alignment of the Metallic Blocking Mask (SB), which improves ESD robustness by avoiding the formation of metalloids in the area of the ESD protection element. In the CMOS process, the temperature of the metal oxide compound is higher than that of the tantalum oxide, so that the oxide can be placed on the planned area as a barrier mask before the precipitation of the metal telluride. The oxide separates the niobium from the metal to prevent the metal from deuterating during subsequent annealing. The ESD strength of the MOSFET is improved by the increase in ballast resistance due to the blockage of the metal and the proper increase in contact with the gate spacing. However, SB technology will add a reticle and related process steps, resulting in increased manufacturing costs. Therefore, other ballast techniques using high ballast resistance have been proposed. Since ESD is a phenomenon of high current, the concentration of current will impact the ESD protection components, and increasing the ballast resistance of the ESD ballast element (MOSFET) can make the ESD current path deep into the substrate to improve the ESD strength. Furthermore, grounded guard rings of different 201112391 distances cause asymmetric substrate resistance, which makes multi-fmger NMOS components with uneven conduction, due to the voltage difference VSDQp on the ESD protection component is ESD current IESD Multiply the on-resistance.
Vdrop - (IeSD X R〇n) 式 1 藉由將鎮流電阻Rballast串聯導通電阻，可以增加壓差Vdrop - (IeSD X R〇n) Equation 1 Increase the differential pressure by connecting the ballast resistor Rballast in series with the resistor
Vdrop_ (IeSD X R〇n’） 式 2 其中Ron’ = (Ron + Rballast)。如圖1所示，提升鎮流電阻Rbaiiast使第 二崩潰電壓(νβ)增加到高於雙極性觸發電壓(Vti)後，植基於驟回的 鲁 （snaPback-based)ESD保護元件，例如多指N]y[〇s，便可以在esd 轟擊下均勻地觸發，換言之，增加鎮流電阻可以有效改善ESD強 韌度。 圖2纟會示一種習知增加鎮流電阻的方法，nm〇s的源極、閘 極和>及極都設置在基板18上，其汲極被分為第一區域1〇以及第 二區域14’二者之間以絕緣體12隔開，第一區域1〇連接接合墊(圖 中未示），由接合墊經由第一區域1〇進入的電流必須穿過 • N型井(N-Well)16，再經由第二區域14到達閘極通道。若以等效 電路來看，可視為在NMOS的汲極接上電阻RN Well後再連接接合 墊，因而提升NMOS的ESD強韌度型井16為具有高片電阻 值的低掺雜區域，藉由調整N型井16的深度L及寬度w可決定 -電阻的阻值。絕緣體12可以是場氧化物(Field 〇xide; F〇x) 或淺溝渠隔離(Shallow Treneh IsoMoi^ SO)。 圖3繪示另一種習知增加鎮流電阻的方法，在汲極的第一區 域10和第二區域14之間設置空(dummy)閘極2〇，以強迫電流流 經N型井16。 201112391 圖2及圖3的方法不需要增加光罩即可實施，但僅適用於 NMOS ’這是因為PMOS的汲極和n型井之間會產生寄生二極體 D1和D2 ’如圖.4所示，寄生二極體D1和〇2使得電流無法由N 型井26流入汲極的第一區域22和第二區域24。 圖5繪示使用多晶矽後段鎮流(p〇ly Back_End Ballast; BEB)技 術的NMOS的佈局(layout)上視圖和侧視圖，此BEB技術可應用 在PMOS和NMOS上。在NM〇s的兩側設置絕緣體28和30，並 在絕緣體28及30上設置導體32和34，使電流經由節點1、2、3 ® 後連接到NMOS的汲極，再經由閘極通道進入源極，再經由節點 4、5和6。此技術是藉由拉長電流路徑達到增加鎮流電阻的目的， 因此可以同時適用於NMOS和PMOS，相關技術可參考美國專利 號 6,046,087。 另一種增加鎮流電阻的習知技術稱做主動區域切割 (Active-Area-Segmentation; AAS)。而美國專利號 7,〇〇5,708 便揭露 此相關技術，如圖6所示，此技術應用於全金屬矽化物 Φ silicided)ESD保護MOSFET時，能比BEB技術更進一步減少佈局 面積，藉由切割汲極和源極掺雜的擴散面積，使汲極到源極的每 一擴散區域的ESD電流路徑的電阻率增大。 圖7為習知AAS鎮流技術的另一種方式，也適用於全金屬石夕 • 化物MOSFET。這種方法利用區域擴散及特殊電路佈局，使汲極 的電流延者非直線路徑36流往源極，藉由拉長電流路徑達到增加 鎮流電阻的目的。也可以使用STI或F〇x將擴散區域分隔開來， 達成AAS的技術效果。 美國專利號7,009,252另揭露一種浮動多晶石夕陣列(Fi〇aung 201112391Vdrop_ (IeSD X R〇n') where Ron' = (Ron + Rballast). As shown in Figure 1, the boosting ballast resistance, Rbaiiast, increases the second breakdown voltage (νβ) above the bipolar trigger voltage (Vti), based on a snapback snaPback-based ESD protection component, such as multi-finger N]y[〇s, it can be triggered evenly under esd bombardment. In other words, increasing the ballast resistance can effectively improve the ESD toughness. Figure 2A shows a conventional method of increasing the ballast resistance. The source, gate, and > and the poles of nm〇s are disposed on the substrate 18, and the drain is divided into the first region 1 and the second. The region 14' is separated by an insulator 12, and the first region 1 is connected to a bonding pad (not shown), and the current entering by the bonding pad via the first region 1 must pass through the N-type well (N- Well) 16 then reaches the gate channel via the second region 14. If the equivalent circuit is used, it can be considered that the NMOS anode is connected to the resistor RN Well and then the bonding pad is connected. Therefore, the NMOS ESD robustness well 16 is raised to be a low-doped region having a high sheet resistance value. The resistance of the resistor can be determined by adjusting the depth L and the width w of the N-well 16. The insulator 12 can be a field oxide (Field 〇xide; F〇x) or a shallow trench isolation (Shallow Treneh IsoMoi^ SO). 3 illustrates another conventional method of increasing ballast resistance by providing a dummy gate 2〇 between the first region 10 and the second region 14 of the drain to force current through the N-well 16. 201112391 The method of Figure 2 and Figure 3 can be implemented without adding a mask, but only for NMOS 'This is because parasitic diodes D1 and D2 are generated between the PMOS drain and the n-well. Figure 4. As shown, the parasitic diodes D1 and 〇2 prevent current from flowing from the N-well 26 into the first region 22 and the second region 24 of the drain. Figure 5 illustrates a top view and a side view of an NMOS layout using a polysilicon back-end ballast (BEB) technique that can be applied to PMOS and NMOS. Insulators 28 and 30 are disposed on both sides of the NM〇s, and conductors 32 and 34 are disposed on the insulators 28 and 30, so that current is connected to the drain of the NMOS via the nodes 1, 2, 3 ® and then through the gate channel. The source is then passed through nodes 4, 5 and 6. This technique achieves the purpose of increasing the ballast resistance by extending the current path, and thus can be applied to both NMOS and PMOS. For related art, reference is made to U.S. Patent No. 6,046,087. Another conventional technique for increasing ballast resistance is called Active-Area-Segmentation (AAS). U.S. Patent No. 7, 〇〇5,708 discloses the related art. As shown in Fig. 6, this technique can be applied to the all-metal telluride Φ silicided ESD protection MOSFET to further reduce the layout area by the BEB technology. The diffusion area of the drain and source doping increases the resistivity of the ESD current path for each drain region from the drain to the source. Figure 7 is another way of conventional AAS ballast technology, also applicable to all-metal cermet MOSFETs. This method utilizes region diffusion and special circuit layout to cause the drain current non-linear path 36 to flow to the source, thereby increasing the ballast resistance by extending the current path. It is also possible to use STI or F〇x to separate the diffusion areas to achieve the technical effect of AAS. U.S. Patent No. 7,009,252 discloses a floating polycrystalline stone array (Fi〇aung 201112391)
Poly Array; FPA)技術。圖8便是使用FPA技術的NMOS的佈局上 視圖和側視圖，利用交錯的多晶矽陣列38分隔擴散區域以增加鎮 流電阻值。 在CMOS製程中，接點電阻(contact resistance)提供另一種應 用於全金屬矽化物ESD保護MOSFET的鎮流技術。如圖9所示， 以40處做為接合墊，此接點鎮流(ConTact Ballast; CTB)技術從接 點42、44、46處及擴散區域48強加鎮流電阻於全金屬矽化物 NMOS上。具CTB技術的NMOS已有報告指出比SB技術的 ® NMOS具有更高的ESD強韌度。 雖然已有許多鎮流技術可適用於全金屬石夕化物I/O驅動器，但 能做到對整體晶片的ESD保護技彳标依舊少見。為了同時能縮小電 路面積及提高ESD強韌度，習知的COMS晶片中常採用具有自我 保護功能的I/O驅動器，其並無並聯額外的ESD保護元件。因此， 使用最低ESD保護要求的2-kV PS模式ESD在I/O接合塾上做 的全晶片的ESD測試時，其鎮流電阻的不足使得esd電流聚集於 • 矽的表面，造成全金屬矽化物NMOS的崩潰。 因此，一種用於輸出入接合墊的ESD保護電路，具有保護整 體晶片的全金屬石夕化物I/O驅動器的ESD鎮流電阻乃為所冀。 【發明内容】 本發明之目的之一，在於提出一種用於輸出入接合墊的esd 保護電路。 根據本發明，一種用於全金屬矽化物輸出入ESD保護的鎮流 結構包括：接合墊；基板；設置在該基板上的NMOS包括：第一 201112391 N型井’其中具有第-區域連接該接合塾；第1極；以及第一 汲極，設置於該第-N型井中，和該第—區域之間形成有鎮流電 阻；以及設置在該基板上的PM0S包括：第二N型井，第二源極， 設置於該第三N型井中；以及第二⑦極，設置於該第二^^型井中， 經由導體連接到該第一没極；據此’該鎮流電阻同時保護該 及該PMOS。 根據本發明’ -種用於全金屬石夕化物輸出入咖保護的鎮流 、、'α構’包括·接合塾，基板，没置在該基板上的包括：第 一 Ν型井，其中具有第一區域連接該接合墊；第一源極；以及第 一汲極，設置於第一 Ν型井中，和該第一區域之間形成有第一鎮 流電阻，以及設置在該基板上的PMOS，包括：第二ν型井，其 中具有第二區域連接該接合墊；第二源極，設置於該第型井 中，以及第二及極，設置於該第型井中，和該第二區域之間 形成有第二鎮流電阻，且經由導體連接到該第一汲極。 【實施方式】 本發明提出兩種鎮流方法的實施例，可於〗/〇驅動器上同時對 全金屬石夕化物的NMOS及PMOS鎮流。 由於習知的全金屬矽化物I/O驅動器無法通過商用Ic產品的 通用ESD保護要求(2-kVHBMESD強韌度），必須以鎮流技術增 加其ESD強度。圖1〇繪示本發明之鎮流方法之一實施例’在 ^OS上N型井將汲極擴散分隔開並且環繞與接合墊連接的區 域’以有效地提供需要的鎮流電阻。然而，如前所述，因為這種 技術無法應用在PMOS元件上，pm〇S的鎮流需求另以特殊的金 201112391 屬路控女排來實現。不同於習知的佈局(lay〇ut)配置，pM〇s的汲 極不連接到接合墊而疋連接到]SiMOS的沒極，NMOS的沒極透過 N型井電性連接到接合墊。 圖11表示圖10實施例由A至A，的元件截面圖。透過這種佈 局配置，電流由PM0S至接合墊的路徑被強迫通過_〇8中的N 型井，使該N型井同時鎮流NM〇S和PM〇s。由於通過pM〇s 的電流導通路徑被強迫通過N型井，其阻值在圖丨丨中以電阻Rbai— 表示，其保護效果在PS模式ESD測試下是受到影響的，在PS模 • 式ESD測試下’ BSD t流先透過N型井鎮流電阻對PM〇s的汲 極放電，接著透過PM0S中寄生於p+及N型井之間的二極體到 vDD端，最後通過電源執(p0wer_rail)的ESD箝位電路(ESDdamp circuit)到達接地端。必然地，雖然鎮流n型井保護了 nmos上的 ESD損壞，卻也在PS模式ESD測試中增加了接合墊到接地端之 間的壓降損失(IESDX Rballast)，該增加的壓降夾擠了 ESD保護窗 (ESD protection window)並造成内部電路變得對ESD錯誤更為敏 φ 感，特別是在深次微米CMOS技術中。 圖12係本發明提出之另一種實施例，而圖13係圖12由A至 A’的元件截面圖。為了改善前述影響，此種鎮流技術包括n型井 將汲極擴散分隔開並且環繞與接合墊連接的區域，以達到在 NMOS上鎮流的需求，然而，PMOS上的汲極擴散也是被分開的， 為了保存PMOS的驅動能力，PM0S和nmos的汲極互相連接， 在這種配置下，PS模式測試的ESD電流可以直接經過pM〇s中 寄生於P+及N型井之間的二極體以及電源執的ESD箝位電路放 電，而不需要流經NM0S中P+及N型井之間形成的鎮流電阻 201112391Poly Array; FPA) technology. Figure 8 is a top and side view of the layout of the NMOS using FPA technology, with the interleaved polysilicon array 38 separating the diffusion regions to increase the ballast resistance value. In the CMOS process, contact resistance provides another ballast technique for all-metal germanide ESD protection MOSFETs. As shown in FIG. 9, 40 is used as a bonding pad, and the CoT ballast (CTB) technology imposes a ballast resistor on the all metal germanide NMOS from the contacts 42, 44, 46 and the diffusion region 48. . NMOS with CTB technology has reported higher ESD robustness than SB technology's ® NMOS. While many ballasting techniques are available for all-metal lithotripter I/O drivers, it is still rare to have ESD protection for the entire wafer. In order to simultaneously reduce the circuit area and improve the ESD toughness, conventional self-protected I/O drivers are often used in conventional COMS chips, and there is no additional ESD protection component in parallel. Therefore, when using the 2-KV PS mode ESD with minimum ESD protection requirements for full-wafer ESD testing on I/O pads, the lack of ballast resistance causes the esd current to concentrate on the surface of the ,, causing total metal deuteration. The NMOS crash. Therefore, an ESD protection circuit for the input and output pad has an ESD ballast resistor having an all-metal lithiation I/O driver for protecting the entire wafer. SUMMARY OF THE INVENTION One object of the present invention is to provide an esd protection circuit for inputting and outputting a bonding pad. According to the present invention, a ballast structure for all-metal germanide output into ESD protection includes: a bond pad; a substrate; and an NMOS disposed on the substrate includes: a first 201112391 N-type well having a first-region connection thereof a first pole; and a first drain, disposed in the first-N well, and a ballast resistor formed between the first region; and the PMOS disposed on the substrate includes: a second N-well, a second source, disposed in the third N-type well; and a second 7 pole disposed in the second well, connected to the first pole via a conductor; accordingly, the ballast resistor simultaneously protects the And the PMOS. According to the present invention, a ballast for the protection of an all-metal lithographic output, a 'α-structure' includes a bonding yoke, and a substrate, not disposed on the substrate, includes: a first Ν type well having a first region is connected to the bonding pad; a first source; and a first drain is disposed in the first germanium well, and a first ballast resistor is formed between the first region and a PMOS disposed on the substrate The method includes: a second type ν well, wherein the second area is connected to the bonding pad; the second source is disposed in the first type well, and the second and second poles are disposed in the first type well, and the second area is A second ballast resistor is formed therebetween and is connected to the first drain via a conductor. [Embodiment] The present invention proposes an embodiment of two ballasting methods, which can simultaneously perform NMOS and PMOS ballasting of an all-metal ceramsite on a 〇/〇 driver. Since conventional all-metal telluride I/O drivers cannot pass the general ESD protection requirements of commercial Ic products (2-kVHBMESD toughness), their ESD strength must be increased by ballast technology. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A illustrates an embodiment of the ballasting method of the present invention. The N-well divides the drain diffusion and surrounds the region connected to the bond pad to effectively provide the required ballast resistance. However, as mentioned earlier, because this technology cannot be applied to PMOS components, the ballasting requirements of pm〇S are implemented by a special gold 201112391 road-controlled women's volleyball team. Unlike the conventional layout configuration, the anode of pM〇s is not connected to the bonding pad and is connected to the immersion of the SiMOS, and the NMOS is electrically connected to the bonding pad through the N-well. Figure 11 is a cross-sectional view showing the elements of the embodiment of Figure 10 from A to A. With this layout configuration, the path from the PM0S to the bond pad is forced through the N-well in _8, which simultaneously forces the NM〇S and PM〇s. Since the current conduction path through pM〇s is forced through the N-type well, its resistance is represented by the resistance Rbai- in the figure, and its protection effect is affected under the PS mode ESD test, in the PS mode ESD Under test, the 'BSD t flow first discharges the drain of PM〇s through the N-type well ballast resistor, then passes through the PM0S parasitic between the p+ and N-type wells to the vDD end, and finally passes the power supply (p0wer_rail The ESD clamp circuit (ESDdamp circuit) reaches the ground. Inevitably, although the ballast n-well protects the ESD damage on the nmos, it also increases the pressure drop loss (IESDX Rballast) between the bond pad and the ground in the PS mode ESD test, which increases the pressure drop. The ESD protection window and the internal circuitry become more sensitive to ESD errors, especially in deep sub-micron CMOS technology. Figure 12 is another embodiment of the present invention, and Figure 13 is a cross-sectional view of the elements of Figure 12 from A to A'. In order to improve the aforementioned effects, this ballasting technique involves the n-type well separating the drain diffusion and surrounding the area connected to the bond pad to achieve the ballasting requirement on the NMOS. However, the drain diffusion on the PMOS is also Separately, in order to preserve the driving capability of the PMOS, the drains of the PM0S and the nmos are connected to each other. In this configuration, the ESD current of the PS mode test can directly pass through the pM〇s parasitic between the P+ and N wells. Body and power supply ESD clamp circuit discharge, without the need to flow through the ballast resistor formed between P+ and N wells in NM0S 201112391
Rballast。該分開的P+擴散區直接連接接合墊，因此能提供有效的放 電路徑給該PS模式下之ESD電流，PMOS中的N型井鎮流電阻 避免全金屬矽化物PMOS受ND模式ESD能量損毁。 表1列出習知無鎮流技術之元件和本發明兩實施例之元件在 全金屬矽化輸出入端人體放電模式(HBM)之靜電放電耐受度。表i 中的數值驗証了最低階誘發1C上的ESD損毁，其測試結果證實 了本發明有效改善了全金屬矽化物I/O驅動器的ESD強度。Rballast. The separate P+ diffusion regions are directly connected to the bond pads, thus providing an effective discharge path for the ESD current in the PS mode. The N-type well ballast resistors in the PMOS prevent the all metal germanide PMOS from being damaged by the ND mode ESD energy. Table 1 lists the electrostatic discharge tolerances of the conventional ballastless technology components and the components of the two embodiments of the present invention in the all metal deuterated input and output human body discharge mode (HBM). The values in Table i verify the ESD damage at the lowest order induced 1C, and the test results confirm that the present invention effectively improves the ESD intensity of the all metal telluride I/O driver.
全金屬矽化輸出入端人體放電模式 (HBM)之靜電放電耐受度 PS PD NS ND 無鎮流技術 1.5 KV 2.5 KV >8KV 4.5 KV 本發明 (第一實施例） 6KV 6KV >8KV >8KV 本發明 (第二實施例） 7kV >8KV >8KV >8KV 以上對於本發明之較佳實施例所作的敘述係為闡明之目的， 而無思限疋本發明精確地為所揭露的形式，基於以上的教導或從 本發明的實施例學習而作修改或變化是可能的，實關係為解說 本發明的原取及讓熟習該項技術者以各種實施例湘本發明在 實際應用上而選擇及敘述，本發明的技術思想企圖由以下的申請 專利範圍及其均等來決定。 201112391 【圖式簡單說明】 圖1係鎮流電阻改善ESD穩定性的電流電壓示意圖； 圖2係一種習知增加NMOS鎮流電阻的方法； 圖3係另一種習知增加_〇8鎮流電阻的方法； 圖4係圖2圖3之習知技術使用於pM0S上的側視示意圖； 圖5係習知多晶矽後段鎮流技術的NMOS佈局上視圖和侧視 不意圖； _ 圖6係習知主動區域切割技術的NMOS佈局上視圖； 圖7係另一習知主動區域切割技術的NMQS佈局上視圖； 圖8係習知浮動多晶矽陣列技術的NMOS佈局上視圖和側視 不意圖； 圖9係習知全石夕化物ESD保護MOSFET的接點鎮流技術； 圖1〇係本發明實施例之佈局上視圖； 圖11係本發明之實施例圖10由A至A’的元件截面圖； • 圖12係本發明另一實施例之佈局上視圖；以及 圖13係本發明之實施例圖12由A至A’的元件截面圖。 【主要元件符號說明】 第一區域 絕緣層 第二區域 N型井 基板 11 18 201112391Electrostatic discharge tolerance of all metal deuterated input and output human body discharge mode (HBM) PS PD NS ND ballastless technology 1.5 KV 2.5 KV > 8KV 4.5 KV The present invention (first embodiment) 6KV 6KV > 8KV > 8KV The present invention (second embodiment) 7kV > 8KV > 8KV > 8KV The above description of the preferred embodiments of the present invention is for illustrative purposes, and it is not intended that the present invention be precisely disclosed. It is possible to modify or change the form based on the above teachings or learning from the embodiments of the present invention. The actual relationship is to explain the originality of the present invention and to enable the person skilled in the art to practice the invention in various embodiments. The selection and elaboration of the technical idea of the present invention are determined by the following claims and their equals. 201112391 [Simple diagram of the diagram] Figure 1 is a schematic diagram of the current and voltage of the ballast resistor to improve the stability of ESD; Figure 2 is a conventional method of increasing the NMOS ballast resistance; Figure 3 is another conventional increase _ 〇 8 ballast resistor FIG. 4 is a side view of the conventional technique of FIG. 2 and FIG. 3 for use on the pM0S; FIG. 5 is a top view and side view of the NMOS layout of the conventional polysilicon back-end ballast technique; FIG. 7 is a top view of another conventional active area cutting technique in an NMQS layout; FIG. 8 is a top view and side view of an NMOS layout of a conventional floating polysilicon array technology; FIG. 1 is a top view of a layout of an embodiment of the present invention; FIG. 11 is a cross-sectional view of an element of FIG. 10 from A to A'; A top view of a layout of another embodiment of the present invention; and FIG. 13 is a cross-sectional view of an element of FIG. 12 from A to A' of an embodiment of the present invention. [Main component symbol description] First region Insulation layer Second region N-well substrate 11 18 201112391
20 空閘極 22 第一區域 24 第二區域 26 N型井 28 絕緣層 30 絕緣層 32 導體 34 導體 36 非直經路徑 38 多晶矽陣列 40 接合墊 42 接點 44 接點 46 接點 48 擴散區域20 Air Gate 22 First Area 24 Second Area 26 N-well 28 Insulation 30 Insulation 32 Conductor 34 Conductor 36 Non-straight path 38 Polysilicon array 40 Bond pad 42 Contact 44 Contact 46 Contact 48 Diffusion area