201111813 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種用於半導體元件測試之時脈信號產生方法，特別 是一種藉由上升脈波方式(rising-pulse approach)控制商數與餘數累加進位以 進行時脈信號產生方法。 【先前技術】 傳統用於半導體元件測試之基頻，係使用除頻器、鎖相迴圈(phaselock loop，PLL)或計數器來產生。然而這類的基頻產生方法皆無法產生任意頻 率所β產生任思頻率係指這類的基頻產生器僅可產生具有固定週期的訊 號’卻無法產生其他具有不同週期的訊號。譬如，除頻器能產生可整除於2、 4、8…等的頻率訊號，如i00Mhz經除頻器可產生5〇Mhz 25Mhz4 12 5_ 等週期頻率滅’而無法任意產生非預定週_鮮職。#鎖相迴 路做為基頻產生科，其是由輸人鮮F (frequeney inpm)、乘法器M (multiplication)與除法器N (division)所控制，鎖相頻率輸出係為F乘上M除 以N ’雖射藉由Μ與N·出較多鮮，但是仍無法產纽意的頻率訊 號。另外，若基頻產生器為-计數器’其能產生週期為τ倍數的頻率訊號， 例如IT、2Τ、3Τ等。舉例來說’ 100Mhz經計數器可產生5〇Mhz(2T)、 25Mhz(3T)或12.5Mhz(4T)等週期頻率，依然無法產生任意頻率訊號。 當利用此細產生H在it行數鋪比喊處辦，由於在處理類比訊 號取樣頻料，取細率常⑽法除，因而造成取樣鮮漂移㈣的的 狀況產生，進而魏取_率的誤差。例如，當基頻辭訊縣丨⑻麻 的數位訊號賴成3GGKhz賴味樣辭峨時，1G()M除幻⑻κ等於 3333.333，即會因為則.333的類比訊號無法被整除，， 因而產生訊號的誤差。 201111813 【發明内容】 為了解決上述先前技術不盡理想之處，本發明提供一種用於半導體_ 件測試之時脈信號產生方法，而此時脈信號產生方法包含以下步驟· 70 ⑴提供-基頻時鐘以產生時鐘脈衝Tosc，此時鐘脈衝丁⑽具有一固定頻 F及此固定頻率F所對應之週期時間Τρ ; , ;ί (2) 提供一半導體元件測試所需之時脈信號之週期Tcpu的規格； (3) 提供-計數器累加此時鐘脈衝T〇sc之週期時間Τρ，以產生一商數時間 Tq，使此商數時間Tq為此週期時間Τρ之整數倍； ⑷提供-餘數加法器進行餘數累加以產生一餘數_ Tr，此餘數時間打 ^於此週期咖Τρ ’使得此雜親與此商數咖Tq之差料於此餘數 (5) 當此餘數加法器因餘數累加而發生進位時，提供1位脈衝至此計數器 以使此商數時間Tq增加一單位之週期時間Tp ; (6) 提供-延遲線以產生一延遲時間Td，此延遲時間Td等於此餘數時間化 ⑺根據延遲關Td崎遲此雜_ Tq，據此得麻料體元件測試所 需之時脈信號之週期Tcpu。 η因此’本發明之主要目的在於提供一種用於半導體元件測試之時脈信 號產生方法’可娜—狀週_產生㈣鮮之基頻信號。 、本發明之次要目的在雜供—種祕半導體元制試之雜信號產生 方法’藉由餘數累加進位而觸發—上升脈波產生器據此可將商數時間延 長-單位之週_間，可有效消除鮮漂移的問題。 、I發—目的在於提供-翻於半導體元件麟之時脈信號產生 方法，藉由將上升脈波產生!I所產生的單位上升脈波輸人至商數時間之計 數器’可有效解她比信號無法被整除的問題。 201111813 【實施方式】 由於本發明係揭露-種時脈信號產生方法，用於半導體元件測試，其 愤用的積體電路元件測試原理，已為相關技術領域具有通常知識者所能 明瞭’故以下文中之制，不再作完整描述。此外，本發明的施行並未限 定用於基頻的取樣鮮產生器之技藝者所熟f的特殊細節。另—方面，幕 所周知的取樣鮮之運作並未描祕細料，以避免造成本 發明不必要之關。細，騎本發_健實_，則會詳細描述如下， 然而除了這些詳細描述之外，本發明還可以廣泛地施行在其他的實施例 中，且本發明的範圍不受限定，其以之後的專利範圍為準。同時，以下文 中所對照之圖式，係表賴本發腎徵有關之結構示意，並未亦不需要依 據實際尺寸完整繪製，盍先敘明。 首先請參考第-圖，係為本發明提出之較佳實施例，為一種用於 體讀測試之日械雜產生綠，此雜信鮮生方法包含以下步驟： ()提供基頻時知以產生時鐘脈衝T〇sc，此時鐘脈衝具有一固定 F及此固定頻率F所對應之週期時間Tp (S110); ()提供半導體儿件測试所需之時脈信號之週期及pu的規格，包括對廡 =的商數部時間、餘數部時間以及邊緣觸發之形式⑻^ … (3)2供梢器以累加時鐘脈衝T〇sc之週期時間办，據此產生一商數 Β，間Tq’其中此商數時間Tq為週期時間Τρ之整數倍（S130); 數加法如進行_加，據此產生—餘數時間h，其中此餘 時間小於週期時間TP，且使得時脈信號與商數時間Tq之時間差等 於此餘數時間Tr (S140); 寻 ()田此餘數加去器因餘數累加而發生進位時，提供—單位脈衝至此計數器 ^使此商數時間Tq增加·'單位之週期時間Tp (S150) ； 〇 ^遲線以產生一延遲時間Td ’此延遲時間Td等於此餘數時間Tr (S160);以及 201111813 ⑺根據此此延遲铜Td以延麟數制Tq，據此可制此半導體元件測 試所需時脈信號之週期時間Tcpu (S170) 〇 奪參考表與第二圖，係說明本發明之時脈信號產生機制。時脈信號 產生機制餐1G()MHz_时秒則雜震紅基礎而產 生所需之時=信號Tepu為3(X)KHz(職3333 33333奈秒卜在此基頻時 1、有U讀率F ’也就是·時此固定辭1麵所對應之201111813 VI. Description of the Invention: [Technical Field] The present invention relates to a method for generating a clock signal for testing semiconductor elements, and more particularly to controlling a quotient by a rising-pulse approach The remainder is accumulated to carry out the clock signal generation method. [Prior Art] The fundamental frequency conventionally used for semiconductor component testing is generated using a frequency divider, a phase lock loop (PLL), or a counter. However, such a fundamental frequency generation method cannot generate an arbitrary frequency. The β-generated frequency means that such a fundamental frequency generator can only generate a signal having a fixed period but cannot generate other signals having different periods. For example, the frequency divider can generate frequency signals that can be divided by 2, 4, 8, etc., such as i00Mhz, which can generate 5〇Mhz 25Mhz4 12 5_ by the frequency divider, and the cycle frequency is off, and cannot generate arbitrary schedules _ . The #phase-locked loop is used as the base frequency generation section, which is controlled by the Frequeney inpm, the multiplier M (multiplication) and the divider N (division). The phase-locked frequency output is F multiplied by M. Although N' is shot by Μ and N· is more fresh, but still can not produce the frequency signal. Further, if the fundamental frequency generator is a -counter', it can generate a frequency signal having a period of τ multiple, such as IT, 2Τ, 3Τ, and the like. For example, the '100Mhz counter can generate periodic frequencies such as 5〇Mhz(2T), 25Mhz(3T) or 12.5Mhz(4T), and still cannot generate arbitrary frequency signals. When using this fine to generate H in the number of rows of the shop, because the sampling rate of the analog signal is processed, the fineness is often divided by (10) method, thus causing the situation of sampling fresh drift (4), and then the rate of the sample is taken. error. For example, when the digital signal of the baseband speech county (8) hemp is converted into 3GGKhz, the 1G()M illusion (8) κ is equal to 3333.333, because the analog signal of .333 cannot be divisible, thus resulting in Signal error. 201111813 SUMMARY OF THE INVENTION In order to solve the above-mentioned prior art unsatisfactory, the present invention provides a clock signal generating method for semiconductor_device testing, and the pulse signal generating method includes the following steps. 70 (1) Providing - fundamental frequency The clock generates a clock pulse Tosc, the clock pulse D10 has a fixed frequency F and a period Τρ corresponding to the fixed frequency F; , ί (2) provides a period Tcpu of a clock signal required for testing a semiconductor component (3) The counter-counter accumulates the cycle time Τρ of the clock pulse T〇sc to generate a quotient time Tq such that the quotient time Tq is an integer multiple of the cycle time Τρ; (4) providing a - remainder adder The remainder is accumulated to produce a remainder _ Tr, and the remainder time is ^ 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此 于此When a 1-bit pulse is supplied to the counter to increase the quotient time Tq by one unit of the cycle time Tp; (6) providing a delay line to generate a delay time Td equal to the remainder time The delay Td ⑺ off later this Kawasaki heteroaryl _ Tq, whereby to obtain hemp element test cycle of the clock signals required Tcpu. η Therefore, the main object of the present invention is to provide a clock signal generating method for semiconductor element testing, which can generate a (four) fresh fundamental frequency signal. The secondary purpose of the present invention is to generate a heterogeneous signal generation method for the heterogeneous-semiconductor semiconductor element test, which is triggered by the residual accumulation carry-up. The rising pulse wave generator can thereby extend the quotient time-unit week_between Can effectively eliminate the problem of fresh drift. , I hair - the purpose is to provide - turn over the semiconductor component Lin clock signal generation method, by the rising pulse wave generated! I generated by the unit rising pulse wave input to the quotient time counter 'can effectively solve her ratio The problem that the signal cannot be divisible. 201111813 [Embodiment] Since the present invention discloses a method for generating a clock signal, which is used for testing semiconductor devices, the principle of testing the integrated circuit components used by the related art has been known to those skilled in the relevant art. The system in the text is no longer fully described. Moreover, the practice of the present invention does not limit the particular details of the skilled artisan of the baseband. On the other hand, the well-known sampling operations are not detailed, in order to avoid unnecessary problems in the invention. The present invention is described in detail in the following detailed description, but the scope of the present invention is not limited, and The scope of the patent is subject to change. At the same time, the patterns in the following texts are based on the structure of the kidney sign, and do not need to be completely drawn according to the actual size. First of all, please refer to the first figure, which is a preferred embodiment of the present invention, which is a green type for the body reading test. The method for fresh-keeping of the hybrid includes the following steps: () Generating a clock pulse T〇sc having a fixed F and a period time Tp corresponding to the fixed frequency F (S110); () providing a period of the clock signal and a specification of the pu required for the semiconductor component test, Including the quotient part time, the remainder time, and the edge triggering form of 庑= (8)^ (3) 2 The tipping device performs the cycle time of accumulating the clock pulse T〇sc, thereby generating a quotient Β, between Tq 'where the quotient time Tq is an integer multiple of the cycle time Τρ (S130); the number addition is performed as _add, and accordingly generates a remainder time h, wherein the remaining time is less than the cycle time TP, and the clock signal and the quotient are made The time difference of time Tq is equal to the remainder time Tr (S140); when the remainder of the seeker is added by the remainder, the unit pulse is supplied to the counter ^ to increase the quotient time Tq·' Tp (S150) ; 〇^late line to generate a delay Td 'this delay time Td is equal to the remainder time Tr (S160); and 201111813 (7) according to this delay copper Td is based on the number of times Tq, according to which the cycle time Tcpu of the clock signal required for testing the semiconductor component can be made (S170 The reference table and the second figure are used to illustrate the clock signal generation mechanism of the present invention. Clock signal generation mechanism meal 1G () MHz _ seconds when the noise is red basis to produce the required time = signal Tepu is 3 (X) KHz (3333 33333 nanoseconds at this base frequency 1, there is U read The rate F 'is also the corresponding one of the fixed words
二時]P則疋10奈秒(nS)，而欲產生之時脈信號Tcpu之週期時間係由 商數時間Tq與一餘數時間Tr所組成。 當欲產生時脈信號Tcpu所需之第一個週期時間地迎灿時，時脈 ^產生機制產生對應上述第一個週期時間之第一個商數時間Tq為遍 沾’二及對應上述第一個週期時間之第一個缝時間η為3.脚沾。 虽欲產S時脈錄Tcpu所需之第二個週期祕祕触時 666〇 ^ } 數時間Tr亦藉由累加上述第一個餘數時間得到6細. -初生時脈信號¥所需之第三個週期"99.99震時，對库之第 由累力吐述第二個商數時間而得到999g ns，第三個 餘數，間Tr亦侧加上述第二個餘數時間而得到9.戀. 第二ίίί時脈信號TCPU所需之第四個週期13333.3迎nS時，對岸之 =數時間Tr _由累加上述第三個餘數時間而得和細 ^ 進位發生而加至細個商數時間=而第關3.33胸，多出的聰因 理，時脈信號TCP碰續所需之商數商數時間得到删沾。同 方式持續進行。 _ '與餘數時間Tr將依據這樣循環 201111813 表一、時脈信號產生機制The second time]P is 10 nanoseconds (nS), and the cycle time of the clock signal Tcpu to be generated is composed of the quotient time Tq and a remainder time Tr. When the first cycle time required to generate the clock signal Tcpu is welcoming, the clock generation mechanism generates the first quotient time Tq corresponding to the first cycle time as the second and corresponding to the above The first slit time η of one cycle time is 3. Although the second cycle required for the recording of the S clock is required to be touched by the 666 〇 ^ }, the time Tr is also obtained by accumulating the first remainder time. 6 - The birth clock signal is required. In the three cycles "99.99 earthquake time, the second quotient time of the library is exhausted to get 999g ns, the third remainder, and Tr is also added to the second remainder time to get 9. Love The second period required by the second clock signal TCPU, 13333.3, welcomes nS, the opposite bank's = time Tr _ is added to the third quotient time by summing up the third remainder time and adding to the fine quotient time = And the third level of 3.33 chest, the extra Cong Yin, the time quotient of the clock signal TCP continuation required to get deleted. The same way continues. _ 'and the remainder time Tr will be based on this cycle 201111813 Table 1, clock signal generation mechanism
週期時間 商數時間 延遲時間（餘數時間） 3333.33333nS 0000nS+3330nS=3330nS O.OOOOOnS+3.33333nS= 3.33333nS 6666.66666nS 3330nS+3330nS=6660nS 3.33333nS+3.33333nS= 6.66666nS 9999.99999nS 6660nS+3330nS=9990nS 6.66666nS+3.33333nS= 9.99999nS 13333.33332nS 9990nS+3330nS=13320nS 9.99999nS+3.33333nS=13.3332nS 進位發生 10nS 13320nS+10nS=13330nS ->3.33332nS 請參考第三圖，在上述實施例中，時脈信號產生方法可用在一時脈信 號產生系統20 ’以提供半導體元件測試所需之時脈信號Tcpu，此時脈信號 產生系統20包括一中央處理器21 ' —商數記憶體22、一振盪器23、一餘 數δ己憶體24、餘數加法器25、餘數暫存器26、上升脈衝產生器27、計數 器28、比較器29以及延遲線3〇，其中振盪器23產生一基頻時鐘且具有一 固定頻率F為100MHz(週期1〇奈秒）。中央處理器21產生半導體元件測試 所而之時脈k號Tcpu的規格。時脈信號產生系統2〇進一步包含提供一第 -記憶體(也就是商數記憶體22)，第一記憶體係儲存一商數時間Tq，且可 供中央處㈣21存取1外進—步包含_第二記憶體(也就是餘數記憶體 24) ’第二記憶體係儲存餘數_ Tr，且可供中央處理胃21存取。商數時 間Tq的累加係將商數記憶體22存放之商數值輸入比較器29且根據振盈器 2之週期觸發以㈣商鱗，的累加。餘數_ 的累加係將餘數記憶 體24存紅賊_錄數加邮25與缝做_ %⑽行餘數時間的 累加。單位脈衝信號係由上升脈衝產生器27所提供。此外’計數器28進 :步包含-遞增式加法器281、多工器282朗鎖器挪。值得注意的是， 虽餘數_ tv發生進位_發上升脈魅生㈣27，使得上升脈衝產生器 7提供-㈣蝴Η龜魏^ 28之彡卫請，使縣本域增式加法 201111813 器281所產生之计數值(C0unter value)藉由問鎖器283之作動而被延遲川奈 秒之週期時間，據此可有效消除頻率漂移的問題，且有效解決類比信號無 法被整除關題。糾，賴線3G之侧在於提供—延遲_ Μ，而延遲 時間Td等於餘數時間Tr’進而使得商數時間Tq被延遲餘數時間以產生 時脈信號Tcpu所需的每一週期時間。 以上所述僅為本發明之較佳實施例，並非用以限定本發明之中請專利 權利；同時以上的描述，對於熟知本技術領域之專以士應可明瞭及實施， φ因此其他未脫離本發明所揭示之精神下所完成的等效改變或修飾，均應勺 含在申請專利範圍中。 〜匕 【圖式簡單說明】 第-®為-流侧，係根據本發明提出之較佳實細，為—種用於 導體元件測試之時脈信號產生方法。 、 第二圖為一時序圖’係根據本發明提出之較佳實施例，為-種用於半 導體元件測試之時脈信號產生時間。 ' 第三圖為-方塊圖，係根據本發明提出之較佳實施例，為—種時 ’ 號產生系統。 ° 【主要元件符號說明】 時鐘脈衝Tosc 頻率F 週期時間Tp 時脈信號Tcpu 商數時間Tq 餘數時間Tr 延遲時間Td 時脈信號產生系統20 中央處理器21 商數記憶體22 振盪器23 餘數記憶體24 201111813 餘數暫存器26 多工器282 比較器29 餘數加法器25 上升脈衝產生器27 計數器28 遞增加法器281 閂鎖器283 延遲線30 步驟 S110、S120、S130、S140、S150、S160、S170Cycle time quotient time delay time (residual time) 3333.33333nS 0000nS+3330nS=3330nS O.OOOOOnS+3.33333nS= 3.33333nS 6666.66666nS 3330nS+3330nS=6660nS 3.33333nS+3.33333nS= 6.66666nS 9999.99999nS 6660nS+3330nS=9990nS 6.66666 nS+3.33333nS= 9.99999nS 13333.33332nS 9990nS+3330nS=13320nS 9.99999nS+3.33333nS=13.3332nS Carrying occurs 10nS 13320nS+10nS=13330nS ->3.33332nS Please refer to the third figure, in the above embodiment, the clock signal The generating method can be used in a clock signal generating system 20' to provide a clock signal Tcpu required for testing the semiconductor component. The pulse signal generating system 20 includes a central processing unit 21' - quotient memory 22, an oscillator 23, a remainder δ hex memory 24, a remainder adder 25, a remainder register 26, a rising pulse generator 27, a counter 28, a comparator 29, and a delay line 3A, wherein the oscillator 23 generates a fundamental frequency clock and has a fixed The frequency F is 100 MHz (cycle 1 〇 nanosecond). The central processing unit 21 generates the specifications of the clock k number Tcpu for the semiconductor element test. The clock signal generating system 2 further includes a first memory (ie, quotient memory 22), the first memory system stores a quotient time Tq, and is available for the central (four) 21 access 1 external input step-by-step _Second memory (ie, remainder memory 24) 'The second memory system stores the remainder _Tr and is available for central processing stomach 21 access. The accumulation of the quotient time Tq inputs the quotient value stored in the quotient memory 22 to the comparator 29 and triggers the accumulation of the (4) quotient scale according to the period of the oscillator 2. The accumulation of the remainder _ accumulates the remainder memory 24 in the red thief _ record plus post 25 and sew _ % (10) line accumulation time remainder. The unit pulse signal is provided by the rising pulse generator 27. Further, the 'counter 28' step includes an incremental adder 281 and a multiplexer 282 locker. It is worth noting that although the remainder _ tv occurs into the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The generated count value (C0unter value) is delayed by the cycle time of the Kawasaki second by the action of the lock 283, thereby effectively eliminating the problem of frequency drift and effectively solving the problem that the analog signal cannot be divisible. The correction, the side of the line 3G is to provide - delay _ Μ, and the delay time Td is equal to the remainder time Tr' such that the quotient time Tq is delayed by the remainder time to generate each cycle time required for the clock signal Tcpu. The above description is only a preferred embodiment of the present invention, and is not intended to limit the patent right of the present invention; at the same time, the above description should be understood and implemented for those skilled in the art, and therefore φ is not separated. Equivalent changes or modifications made in the spirit of the present invention should be included in the scope of the patent application. ~ 匕 [Simple description of the drawing] The - - - - flow side, which is a preferred embodiment of the present invention, is a method for generating a clock signal for testing a conductor element. The second diagram is a timing diagram', which is a preferred embodiment of the present invention, which is a clock signal generation time for semiconductor component testing. The third figure is a block diagram, which is a preferred embodiment of the present invention, which is a time-of-day generation system. ° [Main component symbol description] Clock pulse Tosc Frequency F Cycle time Tp Clock signal Tcpu Quotient time Tq Remainder time Tr Delay time Td Clock signal generation system 20 Central processor 21 Quotient memory 22 Oscillator 23 Remainder memory 24 201111813 Remainder register 26 multiplexer 282 comparator 29 remainder adder 25 rising pulse generator 27 counter 28 incrementing 281 latch 283 delay line 30 steps S110, S120, S130, S140, S150, S160, S170
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