TW201110540A - Amplifier with programmable off voltage - Google Patents

Abstract

An amplifier with multiple stages and having improved reliability is described. The multiple amplifier stages are coupled in parallel and include at least one switchable amplifier stage. Each switchable amplifier stage may be operated in an on state or an off state and includes a gain transistor and a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and is disabled in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state and is disabled based on an off voltage in the off state. The off voltage may be greater than zero volts or may have one of multiple possible values. The off voltage may be generated based on an output signal level, e.g., may be set to different values for different ranges of output signal level.

Description

201110540 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to electronic devices and, more particularly, to an amplifier. [Prior Art] - Amplifiers are commonly used in various electronic devices to provide signal amplification. Different types of amplifiers can be used for different purposes. For example, a wireless communication device such as a beephone can include one of a transmitter for two-way communication and a receiver. The transmitter can utilize a driver amplifier (DA) and a power amplifier (PA). The receiver can utilize a low noise amplifier (LNA), and the transmitter and receiver can utilize a variable gain amplifier (VGA). Sub-micron complementary metal oxide semiconductor (CMOS) fabrication processes are commonly used in radio frequency (RF) circuits in wireless devices and other electronic devices to reduce cost and improve integration. However, transistors fabricated in sub-micron (: River 03 process typically have small physical dimensions and are more susceptible to stresses due to large signal swings. This stress can adversely affect the amplifier implemented by such an isomorph Offence. There is an urgent need for an amplifier with good performance and good reliability. [Embodiment] • The word "exemplary" is used herein to mean "serving as an instance, instance or description." Any design that is exemplary should not be construed as preferred or advantageous over other designs. Amplifiers with good performance and improved reliability are described herein. Amplifiers can be used in a variety of electronic devices, such as wireless communication devices, honeycombs Telephones, personal digital assistants (PDAs), handheld devices, wireless data I45291.doc 201110540 machines, laptops, wireless phones, broadcast receivers, Bluetooth devices, consumer electronics, etc. For the sake of clarity, The use of an amplifier in a wireless device that can be a cellular phone or some other device is described below. Figure 1 shows a wireless communicator A block diagram of an exemplary design of the device 1. In this exemplary design, the wireless device 100 includes a data processor 11 and a transceiver 120. The transceiver 120 includes a transmitter 130 and a support for two-way wireless communication. Receiver 150. In general, the wireless device 1 can include any number of transmitters and any number of receivers for any number of communication systems and any number of frequency bands. In the transmission path, data processor 110 processes The data to be transmitted and the analog output signal is provided to transmitter 130. Within transmitter 130, the analog output signal is amplified by amplifier (Amp) 132 and filtered by low pass filter 134 to remove the digital to analog conversion. The image is amplified by VGA 136 and is upconverted from base frequency to rf by mixer 13. The upconverted signal is filtered by filter 140 to remove the image caused by the upconversion, further by the driver amplifier (DA) 142 and power amplifier (pa) 144 are amplified, delivered via duplexer/switch 146, and transmitted via antenna 148. In the receive path, antenna 148 receives from the base station And provide the received signal 'The received signal is routed via duplexer/switch 1 46 and provided to receiver 150. Within receiver 150, the received signal is amplified by LNA 1 52 by bandpass Filter 154 filters and is downconverted from RF to the fundamental frequency by mixer 156. The downconverted signal is amplified by vga 158, filtered by low pass filter 160 and amplified by amplifier 1 62 to obtain the data. Analog input signal to processor 110. 145291.doc 201110540 Figure 1 shows a transmitter 130 and a receiver 15A implementing a direct conversion architecture that frequency converts a signal between RF and a fundamental frequency in one stage. Transmitter 130 and/or receiver 150 may also implement a superheterodyne architecture that frequency converts signals between RF and fundamental frequencies in multiple stages. The local oscillator (L0) generator 17 generates a transmission signal and a reception LO signal, and supplies them to the mixers 138 and 156, respectively. A phase locked loop (PLL) 172 receives control information from the data processor 11 and provides control signals to the LO generator 170 to generate transmissions at appropriate frequencies and to receive and receive L0 signals. Figure 1 shows an exemplary transceiver design. In general, the adjustment of the signals in transmitter J3 and receiver 150 can be performed by one or more stages of amplifiers, filters, mixers, and the like. These circuit blocks can be configured differently than the configuration shown in Figure i. In addition, other circuit blocks not shown in the figure can be used to adjust the signals in the transmitter and receiver. Some of the circuit blocks in Figure 1 may also be omitted. All or part of the transceiver i 20 may be implemented on an analog integrated circuit (1C), an RF lC (RFIC), a hybrid nickname 1C, or the like. For example, amplifier U2 in transmitter 13A can be implemented on the RFIC to driver amplifier 142' and power amplifier 丨44 can be implemented external to the RFIC. The data processor 110 can perform various functions of the wireless device 100, such as processing of transmitted and received data. Memory! 12 can store code and data for the data processor 110. The data processor no can be implemented on one or more special application integrated circuits (AS 1C) and/or other 1C. As shown in Figure 1, a transmitter and a receiver can include various amplifiers. Each amplifier can be implemented in a variety of ways. 145291.doc 201110540 FIG. 2 shows a schematic diagram of an amplifier 200 that can be used with DA 142, PA 144, LNA 152, VGA 136 and 158, and/or other amplifiers in FIG. The amplifier 200 includes κ amplifier stages 2 10a through 210k coupled in parallel, where κ can be any integer value. The amplifier stage can also be referred to as a branch or the like. In each amplifier stage 210, the source of the 'N-channel MOS transistor 212 is connected to the circuit ground' and its gate receives an input signal Vin ^. The terms "transistor" and "and" are often used interchangeably. Device". The source of the NMOS transistor 214 is coupled to the drain of the NMOS transistor 212 and its drain is coupled to the node X that provides the output signal Vout. NMOS transistor 212 is a gain transistor that receives a Vin signal at its gate to amplify the Vin signal and provide an amplified signal at its drain. The NMOS transistor 214 has its gate coupled to an ac grounded cascode transistor. NMOS transistor 2 14 receives the amplified signal at its source and provides a v〇uMf number at its drain. The input of inverter 220 receives a Bk control signal and its output provides a control voltage for NMOS transistor 214, where keO,, . . . , K}. The inverter 220 can be implemented by a P-channel MOS (PMOS) transistor and an NMOS transistor. The gates of the transistors are coupled together to form an inverter input, and the Together form the inverter output. The source of the PM 电 电 transistor can be coupled to the power supply Vdd, and the source of the NM 〇 s transistor can be connected to the circuit ground, as shown in FIG. 2 . Resistor 222 is coupled between the output of inverter 220 and the gate of NMOS transistor 214. The inductor 230 is coupled between the node X and the Vdd supply voltage. Inductor 230 provides bias current for NM〇s transistors 212 and 145291.doc 201110540 214 for all enabled amplifier stages, and inductor 23〇 can also be used for output impedance matching. Each of the κ amplifier stages 210a through 210k can be individually enabled or disabled via respective Bk control signals. For the kth amplifier stage, when Bk controls k to be at logic low, inverter 22 提供 provides vdd at its output, NMOS transistor 214 is turned "on" and the amplifier stage is enabled. Conversely, when the Bk control k is at logic high, the inverter 220 supplies 〇 volts (V) at its output, the NMOS transistor 214 is turned off, and the amplifier stage is disabled. Each amplifier stage provides signal gain when enabled. K amplifier stages 210a through 21 Ok may provide equal amounts of gain (eg, with all κ amplifier stages having the same transistor size) or may provide different amounts of gain (eg, different at the K amplifier stages) In the case of transistor size). For example, the size (and gain) of NMOS transistors 212 and 214 in amplifier stage 1 can be twice that of NMOS transistors 212 and 214 in amplifier stage 2 NMOS transistors 212 and 2 14 in amplifier stage 2. The size can be twice that of the NMOS transistors 212 and 214 in the next amplifier stage, and so on. The desired overall gain of the amplifier 2 can be obtained by enabling the appropriate amplifier stage(s). The output signal level is dependent on the total gain of the visual amplifier 200 (e.g., may be proportional to the total gain of the amplifier 200). The amplifier 200 operates as follows. For each amplifier stage enabled, the nm〇s transistor 212 amplifies the Vin signal and provides an amplified signal. NMOS transistor 212 also performs voltage to current conversion. The NMOS transistor 2 14 buffer is provided with a current gain and provides a signal drive for the V〇ut signal. Resistor 222 is an RF blocking resistor that blocks the RF signal component in the Vout signal at the gate of NMOS transistor 214. 145291.doc 201110540 The amplifier 200 is implemented by an open drain architecture commonly used for driver amplifiers in wireless transmitters. The amplifier 200 uses an inductor 230 coupled between the Vdd supply voltage and the stacked transistors 214 of all of the K amplifier stages 21a through 210k. Inductor 230 allows the Vout signal to swing above the Vdd voltage'. This situation can be beneficial for obtaining a higher 1 dB (dB) compression point for amplifier 200 and better adjacent channel leakage rejection (ACLR) and adjacent channel power rejection ( ACPR) performance. However, a larger v〇ut signal swing can also cause loss of reliability to the stacked transistor 214. When the Vout signal is higher than vdd, the stacked transistors 214 of all of the K amplifier stages 21A can observe a large voltage at which stress can be applied to the stacked transistors. For each amplifier stage 210 that is enabled, the voltage swing of the Vout signal can be split across the stacked transistor 2丨4 and the gain transistor 212 by applying vdd to the gate of each enabled stacked transistor. However, when the stacked transistor 214 is turned off by automatic gain control (AGC), for example, when a smaller output signal level is required, most of the stress due to the swing of the larger Vout signal occurs. Even when the spliced transistor 214 is turned off, the spliced transistor 214 is still connected to the output node X and will then observe the v 〇ut signal at its drain. In the off state, the gate of the stacked transistor 214 is pulled to ground via the inverter 22, and the source of the stacked transistor 214 is also pulled to ground via the gain transistor 2 12 operating as a switch. In the off state, the drain-to-source voltage Vds and the drain-to-gate voltage vdg of the stacked NMOS 214 may be greater than Vdd (e.g., 'doubled to Vdd') and may exceed the rated device voltage. Large Vds and Vdg voltages can stress the stacked transistor 214 and can adversely affect the reliability and lifetime of the transistor. The stress can be particularly severe when the amplifier 2 operates with high gain / 14529i.doc •10-201110540 two output powers and deactivates an amplifier stage to reduce the gain. The stacked transistors in this deactivated amplifier stage can observe Vds and Vdg voltages that are much higher than Vdd. 3 shows a schematic diagram of an exemplary design of an amplifier 300 having a programmable cut-off voltage for improved reliability. Amplifier 3 〇〇 can be used for DA 142, PA 144, LNA 152, VGA 136 and 158' and/or other amplifiers in FIG. The amplifier 3A includes an inverse amplifier stage 3 10a to 3 10k coupled in parallel. Within each amplifier stage 31, the source of NMOS transistor 3 12 is coupled to circuit ground ' and its gate receives a Vin signal. The source of the NMOS transistor 3 14 is coupled to the drain of the NMOS transistor 3 12 , the gate of which is coupled to the node Ak ' (where ke{l, .., K}), and the drain is coupled to Node X. The input of the inverter 320 receives the Bk control signal, the upper supply node is coupled to the node γ, and the lower supply node is coupled to the node Z. The resistor 322 is coupled between the output of the inverter 320 and the node aAk. The capacitor 324 is coupled between the node Ak and the circuit ground. The inverter 320 can also be replaced with a buffer composed of a plurality of (e.g., two) inverters connected in series. The Bk control signal visible inverter or buffer is used in the amplifier stage 31〇 with different polarities. The inductor 330 is coupled between the Vdd power supply and the node X that provides the v〇m signal. The Von voltage generator 340 supplies the turn-on voltage Von to the node γ, and can be implemented by a resistor, a capacitor, a transistor, or the like. The v〇n voltage can be equal to the fraction of vdd or vdd. When the amplifier stage is enabled, the v〇n voltage can be selected to provide the desired voltage drop across the stacked transistor 314 and the gain transistor 312. The Von voltage generator 340 can also be omitted, and the node γ can be directly coupled to the Vdd 145291.doc 201110540 power supply. The Voff voltage generator 350 provides the cutoff voltage v?ff to the node Z' and can be implemented as described below. Another voltage generator, not shown in Figure 3, can generate a bias voltage for the gate of the NMOS transistor 3 1 2 of all K amplifier stages 310. Each of the K amplifier stages 310a through 31 Ok can be individually enabled or disabled via a Bk control signal for the other stage. The kth amplifier stage can be enabled by providing a logic low to the Bk control signal. This condition causes the inverter 320 to provide a Von voltage to the gate of the NMOS transistor 3 14 via the resistor 322 and turn the NMOS transistor on. Conversely, the kth amplifier stage can be deactivated by providing a logic high to the Bk control signal, which causes the inverter 320 to provide a Voff voltage to the gate of the NMOS transistor 314 via the resistor 322 and to turn off the NMOS. Transistor. The spliced amplifier 300 operates as follows. For each amplifier stage 3 1 0 that is enabled, the NMOS transistor 3 1 2 operates as a gain transistor that amplifies the Vin signal. NMOS transistor 314 is enabled by the Von voltage at its gate, operates to buffer the stacked transistor from the amplified signal of NMOS transistor 312, and provides signal drive for the Vout signal. Resistor 322 is an rf blocking resistor that blocks the RF signal component in the Von voltage at the gate of NMOS transistor 314. Capacitor 324 stabilizes the gate voltage of NMOS transistor 314 to improve the gain of NMOS transistor 314. For each amplifier stage that is deactivated, NMOS transistor 314 receives the V〇ff voltage at its gate and is turned off. The NMOS transistors 312 and 314 can be implemented by a thin oxide NMOS transistor having a thin gate oxide to achieve good rf performance. The reliability of the gate oxide of a thin oxide NMOS transistor depends on the voltage of the nm 〇s 145291.doc •12· 201110540 depending on the Vdg voltage at which it is turned off. The lifetime of the thin oxide NMOS transistor can be given by a time dependent dielectric collapse (TDDB) function prior to the breakdown of the gate oxide. The TDDB function can be modeled by an equation or can be determined by computer simulation. Figure 4 shows a graph of oxide lifetime versus Vdg voltage. The horizontal axis represents the Vdg voltage and is given on a linear scale. The vertical axis represents the oxide lifetime and is given on a logarithmic scale. Curve 410 shows the oxide lifetime versus Vdg voltage for a thin oxide NMOS transistor. Curve 420 shows the oxide lifetime versus Vdg voltage of a thin oxide PMOS transistor. The dashed line 43 0 represents the target oxide lifetime, which may be 10 years as shown in Figure 4 or some other duration. As shown in Figure 4, the target oxide lifetime of the NMOS transistor can be obtained by ensuring that the Vdg voltage of the NMOS transistor is below the Vmaxl voltage. The target oxide lifetime of the PMOS transistor can be obtained by ensuring that the Vdg voltage of the PMOS transistor is lower than the Vmax2 voltage. The curves 410 and 420 and the Vmax1 voltage and the Vmax2 voltage may be determined by various factors such as a 1C manufacturing process, a gate oxide thickness, a gate oxide area, a temperature, and the like. For the exemplary design shown in Figure 3, the Vdg voltage of the deactivated NMOS transistor 3 14 can be given as:

Vdg=Vout-Voff 〇 Equation (1)

The Vdg voltage should be less than Vmaxl to achieve the desired oxide lifetime of the NMOS transistor 314. As shown in equation (1), the Vdg voltage can be reduced by increasing the Voff voltage. A higher Voff voltage improves oxide lifetime, which is desirable. However, since the Voff voltage is applied to the gate of the NMOS transistor 314 when the NMOS transistor 314 is stopped, the v〇ff voltage should be limited as follows: Equation (2)

Voff < Vth, where Vth is the threshold voltage of the NMOS transistor 314. A higher v〇ff voltage can increase leakage current through the nm〇S transistor 3 14 when the NMOS transistor 314 is turned off, which can be undesirable. The voltage can be selected based on a trade-off between oxide reliability and leakage current. The Vdg voltage can be decomposed into a direct current (DC) portion and an alternating current (AC) portion. The DC portion of the Vdg voltage can be viewed as a V〇ff voltage and can be related to (e.g., equal to) the Vout of Vout Vout. The AC portion of the vdg voltage can be determined by the AC portion of the V〇ut signal. The parasitic drain to gate capacitance cdg of the NM〇s transistor 314 can help maintain the Vdg voltage and reduce the amount of coupling of the ac portion of the v〇ut signal. ~ In an exemplary design, the ride voltage can be a programmable value for the visual output signal level. A larger v〇ff voltage can be used for a larger output signal level and vice versa. A larger v〇ff voltage can result in more leakage current. However, more current can be consumed to provide a larger output signal = a higher leakage current can therefore account for a small percentage of the overall output signal level. The medical voltage can be set to 〇 v for low output signal levels, and leakage current will not occur under this condition. Figure 5 shows an exemplary design of a programmable V〇ff voltage. Horizontal axis table The output, level, which can be given in decibels (dBm). The vertical axis represents the medical voltage that can be given in volts. 145 291.doc -14 - 201110540 510 shows the Voff voltage versus output signal level. In the exemplary design shown in Figure 5, the Voff voltage can be set to one of four possible values based on four ranges of rounded signal levels. In particular, the medical power can be set to VofH for the output signal level of PouU or less than Poutl, and set to Voff2 for the output signal level between the plus and the like, for? The output signal level between _2 and P〇ut3 is set to

Voff3, or the output signal level for Pout3 or greater than p〇ut3 is set to

Voff4. Voffl to Voff4 and p〇utl to ρ_3 may be selected based on various factors such as desired oxide reliability, Vmax of the NMOS transistor, desired overall range of output signal levels, and the like. In an exemplary design, Voffl may be equal to 〇 V, v 〇 ff2 may be equal to 1 〇〇 millivolt (mv), 侃 may be equal to 200 mV, and % 4 may be equal to 3 〇〇 mV. In an exemplary design: Poutl can be equal to 4 dBm, P〇ut2 can be equal to 8 dBm, and 卩^ can be equal to 12 dBm. You can also set ... to ^ and add to 卩 ^ ^ to other values. Figure 5 shows an exemplary design for setting the Voff voltage to discrete values for different ranges of output signal levels. In general, any number of Voff values can be used for any number of ranges of output signal levels. Any Voff value can be used to output each range of the loyalty level. In another exemplary design, the v〇ff voltage can be continuously adjusted based on the output level. For two exemplary settings. Ten can be judged based on the B1 to BK control signals for the K amplifier stages 310. The B1 to BK control signals can thus be used to generate a Voff voltage. Figure 6 shows an illustration of an exemplary design of the Voff voltage generator 350 of Figure 3, 14529l.d, 201110540. In the Voff voltage generator 350, the source of the PM 〇s transistor 61 耦 is coupled to the reference voltage Vref, and its gate receives the enable signal Enb. The Enbk number can be set to logic high to disable the voltage generator ho or set to logic low to enable the Voff voltage generator 350. Resistors 612, 614, 616, and 618 are coupled in series and coupled between the drain of PMOS transistor 610 and the circuit ground. The bottom ends of the resistors 612, 614 and 616 are respectively provided with v 〇 ff4,

Voff3 and Voff2. One end of the switches 622, 624, and 626 is connected to the node z and the other end thereof receives Voff4, Voff3, and Voff2, respectively. The switch 628 is coupled between the defect Z and the circuit ground. Switches 622, 624, 626, and 628 are opened and closed by S1, S2, S3, and S4 control signals, respectively. The decoder 63 0 can receive the B1 to BK control signals of the K amplifier stages 310 of Figure 3. The decoder 630 can generate the S 1 to S4 control signals based on the control signal that can be output to the 6 control signals. Figure 6 shows an illustrative design of a voltage generator 350 that sets the Voff voltage to one of four possible values. Resistors 612 ' 614, 616, and 61 8 may have appropriately selected values to obtain four desired Voff values. The Voff voltage generator 350 can also be implemented by other exemplary designs. In general, a device can include multiple amplifier stages to amplify an input signal and provide an output signal 'e.g., as shown in FIG. The plurality of amplifier stages can be coupled in parallel and can include at least one switchable amplifier stage. Each of the switchable amplifier stages can be operated in an on state or in an off state and can include a gain transistor connected to a stacked transistor. The gain transistor amplifies the input signal in an on state and provides an amplified signal, and can be in a cut-off state without amplifying the input signal. The spliced transistor can buffer the signal amplified by 145291.doc •16· 201110540 and provide an output signal in the on state, and can be deactivated based on the cut-off voltage in the off state. The cutoff voltage can be greater than zero volts or can have any of a number of possible values. The cut-off voltage can also be less than the threshold voltage of the stacked transistor. This enables at least one amplifier stage whenever the device is transmitting '. The at least-switchable amplifier stage can be enabled or disabled to achieve a target round-trip signal level. The inductor can be coupled between the output of all amplifier stages and the supply voltage. The output signal can then have a voltage swing below and above the supply voltage. In an exemplary design, the first voltage generator can generate a cut-off voltage based on the output signal level. The plurality of possible values of the cutoff voltage (which may include zero volts) may be associated with a plurality of ranges of output signal levels. The cut-off voltage can be set to a value determined based on the range covering the current output signal level. In an exemplary design, the first power generator can receive at least one control signal for the at least one switchable amplifier stage and can generate a cutoff voltage based on the at least one control signal. Each control signal can set the corresponding switchable amplifier stage to an on state or an off state. In an exemplary design, the first voltage generator can include a plurality of resistors coupled in series and providing the plurality of possible values of the cutoff voltage, for example, as shown in FIG. In an exemplary design, each switchable amplifier stage may further comprise an inverter (as shown in FIG. 3) or a buffer (which may be formed by a cascade of two inverters) for receiving The control signal of the amplifier stage is switched and a control voltage for the stacked transistor is provided. The inverter/buffer can be coupled between the turn-on voltage (e.g., vdd or Von) to enable the stacked transistor and the voltage to cut off I45291.doc 17 201110540. Each switchable level further includes: (1) a resistor coupled between the output of the inverter/buffer and the gate of the stacked transistor, and (11) a capacitor coupled Connected between the gate of the stacked transistor and the circuit ground. The second voltage generator can receive the output signal and generate a turn-on voltage for the inverter/buffer in each switchable amplifier stage. The gain transistor and the stacked transistor of each switchable amplifier stage can be implemented by an NMOS transistor (as shown in Figure 3), a pM〇s transistor, or other type of transistor. The cut-off electric grinder and the turn-on voltage can be set to different values for different types of transistors. Figure 7 shows an exemplary design of a procedure 7 for operating an amplifier. The input signal can be amplified by the gain transistor in the on state to obtain the amplified L number (block 7 12) » The amplified signal can be buffered by the stacked transistor in the on state to obtain an output signal ( Block 714). The stacked transistor can be turned off by a cut-off voltage in a cut-off state, wherein the cut-off voltage is greater than zero volts or has one of a plurality of possible values (block 716). In the example of the generation of the temperature, the cut-off voltage can be generated based on the output signal level (block 7 8). The cut-off voltage β can be set to the output signal level below the threshold. Zero volts, or a value greater than zero volts if the output signal level is greater than the threshold. The control voltage of the laminated transistor can be set to cut off the electric house in the off state, or set to the on voltage in the on state. The turn-on voltage can be generated based on the output signal or can be set to a predetermined value (e.g., Vdd;). In an exemplary design, at least one of the plurality of amplifier stages connected in parallel can be enabled and the remaining amplifier stages can be disabled. Each amplifier stage can be packaged 145291.doc •18- 201110540 with gain transistor and stacked transistor. The stacked transistors in each of the disabled amplifier stages can be deactivated by switching off the voltage. The cutoff voltage can be generated based on which of the at least amplifier stages is enabled in the plurality of amplifier stages. The amplifiers described herein can improve the reliability of a deactivated transistor that can be coupled to the same output node as the output node to which the enabled transistor is coupled. The gate of a deactivated transistor can be coupled to a low voltage (not circuit ground) when RF amplification by the transistor is not required. The Voff voltage can be programmable (e.g., via a serial bus interface)' such that a larger Voff value is available for a larger output signal level, and vice versa, for example, as shown in FIG. Computer simulations were performed for the exemplary amplifier design shown in Figure 3. Computer simulations show negligible RF performance degradation (in terms of gain, power 'linearity, and noise) in the higher output signal range where the Voff voltage is greater than 〇 V. The amplifier can therefore improve the reliability of the disabled transistor without sacrificing RF performance and leakage current. The amplifiers described herein can be implemented on 1C, analog 1C, RFIC, mixed signal 1C, ASIC, printed circuit board (PCB), electronics, and the like. The amplifier can also be used by various technologies such as CMOS, NM0S, PM0S, Bipolar Junctional Transistor (BJT), Bipolar CMOS (BiCMOS), germanium (SiGe), gallium arsenide (GaAs), etc. The device implementing the amplifiers described herein may be a stand-alone device or may be part of a larger device. A device may be (1) independent I (:; (ii) may include memory for storing data and/or instructions. 1 (: a set of one or more 1C; (丨 (1) such as RF Receiver (RFR) 4 RF Transmitter / Receiver (rtr) rFIC; 145291.doc • 19· 201110540 (v) can be embedded in other devices wireless Device, cell phone or (iV) ASIC such as Mobile Station Data Machine (MSM); module within; (vi) receiver, cellular phone, mobile unit, (Vii), etc. in - or multiple illustrative settings In the context, the functions described may be implemented in hardware, human body, orthography, or any combination thereof. If implemented in software, the powers may be used as one or more instructions or code on a computer readable medium. Storing or transmitting via it. Computer readable media includes computer storage media and communications (4), communication media This includes any medium that facilitates the transfer of a computer program from one location to another. The storage medium can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include ROM, EEPROM, CD - ROM or other optical storage device, disk storage device or other magnetic storage device, or any other medium that can be used to carry or store the desired code in the form of an instruction or data structure and accessible by a computer. Any connection is called a computer readable medium. For example, if you use coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), 4 wireless technologies such as infrared, wire, radio and microwave from the website, server or Other remote source transmission software, coaxial cable, fiber optic cable, twisted pair, mouse 'or wireless technology such as infrared, radio and microwave are included in the definition of the media. As used herein, the disk and the optical disk include compression. Optical discs (CDs), laser discs, compact discs, digital versatile discs (DVDs), flexible discs and Blu-ray discs, where the disc is usually magnetic The material is reproduced in a manner that optically reproduces the material by laser. The combination of the above should also be included in the scope of computer readable media. The foregoing description of the present invention is provided to enable anyone skilled in the art to enter the 14529I. The present invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the examples and designs described herein, but rather the broadest scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a block diagram of a wireless communication device; Figure 2 shows a schematic diagram of an amplifier; Figure 3 shows a schematic diagram of an amplifier with improved reliability; Figure 4 shows oxide lifetime versus drain to gate A graph of voltage (Vdg); Figure 5 shows a programmable voltage cutoff versus output signal level; Figure 6 shows a schematic diagram of a cutoff voltage generator; and Figure 7 shows a procedure for operating an amplifier. [Main component symbol description] 100 Wireless communication device 110 Data processor 112 Memory 120 Transceiver 130 Transmitter 132 Amplifier (Amp) 134 Low pass j filter 136 Variable gain amplifier (VGA) 138 Mixing 140 Filter 145291 .doc 201110540 142 Driver Amplifier (DA) 144 Power Amplifier (PA) 146 Duplexer/Switch 148 Antenna 150 Receiver 152 Low Noise Amplifier (LNA) 154 Bandpass Filter 156 Mixer 158 VGA 160 Low Pass Chopper 162 Amplifier 170 Local Oscillator (LO) Generator 172 Phase Locked Loop (PLL) 200 Amplifier 210a Amplifier Stage 210b Amplified Is Stage 210k Amplifier Stage 212 N Channel Metal Oxide Semiconductor (NMOS) Transistor / Gain Transistor 214 NMOS Crystal / lapped transistor 220 inverter 222 resistor 230 inductor 300 cascading amplifier 310a amplifier stage 145291.doc -22- 201110540 310b amplifier stage 310k amplifier stage 312 N-channel MOS transistor / gain transistor 314 NMOS transistor / stacked transistor 320 inverter 322 resistor 324 capacitor 330 inductor Is 340 Von Voltage generator 350 Voff voltage generator 610 P-channel MOS transistor 612 resistor 614 resistor 616 resistor 618 resistor 622 switch 624 switch 626 switch 628 switch 630 decoder A1 node A2 node AK node B1 control Signal 145291.doc -23- 201110540 B2 Control signal BK Control signal Enb Enable signal SI Control signal S2 Control signal S3 Control signal S4 Control signal Vdd Power supply / supply voltage Vin Input signal Voff Cut-off voltage Voffl Cut-off voltage Voff 2 Cut Break voltage Voff 3 cutoff voltage Voff 4 cutoff voltage Von turn-on voltage Vout output signal Vref reference voltage X node Y node z node 145291.doc -24-

Claims (1)

201110540 VII. Patent Application Range: 1. A device comprising: a plurality of amplifier stages for amplifying an input signal and providing an output signal, the plurality of amplifier stages being coupled in parallel and comprising at least one switchable release The stage 'each switchable amplifier stage operates in an on state or a off state and includes a gain transistor for amplifying the input signal and providing an amplified signal in the on state' The input signal is not amplified in the off state, and a stacked transistor is coupled to the gain transistor and used to buffer the amplified signal and provide the output signal in the on state. The spliced transistor is deactivated in the off state based on a cutoff voltage that is greater than zero volts or has one of a plurality of possible values. 2. The device of claim 1, further comprising: a voltage generator for generating the cutoff voltage based on an output signal level. 3. The apparatus of claim 2, wherein the plurality of possible values of the cutoff voltage are associated with a plurality of ranges of output. signal levels, and the cutoff voltage is set to an I to cover the output signal level The value determined by one of the ranges. 4. The device of claim 1, further comprising: a voltage generating benefit for receiving at least one control signal for the at least one switchable amplification stage and for generating the slice based on the at least one control signal Breaking voltage 'each control signal sets a corresponding switchable amplification 145291.doc 201110540 to the on state or the off state. 5. The device of claim 1, further comprising: a voltage generator A plurality of resistors are included, the plurality of resistors being connected in series and providing the plurality of possible values of the cutoff voltage. 6. The device of claim 1, wherein the plurality of possible values of the cutoff voltage comprises zero volts. 7. The device of claim 1, wherein the cut-off voltage is less than a threshold voltage of the stacked transistor. 8. The apparatus of claim 1, each switchable amplifier stage further comprising an inverter or a buffer for receiving a control signal for the switchable amplifier stage and for providing - for The control circuit of the spliced transistor is connected to a turn-on voltage for enabling the spliced transistor and the cut-off power for deactivating the spliced transistor 9. The device of claim 8 wherein the 'each-switchable amplifier stage further comprises a second resistor' that is coupled between the inverter or an output of the buffer and is connected between a gate of the transistor And a capacitor 'coupled between the stacked grounds. and the gate of the next day is connected to the circuit. 10. The device of claim 8 further includes a number and is generated for each rush. The on-voltage-voltage generator of the device is configured to receive the inverter in the turn-off-switchable amplifier stage or the further comprising: 11 - as claimed in claim 1 145291.doc 201110540 An inductor 'between the output of the plurality of amplifier stages and a supply voltage' The output signal has a voltage swing below and above the supply voltage. 12. 13. 14. 15. 16. The device of claim 1, wherein at least one of the plurality of amplifier stages is transmitting while the device is transmitting The device is enabled, such as the device of claim 1, the at least one switchable amplifier stage is enabled or disabled to obtain a target output signal level. An integrated circuit comprising: an amplifier stage for amplifying An input signal and an output nickname, the plurality of amplifier stages being coupled in parallel and including at least one switchable amplifier stage, each switchable amplifier stage operating in an on state or a off state and including a gain a crystal for amplifying the input signal in the on state and providing an amplified signal, and for not amplifying the input signal in the off state, and a stacked transistor coupled to the gain a transistor for buffering the amplified signal and providing the output signal in the on state, the spliced transistor being deactivated based on a cutoff voltage in the off state, the cutoff voltage being large At zero volts or having one of a plurality of possible values, such as the integrated circuit of claim 14, further comprising: a voltage generator for generating the cut-off voltage based on an output signal level. The integrated circuit of item 14, wherein the gain transistor and the stacked transistor comprise an N-channel gold oxide semiconductor (NM〇s) transistor or a germanium channel gold oxide semiconductor 145291.doc 201110540 body (PMOS) transistor. a method comprising: amplifying a round-up by a gain day in an on state to obtain an amplified signal; rolling in a 乜唬 to connect the 乜唬 in the on state And connecting the amplified signal to the output signal and receiving the output signal by a cut-off voltage in a cut-off state, the cut-off voltage being greater than zero volts or more One of the possible values. 18. The method of claim 17, further comprising: generating the cutoff voltage based on an output signal level. 19. The method of claim 18, wherein the generating the cutoff voltage comprises setting the cutoff voltage to zero volts if the output signal level is below a threshold, and the output signal level is greater than In the case of the threshold, the cut-off voltage is set to a value greater than zero volts. 20. The method of claim π, further comprising: generating a turn-on voltage based on the output signal; and setting a control voltage of the one of the stacked transistors to the cut-off voltage in the cut-off state, or This on-voltage is set in the on state. 21. The method of claim 17, further comprising: enabling at least one of a plurality of amplifier stages coupled in parallel, each amplifier stage including the gain transistor and the stacked transistor; and by the cutting The voltage disables the stacked transistor in each of the disabled amplifier stages. 22. The method of claim 21, further comprising: generating the cutoff voltage based on which of the plurality of amplifier stages is enabled. 23. An apparatus comprising: means for amplifying an input signal in an on state to obtain an amplified signal; for buffering the amplified signal and providing an output signal in the on state And a member for deactivating the member for buffering by a cut-off voltage in a cut-off state, the cut-off voltage being greater than zero volts or having one of a plurality of possible values. 24. The device of claim 23, further comprising: means for generating the cut-off voltage based on the rounded signal level. 25. The apparatus of claim 24, wherein the means for generating the cut-off voltage comprises means for setting the voltage to zero volts in the case where the output level is below the threshold value, and ' The knives are used to sever the power down to a value greater than zero volts in the event that the turn-off signal bit breaks the 懕-懕s earlier than the 仏 limit. 145291.doc