201110122 TW98025GB 31964twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種快閃記憶體的存取裝置及方 法’且特別是有關於一種雙通道的快閃記憶體的存取裝置 及方法。 【先前技術】 鲁 快閃記憶體(flash memory)是一種電子式的可程式唯 讀記憶體(programmable read only memory)，允許在操作中 多次的被抹除及寫入。常見的快閃記憶體包括有反或閘式 快閃記憶體(NOR flash)以及反及閘式快閃記憶體(NAND flash)。而不論是反或閘式快閃記憶體或是反及閘式快閃記 憶體都有被抹寫的次數限制，以反及閘式快閃記憶體為例 子’ MLC式的反及閘式快閃記憶體的可抹寫次數通常為1 萬次’而SLC式的反及閘式快閃記憶體的可抹寫次數則通 _ 常為10萬次。 在現今的技術中，有一種雙通道(dual channel)的快閃 記憶體的存取裝置。這種習知的雙通道的快閃記憶體存取 裝置在儲存資料時’可以藉由將欲儲存的資料分成兩個部 份。並將這兩個部份的資料，透過不同的通道同時儲存至 不同的快閃記憶體中。如此一來，資料儲存到快閃記憶體 中的速度，有效的變成為兩倍。也就是說，快閃記憶體存 取裝置的存取資料的頻寬也上升為兩倍。 然而，由於快閃記憶體可能會因為抹寫次數過多而損 201110122 TW98025GB 31964twf.doc/n —母的快閃§己憶體存取裝置中，一曰 何一個通道的快閃記^ —虿任 遠的丟失㈣。也3體拍中所儲存的資料將永 取F % 的雙通道的㈣記憶體存 =置很4因為快閃記憶體的損毁，，而導致資料的無法 【發明内容】 本發明提供-種快閃記憶體 雙通道的㈣記憶體也，取裝置及方法’提供 份的功能。道、且，以增加傳輸的頻寬並提供資料備 本發明提出 ~~ ^ 4Φ· ΨΔ a* 1.0-器H、皆閃思體的存取震置，包括控制 、、圯k體組以及第二 獅組透過第一通道轉，弟:通道 以及至少第一記憶體椐奋描匕括弟一快閃圮憶體 器，第一記_體^弟一快閃記憶體耦接控制 二丄==;接:;r記._及_ 憶體包_接控制器的亡===制器。第二通道記 ‘:二體的，來判斷 在本發明之—實施例中；第亡:二^ 記憶體時，控制H更依據勤j體擴錄則連接第四快， 體以及第四快閃記憶體的讀：：二以及快閃” 取或寫入動作的JL常與否，來 201110122 TW98025GB 31964twf.doc/n 規劃各快閃§己憶體為主要S己憶體或是備份記怜、體 在本發明之一實施例中，上述之控制^偵測 憶體的讀取或寫入動作皆為正常時，規金，丨笛—_ ㈤禾 、-快閃印 憶體為主要m並規劃第三、四快閃記憶體為; 憶體。或是規劃第三、四快閃記憶體為主要記憔體，D 劃第一、二快閃記憶體為備份記憶體。其中，_ 規 記憶體組内的快閃記憶體可互為備份記憶體。201110122 TW98025GB 31964twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a flash memory access device and method, and in particular to a dual channel flash memory Access device and method. [Prior Art] Flash memory is an electronic programmable read only memory that allows multiple erases and writes during operation. Common flash memory includes reverse or gated flash memory (NOR flash) and NAND flash memory. Regardless of whether the reverse or gate flash memory or the anti-gate flash memory has a limit on the number of times to be erased, in contrast to the gate flash memory as an example, the MLC-style reverse gate is fast. The rewritable number of flash memory is usually 10,000 times' and the rewritable number of SLC type anti-gate flash memory is usually 100,000 times. In today's technology, there is a dual channel flash memory access device. This conventional two-channel flash memory access device can be divided into two parts by storing the data. The data of these two parts are simultaneously stored in different flash memories through different channels. As a result, the speed at which data is stored in the flash memory is effectively doubled. In other words, the bandwidth of the access data of the flash memory access device is also doubled. However, because the flash memory may be damaged due to too many erasing times, 201110122 TW98025GB 31964twf.doc/n - the mother's flash § 己 体 存取 存取 , , , 己 己 , , , , 一个 一个 一个 一个 一个 一个 一个 一个 一个 一个 一个 一个Lost (four). Also, the data stored in the 3 body beats will always take F% of the two-channel (4) memory storage = set to 4 because the flash memory is damaged, and the data cannot be obtained. [Invention] The present invention provides The flash memory dual-channel (four) memory also takes the device and method to provide the function of the share. In addition, in order to increase the bandwidth of the transmission and provide data, the present invention proposes that the ~~^4Φ· ΨΔ a* 1.0-device H, the access oscillators of the flash body, including the control, the 圯k body group and the The second lion group turned through the first channel, the brother: the channel and at least the first memory 椐 匕 匕 匕 一 一 一 一 一 一 一 一 一 一 一 , , , , , , , , , , , , , 一 一 一 一 一 一 一 一=; Connect:; r remember. _ and _ memory pack _ connected to the controller of the death === controller. The second channel is recorded as 'two-body, to judge in the embodiment of the present invention; the first is: two ^ memory, the control H is connected to the fourth fast, the body and the fourth fast according to the physical expansion. Flash memory reading:: 2 and flash" JL of the take or write action is often or not, to 201110122 TW98025GB 31964twf.doc/n Planning each flash § 己 体 为 为 为 或是 或是 或是 或是 或是 或是 或是 或是 或是 或是 或是 或是In an embodiment of the present invention, when the above-mentioned control/detection memory reading or writing operation is normal, the rule gold, the whistle--(5)he, the fast flash memory is the main m And plan the third and fourth flash memory for; recall the body, or plan the third and fourth flash memory as the main memory, D draw the first and second flash memory as the backup memory. The flash memory in the memory group can be backup memory for each other.
在本發明之一實施例中，上述之第快閃記憶體_ 備份第一快閃記憶體中所儲存的資料，卫14τ it且弟四快閃記情髀 用以備份第二快閃記憶體中所儲存的資料。 在本發明之一實施例中，上述之第一快閃記憶體用以 備份第三快閃記憶體中所儲存的資料，且第二快閃^己立_ 用以備份第四快閃記憶體中所儲存的資料。、A °己’〖思體 在本發明之一實施例中，上述之控制器在偵測第一 道記憶體组_的快閃記憶體的讀取或寫入動作為不正a 時，規劃第二快閃記憶體為主要記憶體並規劃第四快閃1 憶體為該備份記憶體。或是規劃第四快閃記憒體為 ^ 憶體並規劃第二快閃記憶體為備份記憶體。_ 在本發明之一實施例中，上述之控制器在偵測第二、南 道記憶體組中的快閃記憶體的讀取或寫入動作為不正^ 時，規劃第一快閃記憶體為主要記憶體並規劃第三快1 憶體為備份記憶體。或是規劃第三快閃記憶體為主要 體並規劃第一快閃§己憶體為備份記憶體。 ’ 一通道記憶體 在本發明之一實施例中，上述之第一、 201110122 TW98025GB 31964twf.doc/n 組與控制器皆配置在相同的電路基板上。 在本發明之一實施例中，上述之第一通道記憶 控制器皆配置在姉的祕基板上，第二通道記組^ 開放式反及閘快閃記憶體介面組。 、、一 在，發明之一實施例中，上述之控制器配置在電路基 t面ίτ、二通道記憶體組都為開放式反及閘快閃記ί 在本發明之-實施例中’上述之控制器配置在電路某 開放式反及閘快閃_ 本發明另提出-種快閃記憶體的存取方法，包In an embodiment of the present invention, the first flash memory _ backs up the data stored in the first flash memory, and the data stored in the first flash memory is used to back up the second flash memory. Stored information. In an embodiment of the present invention, the first flash memory is used to back up data stored in the third flash memory, and the second flash memory is used to backup the fourth flash memory. The information stored in it. In one embodiment of the present invention, when the controller detects that the read or write operation of the flash memory of the first memory group is not correct, the plan is The second flash memory is the main memory and the fourth flash 1 memory is planned as the backup memory. Or plan the fourth flash memory to be the memory and plan the second flash memory as the backup memory. In an embodiment of the present invention, the controller is configured to detect the first flash memory when detecting that the read or write operation of the flash memory in the second and south memory groups is not correct. As the main memory and plan the third fast 1 memory as backup memory. Or plan the third flash memory as the main body and plan the first flash § recall as the backup memory. One Channel Memory In one embodiment of the present invention, the first, 201110122 TW98025GB 31964twf.doc/n group and the controller are all disposed on the same circuit substrate. In an embodiment of the invention, the first channel memory controller is disposed on the secret substrate of the crucible, and the second channel group is an open anti-gate flash memory interface group. In one embodiment of the invention, the controller is configured on the circuit base t ίτ, and the two-channel memory group is an open reverse gate flash ί. In the embodiment of the present invention, the above The controller is configured in the circuit to open an anti-gate and flash flash _ the invention further proposes a method for accessing the flash memory, the package
先’提供控制器對第-通道記憶體組中的第―、U ，以及第二通道記憶體組中第三、四快閃記憶體進二 =或寫入動作。接著，控制器依據該讀取或寫 斷 第一、二通道記，隨組心_記賴是否正常。 ΐ!器依快閃記憶體是否正常來規劃各快閃記，體為 主要記憶體或是備份記憶體。 亡體為 來：二本 :記憶體中的資料可以得到備分。並五，： 為抹寫次數過多而導致_時 因 料。另外，本發明也藉由偵測快:=== =正確j否’來規劃雙通道記憶體組 個伊 體，使多個快閃記憶體分別成為儲存資料的主要= 201110122 TW98025GB 31964twf.d〇c/n 以及備伤主要憶體巾的資料的 可1=有未損毁的_二= 舉實施例，她合㈣，下文特 【實施方式】First, the controller provides a second or fourth flash memory in the first, fourth, and second channel memory groups in the first channel memory group. Then, the controller reads or writes according to the first and second channel records, and whether the group _ is recorded as normal. ΐ! Depending on whether the flash memory is normal or not, plan each flash, which is the main memory or backup memory. Dead body is coming: two books: the data in the memory can be reserved. And five,: In order to smear too many times, it leads to _. In addition, the present invention also plans a dual channel memory group by means of detecting fast: === = correct j no ', so that multiple flash memories become the main data stored separately = 201110122 TW98025GB 31964twf.d〇 c/n and the information of the main body towel for the injury can be 1 = there is no damage _ two = example, she combined (four), the following special [embodiment]
記情圖1 ’圖W示本發明的—實施例的快間 由VJ"衣5100的示意圖。快閃記憶體的存取裝置 、酋㈣1111G、第—通道記憶體組12G以及第二通 體、、且130。另外，控制器11〇透過第一通道15〇耦 接弟一通道記龍組12G，並邱制器⑽透過第二通道 160 2接第^通道記鍾組13()。第—通道記紐組㈣ 已括快閃記紐121及記憶體擴充槽122，第二通道纪 ^體^ no切包括㈣記憶體131及記憶體擴充槽 !·夬閃疏體m及記憶體擴充槽m墟並祕至控 制器iig，㈣記憶體131卩記憶體擴錢132也相互麵 接並耦接至控制器11〇。 當記憶體擴充槽122、132都未連接任何記憶體時， 控制器no依據偵測記憶體擴充槽122、132並盔插入快閃 記憶體的狀態，以藉由第-通道15G及第二通道16〇來分 別針對快閃記憶體121、132進行所謂的雙通道的方式進行 取存。 在另一方面，若是記憶體擴充槽122、132如圖】所 纷示的分別連接快閃記憶體m及133，且快閃記憶體的 201110122 TW98025GB 31964twf.doc/n 存取裝置100進行實際的操作時，控哭 122'132 μ， 、據偵測记 ^ 3〇中的快閃記㈣121、123、 怏閃記憶體m、123、m 明’也就是控制器m會針對快閃記憶體i2i、12(、= $ 13=行讀取或寫入等動作’而當控胸ιι〇針對例如 士 ；體121進行讀取或寫人等動作可以正常的進行 閃記㈣a並未損毁。而當控制器110針對 例如快閃記髓121進行讀取或寫 f 行時，則表示快閃記憶體121已經損毁。’…㊉的進 控制器110接著則依據其所判斷出的快 ^，、⑶及⑺的讀取或寫人動作的正常與否= =規劃各快閃記憶體為主要記憶體或是備份記憶體。其 :=記憶體用來儲存所要儲存㈣料，而備份記憶體 則疋用來備份主要記憶體中所儲存的資料。 值传-提的S ’控制器110會定時的針對快閃記憶體 、123、131及133進行的讀取或寫入動作的正常 ^貞測動作。原因是在於快閃記憶體是會因為多次的抹寫 J作而損毀的。因此’控制器11〇必需要能夠掌控快閃記 體的存取裝置100中的快閃記憶體12卜丨23、13丨及133 T否=生損毁’並祕職各,_記憶縣主要記憶體或 疋備份記憶體。 以下則針對本實施例中的控制器丨1〇依據其所判斷的 201110122 TW98025GB 3l964twf.doc/n 快閃記憶體121、123、13〗及133淮广 + 1及133進仃的讀取或寫入動作 =吊，否來進行快閃記憶、體12卜123、131 * 133的規 f式來朗’駿本領域具通f知識者更能清楚瞭解本 實施的動作細.節^ 〜LISTING FIG. 1 'B shows a schematic diagram of the instant of the present invention by VJ" garment 5100. The flash memory access device, the Emirates (4) 1111G, the first channel memory bank 12G, and the second body, and 130. In addition, the controller 11 is coupled to the first channel channel group 12G through the first channel 15 and the second channel 160 2 to the second channel group 13 (). The first channel identification group (4) has included the flash flashing neon 121 and the memory expansion slot 122, and the second channel is the body ^ no cut includes (4) the memory 131 and the memory expansion slot! · 夬 flashing body m and memory expansion The slot m is secreted to the controller iig, and (4) the memory 131 memory stack 132 is also interfaced with each other and coupled to the controller 11A. When none of the memory expansion slots 122, 132 are connected to any memory, the controller no is based on the detection memory expansion slots 122, 132 and the helmet is inserted into the flash memory state by the first channel 15G and the second channel. In the meantime, the so-called two-channel method is performed for the flash memories 121 and 132, respectively. On the other hand, if the memory expansion slots 122, 132 are respectively connected to the flash memory m and 133 as shown in the figure, and the flash memory of the 201110122 TW98025GB 31964twf.doc/n access device 100 is actually implemented. During operation, the control cries 122'132 μ, according to the detection flash 3 (four) 121, 123, 怏 flash memory m, 123, m Ming 'that is, the controller m will be for the flash memory i2i, 12 (, = $ 13 = line read or write actions, etc.) and when the chest is ιι〇 for, for example, the body 121 reads or writes the person can perform normal flashing (4) a is not damaged. When 110 reads or writes f lines for, for example, the flash memory 121, it indicates that the flash memory 121 has been destroyed. '... The controller 110 of the ten is then based on the fast ^, (3), and (7) Read or write the normality of the person's action == Plan each flash memory as the main memory or backup memory. It: = memory is used to store the (4) material to be stored, and the backup memory is used for backup. The data stored in the main memory. The value of the S-controller 110 will be fixed The normal detection operation for the read or write operations of the flash memory, 123, 131, and 133. The reason is that the flash memory is damaged due to multiple erases. Therefore, ' The controller 11 must have the flash memory 12 in the access device 100 capable of controlling the flash memory. 12, 23, 13 and 133 T No = loss of life and secret service, _ memory county main memory or 疋Backup memory. The following is for the controller 本1〇 in this embodiment according to its judgment 201110122 TW98025GB 3l964twf.doc/n flash memory 121, 123, 13 and 133 Huaiguang + 1 and 133 Read or write action = hang, no to flash memory, body 12 Bu 123, 131 * 133 gauge f to Lang 'Junben field with a knowledge of the knowledge can better understand the implementation of this implementation details. ^ ~
、請同時參照圖1及圖2，圖2繪示為當控制器11〇偵 =快閃§己憶體121、123、131及133的讀取或寫入動作 皆可以正常進行時’所可能進行的四種分配方式。其中， 控制盗110可以規劃快閃記憶體121與快閃記憶體13丨(如 連線210)為主要記憶體，相對的’此時的快閃記憶體123 f !夬閃5己彳思體133則為備份記憶體。其中的快閃記憶體123 可以用來備份快閃記憶體121中的資料，當然，快閃記憶 體133可以用來備份快閃記憶體131中的資料。控制器110 也可以規㈣閃記憶體123與快閃記憶體133〇連線220) ^主要記髓’相料，此時的糾記憶體m與快閃記 I"思體131則為備份記憶體。其中的快閃記憶體121可以用 來備份快閃記憶體123中的/資料，當然，快間記憶體131 可以用來備份快閃記憶體133中的資料。 二另外，控制器110也可以規劃快閃記憶體121與快閃 。己憶體133(如連線23〇)為主要記憶體，相對的，此時的快 閃dfe體123與快閃記憶體ι3ι則為備份記憶體。其中的 =閃記憶體123可以用來備份快閃記憶體121中的資料， =然，快，記憶體131可以用來備份快閃記憶體133中的 貝料。或是，控制器110也可以規劃快閃記憶體123與快 閃C憶體131(如連線24q)為主要記憶體，相對的，此時的 201110122 TW98025GB 31964twf.doc/n ==快閃記憶體133則為備份記憶體。其中 S t = 來備份快閃記憶體m中的資 快閃，己憶體133可以用來備份快閃記憶體i3i 及133都^不難得知’當快閃記憶體12卜123、131 控制器110可以規劃第-通道記憶體 二=:7閃記憶體作為主要記憶體，而規劃第 體。並且‘V二120中另—個快閃記憶體作為備份記憶 體。並且，控制器U〇同時 的任-個快閃記憶體作為二通道記憶體組130中 马要5己體，而規劃第二通道記 i快門快閃記憶體作為備份記憶體。如此- ΐ存取裝置1〇0可以保持雙通道的存取方 己憶體組12G、13G的主要記憶體中。 體的心注意的，在備分記憶體進行備份主要記憶 ^的^方式中，控制器11G可以依據固定的時間週期，’ :^要記鐘中的資料複製至備份記紐。也就是說，控 制益110可依據計數器(未緣示)來計算時間，並在計數器 的計數值等於上述的蚊的時間職時，進行複製主要記 憶體中的資料至備份記憶體的動作，使主要記憶體中的資 料可以隨時的得到備分，確保資料的安全性。 、當然，上述的資料備份的方法僅只是一個實施範例， ，不代表本發明一定要使用這樣的方式來進行資料的 份。凡本領域具通常知識者所熟知的資料備份方法，也都 201110122 TW98025GB 31964twf.doc/n 可以使用在本發明的實施例上。 在另方面，由於控制器Π0會即時的偵剛快閃記憶 體的讀取或寫入動作的正常與否以即時掌握快、^ -⑵、123、131及133的狀態，—旦作為主要記憶體· 閃記憶體(例如快閃記憶體121)損毁時，控制器11〇則重新 規劃原本作為快閃記憶體121的備分記憶體的快閃記憶體 123為主要記憶體，並使快閃記憶體的存取裝置忉〇 • 繼續的正常動作。 請繼續參照圖1，若是控制器110偵測出第一通道記 憶體組120中的快閃記憶體121、123的讀取或寫入動作為 不正常時，控制器U0則規劃第二通道記憶體組13〇的 快閃δ己憶體131、133的其中之一為主要記憶體，並規割# 一通道記憶體組130中的快閃記憶體131、133中的另一弟 為備份記憶體。相同的，若是控制器11〇偵測出第二、爾们 記憶體組130中的快閃記憶體131、133的讀取或寫入=道 為不正常時，控制器11〇則規劃第一通道記憶體組= • 的快閃記憶體丨21、123的其中之一為主要記憶體，並規則 第二通道記憶體組12〇中的快閃記憶體121、123中的另1 個為備份記憶體。 接著請參照圖3，圖3繪示本發明的另一實施例的快 閃記憶體存取裝置3〇〇的示意圖。快閃記憶體存取裝置3〇〇 包括控制器310、第一通道記憶體組320以及第二通道記 憶體組330。第一通道記憶體組32〇中則包括快閃記憶體 321及s己憶體擴充槽322，而另外第二通道記憶體級3% 201110122 TW98025GB 31964twf.doc/n 中則包括快閃體331及332。並且，與上一實施例不 相同的，第二通道記憶體組330中還包括多數個的記憶體 擴充槽332、333。其中，記憶體擴充槽332、333與控制 器310、快閃記憶體331及記憶體擴充槽322相耦接，用 來連接更多的快閃記憶體。而記憶體擴充槽333所連接的 快閃記憶體則可以用來作為備分記憶體。另外，第一通道 記憶體組320中也同樣可以配置多數個的記憶體擴充槽。 在此特別說明，上述的實施例中的控制器31〇、通 記憶體組320、33 0可以皆配置在例如是主機板的電路 上。或者將控制器310配置在電路基板上，而通道記 組320則可以與控制—起配置在相同的電路反 上，其中的通道記缝k 制放献及·閃記= 介面組。再或者是將控制器31〇配置電路基板上，:音 記憶體組32G、33G為式反及縣閃記憶體 = 中的if己憶體纟且挪、·可以但不必要與控制哭^ 被配置在同一電路基板上。 310 以下請參照圖4，圖4緣示本發明的再—實沾 閃記憶體，存取方法的流賴。其巾的步驟包括參，，、 提供控制器對第-通道記憶體組中的第―、 ’ 以及第二通道記怜體袓中—决閃圮憶體 寫入動作_):著中二 ^ 、、接者控制斋依據讀取或寫入動作到齡 一、道記憶體組中的快閃記憶體是否正 2:主快閃記憶體是否正常來規劃各丄二 體為要屺丨思體或是備份記憶體(S43〇)。 心 12 201110122 TW98025GB 31964twf doc/n ，另外’關於本實施例中’控制器依據快閃記憶體是否 正系來規t!各快閃記憶體為主要記憶體或是備份記憶體的 方法在前述本發明的快閃記憶體的存取裝置1〇〇及3〇〇的 兩個實—施例中都有清楚的說明，此處則不再多加贅述。 紅上所述，本發明提出一種雙通道記憶體組的快閃記 憶體的存取f置及存取方法，並依據第―、二通道記憶體 組中的快閃記憶體的損毁與否來規劃各快閃記憶體為主要 。己隐體或是備份記憶體。使主要記憶體巾所儲存的資料都 可、^皮備伤而不至於这失。並且在主要記憶體損毁時，可 乂動^^的切換備帛記憶體成為主要記憶體，維持快閃記憶 體的存取裝置的正常動作。 一 雖穌發明已以實_猶如上，然其並_以限定 $明’任何所騎術領域中具有通f知識者，在不脫離 ^明之精神和範_，#可作些許之更動與潤飾，故本 X明之保賴圍當視後附之巾請專職圍所界定者為準。 【圖式簡單說明】 圖1綠示本發明的—實施例的快閃記憶體的存取 1υϋ的示意圖。 劃方閃記憶體的存取裝置100的快閃記憶體規 300^=本發明的另一實施例的快閃記憶體存取裝置 圖4綠示本發明的再一實施例的快閃記憶體的存取方 13 201110122 TW98025GB 31964twf.doc/n 法的流程圖。 【主要元件符號說明】 100、300 :快閃記憶體的存取裝置 110、310 :控制器 120、 320 :第一通道記憶體組 130、330 :第二通道記憶體組 121、 123、131、133、321、331 :快閃記憶體 122、 132、322、332、333 :記憶體擴充槽 210〜240 :連線 150、160 :通道 S410〜S430:快閃記憶體的存取方法的步驟Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 shows that when the controller 11 detects/flashes, the reading or writing operations of the memories 121, 123, 131, and 133 can be performed normally. The four distribution methods that are performed. Among them, the control thief 110 can plan the flash memory 121 and the flash memory 13 丨 (such as the connection 210) as the main memory, the opposite 'flash memory at this time 123 f! 夬 flash 5 彳 彳 body 133 is the backup memory. The flash memory 123 can be used to back up the data in the flash memory 121. Of course, the flash memory 133 can be used to back up the data in the flash memory 131. The controller 110 can also be a backup memory of the (four) flash memory 123 and the flash memory 133 ^ ) ) ^ ^ ^ ^ ^ ^ ^ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , . The flash memory 121 can be used to back up the data in the flash memory 123. Of course, the fast memory 131 can be used to back up the data in the flash memory 133. In addition, the controller 110 can also plan the flash memory 121 and flash. The memory 133 (such as the connection 23 〇) is the main memory. In contrast, the flash dfe body 123 and the flash memory ι3 ι are the backup memory. The flash memory 123 can be used to back up the data in the flash memory 121. If it is fast, the memory 131 can be used to back up the material in the flash memory 133. Alternatively, the controller 110 may also plan the flash memory 123 and the flash C memory 131 (such as the connection 24q) as the main memory. In contrast, at this time, 201110122 TW98025GB 31964twf.doc/n == flash memory Body 133 is the backup memory. Among them, S t = to backup the flash memory in the flash memory m, the memory 133 can be used to backup the flash memory i3i and 133 are not difficult to know 'When flash memory 12 Bu 123, 131 controller 110 can plan the first channel memory 2 =: 7 flash memory as the main memory, and plan the body. And ‘V two 120 another flash memory as a backup memory. Moreover, the controller U 〇 any one of the flash memory as the two-channel memory bank 130 in the two-channel memory group 130, and the second channel is called the shutter flash memory as the backup memory. Thus, the access device 1〇0 can be maintained in the main memory of the dual-channel access memory group 12G, 13G. In the mode of the body's mind, in the backup memory main memory ^ mode, the controller 11G can copy the data in the clock to the backup note according to a fixed time period. That is to say, the control benefit 110 can calculate the time according to the counter (not shown), and when the counter value is equal to the above-mentioned mosquito time, the action of copying the data in the main memory to the backup memory is performed, so that The data in the main memory can be backed up at any time to ensure the security of the data. Of course, the above method of data backup is only an implementation example, and does not mean that the present invention must use such a method to perform a copy of the data. The data backup method well known to those skilled in the art can also be used in embodiments of the present invention. 201110122 TW98025GB 31964twf.doc/n. On the other hand, since the controller Π0 will immediately detect the normality of the read or write operation of the flash memory to instantly grasp the state of fast, ^ - (2), 123, 131 and 133, as the main memory When the flash memory (for example, the flash memory 121) is damaged, the controller 11 re-plans the flash memory 123 originally serving as the backup memory of the flash memory 121 as the main memory, and flashes the flash memory. Memory access device 继续 • Continue normal operation. Referring to FIG. 1, if the controller 110 detects that the reading or writing operation of the flash memory 121, 123 in the first channel memory group 120 is abnormal, the controller U0 plans the second channel memory. One of the flashing δ hexameric bodies 131 and 133 of the body group 13 为 is the main memory, and the other one of the flash memory bodies 131 and 133 in the one-channel memory group 130 is the backup memory. body. Similarly, if the controller 11 detects that the reading or writing of the flash memory 131, 133 in the second memory bank 130 is abnormal, the controller 11 plans to be the first. Channel memory group = • One of the flash memory ports 21, 123 is the main memory, and the other one of the flash memory bodies 121, 123 in the second channel memory group 12 is the backup. Memory. Referring to FIG. 3, FIG. 3 is a schematic diagram of a flash memory access device 3A according to another embodiment of the present invention. The flash memory access device 3 includes a controller 310, a first channel memory bank 320, and a second channel memory bank 330. The first channel memory group 32A includes a flash memory 321 and an suffix expansion slot 322, and the second channel memory level 3% 201110122 TW98025GB 31964twf.doc/n includes a flash body 331 and 332. Further, unlike the previous embodiment, the second channel memory bank 330 further includes a plurality of memory expansion slots 332, 333. The memory expansion slots 332 and 333 are coupled to the controller 310, the flash memory 331 and the memory expansion slot 322 for connecting more flash memories. The flash memory connected to the memory expansion slot 333 can be used as a backup memory. In addition, a plurality of memory expansion slots can be arranged in the first channel memory group 320 as well. Specifically, the controller 31A and the memory banks 320 and 330 in the above embodiments may be disposed on a circuit such as a motherboard. Alternatively, the controller 310 may be disposed on the circuit substrate, and the channel group 320 may be disposed on the same circuit as the control, wherein the channel is marked with a flash and a flash = interface group. Or, the controller 31〇 is arranged on the circuit board, and the audio memory group 32G, 33G is the same as the if memory of the county flash memory = and can be moved, but not necessarily controlled with the crying Configured on the same circuit board. 310. Referring to Fig. 4, Fig. 4 shows the reliance of the access method in the re-flash memory of the present invention. The step of the towel includes a parameter, and provides a controller to the first, the, and the second channel in the first channel memory group, and the second channel is in the middle of the body - the flashing memory is written in the action_): , the receiver controls the fast according to the reading or writing action to the age one, the flash memory in the memory group is positive 2: whether the main flash memory is normal to plan each of the two bodies to be the body Or backup memory (S43〇). Heart 12 201110122 TW98025GB 31964twf doc/n, in addition, 'in the present embodiment, the controller is based on whether the flash memory is positive or not! Each flash memory is the main memory or the backup memory method in the foregoing The two embodiments of the flash memory access device 1〇〇 and 3〇〇 of the invention are clearly illustrated, and will not be further described herein. According to the above description, the present invention provides a method for accessing and accessing a flash memory of a dual channel memory group, and according to the damage of the flash memory in the first and second channel memory groups. Planning each flash memory as the main. Hidden or backup memory. The information stored in the main memory towel can be made and wounded without being lost. When the main memory is damaged, the memory can be switched to become the main memory, and the normal operation of the access device of the flash memory is maintained. Although the invention of the invention has been _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, this X Ming Zhi Bao Lai Wai attached to the towel should be defined by the full-time enclosure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the access of a flash memory of the embodiment of the present invention. Flash memory device for accessing device 100 of square flash memory 300^=Flash memory access device of another embodiment of the present invention. FIG. 4 is a green flash memory of still another embodiment of the present invention. The access method of the 2011 13122 TW98025GB 31964twf.doc/n method. [Main component symbol description] 100, 300: flash memory access device 110, 310: controller 120, 320: first channel memory group 130, 330: second channel memory group 121, 123, 131, 133, 321, 331: flash memory 122, 132, 322, 332, 333: memory expansion slots 210 to 240: connection 150, 160: channels S410 to S430: steps of access method of flash memory