201108307 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明是涉及關於非揮發性記憶體胞元的自會聚底部電 極環的形成，且更特別是關於相改變記憶體胞元。 【先前技術】 [0002] 在電腦記憶體中有兩個主要群組：非揮發性記憶體和揮 發性記憶體。在非揮發性記憶體中為了包持資訊而持續 輸入能源是不需要的，但是在揮發性記憶體中則是需要 的。非揮發性記憶體裝置的範例是光碟（CD和DVD)，磁 性硬碟裝置以及相變化記憶體。揮發性記憶體裝置的範 例包括DRAM (動態隨機存取記憶體）和SRAM (靜態隨機 存取記憶體）。本發明是針對相變化記憶體（phase change memory)和在相位變化記憶體中形成較小纪憶 體胞元的方法。 在相變化記憶體中，資訊是儲存在可以被操控為不同相 。這些相其中之一顯示出可以用在儲存資訊的不同電子 性質。該非晶相和結晶相是典型的用於位元儲存（0與1 資料）的兩個相，此因為他們在電子電阻中具有檢出上 的差異。更特別為’該非晶相具有超過該結晶相為南的 電阻。通常玻璃硫族化合物（glass chalcogenides) 是用於做為相變化材料。這材料的基團包括硫族元素（ chalcogen)(週期表第16/VIA族）以及更多正電性元 素。當設計相變化記憶體胞元時，硒（Se)和碲（Te) 是用在產生玻璃硫族化合物的最常用的半導體基團。此 範例可以是 Ge2Sb2Te5 (GST)、SbTe 以及 In2Se3。然 而，一些項變化材料不同利用硫族元素，像是GeSb。因 098127879 表單編號A0101 第4頁/共24頁 0983285547-0 201108307 此，只要他們可以保留單獨的非晶以及結晶狀態，種種 材料均可以用在相變化材料胞元。 在相變化材料中該非晶和結晶相為可逆的。由於歐姆加 熱，電子脈衝流過相改變材料以熔化該相改變材料。相 對高強度與短持續脈衝導致快速的熔化以及冷卻時間； 該相改變材料沒有時間形成有組織的晶粒，藉此產生非 晶相。相對低強度與長持續脈衝使該相變化材料緩慢冷 卻，於是形成有組織的晶粒且被稱為在該結晶相。= ’較小的項變化區域導致較少需要炫化該相變化材料的 能量。 通常’底部電極是絲載該相變化區域中加熱該相變化 材料。該底部電極的形狀、尺寸與形成影響該底部電極 在提供該相改變材料的相改變所需的電流的有效品質。 因此，其值得去製造最小化需要操作㈣量的底部電極 且提供該相改變材料均勻分布加熱。 【發明内容】 [0003] Ο 098127879 本發明的例示性實施例為一種用於在基材上形成記憶體 胞元結構的方法。該基材可以是但不限制於：裸晶基材 、具有沉積在矽基材的上表面的絕緣材料層的該矽基材 、或是具有在矽基材内所形成的底部接觸的該矽基材。 在該基材上用以形成觀憶體胞元結制該方法必須在 基材上沉積第―絕緣㈣的底賴緣層、在該底部絕緣 層上沉積第二絕緣材料的中介絕緣層以及在該中介絕緣 層上沉積第三絕緣材料的頂部絕緣層。該第二絕緣材料 疋從該第％緣材料可獨立地移除以及該第三絕緣材料 是從該第二絕緣材料可獨立地移除。貫孔形成步驟為在 表單編號A0101 ^ 乐 頁/共 24 頁 0983285547-0 201108307 該頂部絕緣層以及該中介絕緣層中形成貫孔。切口步驟 為在該貫孔中形成切口，致使該頂部絕緣層在該貫孔空 間内突出於該中介絕緣層。 階段間隔件形成步驟為在該貫孔中形成階段間隔件，致 使在該底部絕緣層上產生空腔。該空腔的大小是無關於 該貫孔大小和微影。該空腔的大小是依據該切口和沉積 量。典型地，較大貫孔將得到較多沉積，而較小貫孔將 得到較少沉積。因此，該空腔的關鍵尺寸將自會聚到該 切口的大小。該階段間隔件形成步驟也形成了容納在該 階段間隔件内而延伸到該底部絕緣層的一通道。蝕刻步 驟是在該階段間隔件中的該通道而被延伸穿過該底部絕 緣層和延伸到該基材的頂部表面。在本發明的一特定實 施例中，其該第一絕緣材料和該第三絕緣材料由相同材 料所構成，在該蝕刻步驟期間中該頂部絕緣層也被移除 。底部電極環形成步驟為在該底部絕緣層内的該通道中 形成底部電極環。該底部電極環孢含外部導電材料以及 内部絕緣材料。相變化形成步驟為相變化材料沉積在該 底部電極環上。頂部電極層形成步驟為頂部電極形成在 該相變化材料上。 本發明的另一例示性觀點為一種記憶體胞元結構。該記 憶體胞元結構由基材所構成。該基材可以包括但不限制 於裸矽基材、具有沉積在矽基材的頂部表面的絕緣材料 層的該矽基材、或是具有在矽基材内所形成的底部接觸 的該$夕基材。 該記憶體胞元結構具有在該基材上的底部絕緣層，其由 第一絕緣材料所構成。底部電極環是在該底部絕緣層内 098127879 表單編號A0101 第6頁/共24頁 0983285547-0 201108307 形成。该底部電極環是由杯也丨从^ 个沒外部導電材料以及在 部導電材料内的-内部絕緣#%L ^及在。亥外 科所構成。相變化層是由 相變化材料所構成且在該底部 極展和該底部絕緣層上 ’該底部電極環相較於該相變 戈化層的直徑變化具有較小 的直徑變化。頂部電極層是由道 由導電材料所構成且在該相 變化層上形成。 【實施方式】 [0004] Ο 本發明是以參考第1至11圖而祜 铍描述。當參考這些圖式時 ，整體全部顯示賴似組件是，似的元件符號來指示 。本發明的實施例通常是針對但並未限制在於形成相變 化記㈣（mo裝置的自會聚尺寸（關鍵尺寸）的電極 環。該電極環可以用在PCM裝置中改變相變化狀態。 第1圖表示起始晶圓102。在本發明的特定實施例中，該 起始晶圓是*基材1G4、底部絕緣層1G6、中介絕緣層 108、頂部絕緣層110以及底部接觸112所構成。該基材 ο 可以由_、在#的二氧切或是任何其他前段製程（ front-end-of-line，FE0L)的起始晶圓所構成’其包 括在該晶圓裡面的存取電晶體。該底部接觸112可以由可 以攜帶該PCM裝置的足夠驅動電流的任何導電材料所構成 。在本發明的一特定實施例中，該底部接觸112是由鎢（ W)所構成。 前述三個絕緣層106、1〇8和11〇可以由任何電絕緣材料 所構成，然而具有限制因素。該底部絕緣層1〇6必須從該 中介絕緣層108獨立地可移除，以及該中介絕緣層1〇8必 需從該頂部絕緣層110獨立地可移除。在本發明的一特定 實施例中，該底部絕緣層106是由氮化矽所構成，該中介 098127879 表單編號A0101 第7 1/共24頁 201108307 絕緣層108是由二氧化矽所構成，以及該頂部絕緣層u〇 是由氮化矽所構成。前述三個絕緣層的沉積技術對在此 領域的具有通常知識者為熟知。例如：該沉積可以利用 各種化學氣相沉積（CVD)過程。 現轉向第2圖，貫孔（via) 202在該頂部絕緣層11〇和該 中介絕緣層1G8中形成。該貫孔2Q2的底部是該底部絕緣 層106的頂部表面。該貫孔可以用此領域中具有通常知識 者熟知的微影遮罩和反應性離子㈣（RIE)技術來形成 。在本發明的特定實施例中，該貫孔2〇2直接形成在該底 部電極11 2上。 第3圖顯示在該貫孔202中的切口 3D2的形成。該頂部絕緣 層U〇突出於在該貫孔202内的該令介絕緣層108。此領 域中具有it常知财將瞭解各種濕餘刻 可以施用於形成 切所使用的濕姓刻是根據用在該頂部絕緣層和該 中介絕緣層no的材料。在本發明的實施例中其中該頂 部絕緣層uo是由氮切所構成峨射介絕緣層ι〇8是 由二氧化碎所構成，使用接& 稀乳氟酸（dilute hydro- f 1<： aCld ’贿）〉·顿刻，以便該中介絕緣層108 可以用相較於該頂部絕緣層11Q為非常高的速率而被姓刻 以形成該切口 3 0 2。 在第圖中π度適㈣隔件層術沉積在該頂部絕緣層 110上與沉積在該中介絕緣層108内所容納的貫孔202中 。空腔4Q4在該間隔件層402内且大约到該貫孔202的中 心（請參見第3圖）中形说 ^ 成。该切口 302 (請參見第3圖） 避免該賴件㈣完全填充該貫孔202。該空賴4的直 位疋.’、、關於^孔202的直徑且是兩倍於職在該頂部絕 第8頁/共24頁 098127879 袅單編號A0101 » » „ 09832 201108307 緣層110和該中介絕緣層108之間形成的該切口的直徑。 較大貫孔202將可付到較多的沉積而較小的貫孔go〗可得 到較少的沉積。因此，該空腔404的直徑（關鍵尺寸）將 自會聚到該切口的大小。再者，該關鍵尺寸為無關於微 影。在本發明的實施例中，該間隔件層是由非晶矽所構 成且利用CVD程序而沉積。 第5圖表示階段間隔件502與在該階段間隔件5〇2内的通道 504的形成。該階段間隔件5〇2以及該通道是藉由侧該 Ο 間隔件層402 (請參考第4圖）所形成。該空腔綱（請參 考第4圖）導致該蝕刻穿透到該貫孔2〇2的中心以及在該 階段間隔件4 0 2被蝕刻完之前而蝕刻到在該空腔4 〇 4下的 該間隔件層，因此在該貫孔2_留下—環。該通道5〇4 從該階段間隔件502的頂部延伸到該底部絕緣層1〇6的頂 部表面。該通道504的侧壁為該階段間隔件5〇2。此領域 具有通常知識者將瞭解可以對該蝕刻採用指向性rie程序 〇201108307 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to the formation of self-converging bottom electrode rings for non-volatile memory cells, and more particularly to phase-change memory cells. [Prior Art] [0002] There are two main groups in computer memory: non-volatile memory and volatile memory. Continuous input of energy in order to contain information in non-volatile memory is not required, but is required in volatile memory. Examples of non-volatile memory devices are compact discs (CDs and DVDs), magnetic hard disk devices, and phase change memory. Examples of volatile memory devices include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). The present invention is directed to a phase change memory and a method of forming smaller memory cells in phase change memory. In phase change memory, information is stored and can be manipulated into different phases. One of these phases shows the different electronic properties that can be used to store information. The amorphous phase and the crystalline phase are typically two phases for bit storage (0 and 1 data) because they have a difference in detection in the electronic resistance. More specifically, the amorphous phase has a resistance that is more south than the crystalline phase. Usually glass chalcogenides are used as phase change materials. The groups of this material include the chalcogen (Group 16/VIA of the Periodic Table) and more positively charged elements. When designing phase change memory cells, selenium (Se) and tellurium (Te) are the most commonly used semiconductor groups for the production of glass chalcogenides. This example can be Ge2Sb2Te5 (GST), SbTe, and In2Se3. However, some of the varying materials use different chalcogen elements, such as GeSb. 098127879 Form No. A0101 Page 4 of 24 0983285547-0 201108307 Therefore, as long as they can retain a single amorphous and crystalline state, all materials can be used in phase change material cells. The amorphous and crystalline phases are reversible in the phase change material. Due to ohmic heating, an electron pulse flows through the phase change material to melt the phase change material. Relatively high intensity and short duration pulses result in rapid melting and cooling time; the phase change material has no time to form organized grains, thereby creating an amorphous phase. The relatively low intensity and long duration pulses slow the phase change material, thereby forming organized grains and being referred to as the crystalline phase. = 'The smaller term change area results in less energy to smear the phase change material. Typically the 'bottom electrode' is the filament-loaded phase change region that heats the phase change material. The shape and size of the bottom electrode and the effective quality of the current required to affect the phase change of the bottom electrode in providing the phase change material. Therefore, it is worthwhile to manufacture a bottom electrode that minimizes the need to operate (four) and provides uniform heating of the phase change material. SUMMARY OF THE INVENTION [0003] 例 098127879 An exemplary embodiment of the present invention is a method for forming a memory cell structure on a substrate. The substrate may be, but is not limited to, a bare substrate, the tantalum substrate having an insulating material layer deposited on the upper surface of the tantalum substrate, or the tantalum having a bottom contact formed in the tantalum substrate. Substrate. The method for forming a memory cell on the substrate must be performed by depositing a bottom insulating layer of a first insulating layer on the substrate, an intermediate insulating layer depositing a second insulating material on the bottom insulating layer, and A top insulating layer of a third insulating material is deposited on the dielectric insulating layer. The second insulating material is independently removable from the first edge material and the third insulating material is independently removable from the second insulating material. The through hole forming step is to form a through hole in the top insulating layer and the dielectric insulating layer in Form No. A0101 ^ 乐页 / Total 24 pages 0983285547-0 201108307. The slitting step is to form a slit in the through hole such that the top insulating layer protrudes from the dielectric insulating layer in the through hole space. The stage spacer forming step is to form a step spacer in the through hole to cause a cavity to be formed on the bottom insulating layer. The size of the cavity is irrelevant to the size and lithography of the through hole. The size of the cavity is based on the cut and the amount deposited. Typically, larger vias will get more deposition, while smaller vias will get less deposition. Therefore, the critical dimension of the cavity will self-converge to the size of the slit. The stage spacer forming step also forms a passage that is received in the stage spacer and extends to the bottom insulating layer. The etching step is the passage in the spacer at this stage extending through the bottom insulating layer and extending to the top surface of the substrate. In a particular embodiment of the invention, the first insulating material and the third insulating material are comprised of the same material, and the top insulating layer is also removed during the etching step. The bottom electrode ring forming step is to form a bottom electrode ring in the channel in the bottom insulating layer. The bottom electrode cyclospores contain an outer conductive material and an inner insulating material. The phase change forming step deposits a phase change material on the bottom electrode ring. The top electrode layer forming step is such that a top electrode is formed on the phase change material. Another exemplary aspect of the invention is a memory cell structure. The memory cell structure is composed of a substrate. The substrate may include, but is not limited to, a bare tantalum substrate, the tantalum substrate having a layer of insulating material deposited on a top surface of the tantalum substrate, or the tantalum having a bottom contact formed in the tantalum substrate. Substrate. The memory cell structure has a bottom insulating layer on the substrate, which is composed of a first insulating material. The bottom electrode ring is formed in the bottom insulation layer 098127879 Form No. A0101 Page 6 of 24 Page 0983285547-0 201108307. The bottom electrode ring is made of the cup and the inner insulating material #%L ^ from the outer conductive material and the conductive material. The Wai Wai Branch is composed of. The phase change layer is composed of a phase change material and has a smaller diameter change at the bottom pole and the bottom insulating layer than the diameter change of the phase change geolayer. The top electrode layer is composed of a conductive material and formed on the phase change layer. [Embodiment] [0004] The present invention has been described with reference to Figs. 1 to 11. When referring to these figures, the overall display of the components is a similar component symbol to indicate. Embodiments of the present invention are generally directed to, but not limited to, the formation of phase changes (four) (self-converging dimensions (critical dimensions) of the mo device. The electrode ring can be used to change the phase change state in a PCM device. The starting wafer 102 is shown. In a particular embodiment of the invention, the starting wafer is comprised of a *substrate 1G4, a bottom insulating layer 1G6, an intervening insulating layer 108, a top insulating layer 110, and a bottom contact 112. The material ο can be composed of _, dioxotomy at # or any other front-end-of-line (FE0L) starting wafer, which includes an access transistor included in the wafer. The bottom contact 112 can be constructed of any electrically conductive material that can carry sufficient drive current to the PCM device. In a particular embodiment of the invention, the bottom contact 112 is comprised of tungsten (W). 106, 1〇8 and 11〇 may be composed of any electrically insulating material, however with limiting factors. The bottom insulating layer 1〇6 must be independently removable from the interposing insulating layer 108, and the interposing insulating layer 1〇8 Must be from the top The edge layer 110 is independently removable. In a particular embodiment of the invention, the bottom insulating layer 106 is comprised of tantalum nitride, the interposer 098127879 Form No. A0101, No. 7 1 / Total 24, 201,108,307, the insulating layer 108 is It is composed of cerium oxide, and the top insulating layer 〇 is composed of tantalum nitride. The deposition techniques of the foregoing three insulating layers are well known to those skilled in the art. For example, the deposition can utilize various chemistries. A vapor deposition (CVD) process. Turning now to Figure 2, a via 202 is formed in the top insulating layer 11 and the interposer insulating layer 1G8. The bottom of the via 2Q2 is the top of the bottom insulating layer 106. The via may be formed by a lithographic mask and reactive ion (tetra) (RIE) technique well known in the art as well known to those skilled in the art. In a particular embodiment of the invention, the via 2〇2 is formed directly The bottom electrode 11 2 is shown in Fig. 3. The formation of the slit 3D2 in the through hole 202 is shown. The top insulating layer U is protruded from the insulating layer 108 in the through hole 202. Chang Zhicai will understand all kinds of wetness The wet name that can be applied to form the cut is based on the material used in the top insulating layer and the intermediate insulating layer no. In the embodiment of the present invention, the top insulating layer uo is formed by nitrogen cutting. The dielectric insulating layer ι 8 is composed of oxidized granules, and is etched with dilute hydro-f 1 <: aCld ' bribes, so that the dielectric insulating layer 108 can be used as compared with The top insulating layer 11Q is at a very high rate and is engraved to form the slit 310. In the figure, a π-degree (four) spacer layer is deposited on the top insulating layer 110 and deposited on the interposer insulating layer 108. The through hole 202 is accommodated therein. Cavity 4Q4 is formed in the spacer layer 402 and approximately to the center of the through hole 202 (see Fig. 3). The slit 302 (see Fig. 3) prevents the spacer (4) from completely filling the through hole 202. The position of the vacant 4 is '.', about the diameter of the hole 202 and is twice the position at the top. Page 8 of 24 098,127,879 袅Single number A0101 » » „ 09832 201108307 Edge layer 110 and the The diameter of the slit formed between the dielectric insulating layers 108. The larger through-holes 202 will pay more deposition and the smaller through-holes will result in less deposition. Therefore, the diameter of the cavity 404 (key The size will self-converge to the size of the slit. Again, the critical dimension is lithography-free. In an embodiment of the invention, the spacer layer is comprised of amorphous germanium and deposited using a CVD process. Figure 5 shows the formation of the stage spacer 502 and the channel 504 in the stage spacer 5〇2. The stage spacer 5〇2 and the channel are by the side spacer layer 402 (please refer to Fig. 4) Formed. The cavity class (please refer to FIG. 4) causes the etching to penetrate into the center of the through hole 2〇2 and is etched into the cavity 4 before the spacer 220 is etched. The spacer layer under 4, thus leaving a loop in the through hole 2_. The channel 5〇4 from this stage The top of the spacer 502 extends to the top surface of the bottom insulating layer 〇 6. The sidewall of the channel 504 is the stage spacer 5 〇 2. It is common to those skilled in the art that the directional program can be used for the etch. 〇
現轉向第6® ’該通·4延伸穿過該底部絕緣㈣卜該 階段間隔件5 G 2是用於作為Μ雜底部絕緣層丨〇 6的硬 遮罩。該通道5〇4向下延伸以穿過該底部絕緣層1〇6，致 使麵道504的底部為該基材刚的頂部表面或是該底部 接觸112的頂部表面。此外’該頂部絕緣層也被移除。在 本發明的—特^實施例中，該頂部絕緣層和該底部絕緣 層106都是由11切所構成 ，對於蝕刻到該底部絕緣層和 移除该頂部絕緣層可以採用指向性RIE » _ ’該階段間隔件被移除。此領域中具有通常知 098127879 Α者將了解所採用的蝕刻將依據用於該階段間隔件的材 表單鵠號Α0101 第 9 頁/共 24 頁 0983285547-0 201108307 料類型。在本發明的一特定實施例中，該階段間隔件是 由非晶矽所構成，而氫氧化鉀（Κ0Η)和氫氧化四甲銨（ tetramethylammonium hydroxide ; TMAH)則可以用 於該#刻中。 第8圖顯示由導電材料所構成的外部導線層8〇2的形成。 該外部導電層802是沿著與對齊於該通道5〇4的側壁和底 部而形成。在本發明的特定實施例中，該外部導電層8〇2 是與該底部接觸112接觸。此領域具有通f知識者將瞭解 可以使用各種電性導線材料，例如但不限制在氮化鈦（ πν)或是氮化鈕（：raN) v對於各種導線材料的沉積可 以採用常規的CVD程序。 第9圖顯示由絕緣材料所構成的内部絕緣層9〇2的形成。 該内部絕緣層902是沉積在該外部導電層8〇2上且填充該 通道504的剩餘部分。在本發明的實施例中，該内部絕緣 層902是由氮化矽所構成。此領域具有通常知識者將瞭解 對於該内部絕緣層902的形成可以採用常規的CVD介電質 程序。 轉到第10圖’該通道外面的該中介絕緣層和該内部絕緣 層902以及該通道外面的外部導電層802會被移除。此領 域具有通常知識者將瞭解對於該通道外面的該中介絕緣 層和該内部絕緣層902以及該通道外面的外部導電層802 的移除可以採用譬如但不限制於化學機械拋光（CMP)程 序。 對於該通道外面的該中介絕緣層和該内部絕緣層9〇2以及 該通道外面的外部導電層8〇2的移除會露出該底部絕緣層 106的頂部表面和所形成的該底部電極環丨〇〇2的頂部表面 098127879 表單編號A0101 第10頁/共24頁 0983285547-0 201108307 。該底部絕緣層1 0 6的頂部表面和所形成的該底部電極環 1 002的頂部表面是平行於該基材的頂部表面，藉此對於 相改變層的沉積而形成平坦表面。該底部電極環1 002是 由容納在該内部絕緣層902其中的該外部導電層802杯所 構成。該底部電極環1 002是容納在該底部絕緣層106内。 在本發明的一特定實施例中，該底部電極環1002是直接 定位在該底部接觸112上。 如第11圖所示，該相改變層1102和頂部電極1104是在該 底部絕緣層106和該底部電極環1002上形成。在本發明的 實施例中，該相改變層1102為與該底部電極環1 002至少 相同寬的區塊。該頂部電極1104是在該相改變層1102上 形成。在本發明的特定實施例中，該相改變層11 02是由 鍺-銻-碲（GST)所構成以及該頂部電極1104是由氮化 鈦（TiN)所構成。此領域具有通常知識者將瞭解對於該 相改變層1102和該頂部電極1104的形成可以採用各種程 序，例如但並不限制於，相改變材料沉積的CVD程序以及 金屬沉積的金屬濺渡程序。再者，由於該底部電極802是 被形成以作為該自會聚空腔404 (請參見第4圖）的結果 ，該底部電極802具有小於該相變化層1102的直徑變化為 較少的直徑變化。 在本發明的替換實施例中，該相改變層1102是在相改變 絕緣層1106内形成。該相改變絕緣層1106是在該底部絕 緣層106上和在該底部電極環1 002上形成。溝槽隨後在該 相改變絕緣層1106中的該底部電極環102上形成，致使該 溝槽的底部是該底部電極環1 002的頂部表面和該底部絕 緣層106的頂部表面。該頂部電極1104隨後在該相改變層 098127879 表單編號A0101 第11頁/共24頁 0983285547-0 201108307 1102和該相改變絕緣厗 a 1〇6上形成。在本發明的實施例 中，該相改變絕緣層丨〗 疋由一氧化石夕所構成。此領域 具有通常知識者將瞭解料 听對於该相改變絕緣層11〇6的形成 、溝槽形成以及適用於形 、彬成戎頂部電極1104的表面的形 成可以採用各種程序。产* < — 钗些程序可以包括和並未限制在 對於該相改變絕緣層^ υ6的形成的cvd程序、對於溝槽开 成的微影遮罩和RIE程鬼 征斤、以及對於過量相改變層1102纪 移除的CMP程序。 ’Turning now to the 6th'', the passage 4 extends through the bottom insulation (4). The stage spacer 5 G 2 is used as a hard mask for the doped bottom insulation layer 丨〇 6. The channel 5〇4 extends downwardly to pass through the bottom insulating layer 〇6 such that the bottom of the face 504 is the top surface of the substrate or the top surface of the bottom contact 112. In addition, the top insulating layer is also removed. In the embodiment of the present invention, the top insulating layer and the bottom insulating layer 106 are both formed by 11 dicing, and directional RIE can be used for etching the bottom insulating layer and removing the top insulating layer. 'The stage spacer was removed. The general knowledge in this field is known as 098,127,879. It will be appreciated that the etching used will be based on the material used for this stage of the spacer form number Α0101 page 9 of 24 0983285547-0 201108307 material type. In a particular embodiment of the invention, the stage spacer is comprised of amorphous germanium, and potassium hydroxide (tetramethylammonium hydroxide; TMAH) can be used in the inscription. Fig. 8 shows the formation of an outer wiring layer 8〇2 composed of a conductive material. The outer conductive layer 802 is formed along the side walls and the bottom portion aligned with the channel 5〇4. In a particular embodiment of the invention, the outer conductive layer 8〇2 is in contact with the bottom contact 112. Those skilled in the art will appreciate that various electrical conductor materials can be used, such as, but not limited to, titanium nitride (πν) or nitride button (:raN) v. Conventional CVD procedures can be used for deposition of various conductor materials. . Fig. 9 shows the formation of an inner insulating layer 9〇2 composed of an insulating material. The inner insulating layer 902 is the remaining portion deposited on the outer conductive layer 820 and filling the via 504. In an embodiment of the invention, the inner insulating layer 902 is composed of tantalum nitride. Those of ordinary skill in the art will appreciate that conventional CVD dielectric procedures can be employed for the formation of the inner insulating layer 902. Turning to Fig. 10, the interposer insulating layer and the inner insulating layer 902 outside the via and the outer conductive layer 802 outside the via are removed. Those of ordinary skill in the art will appreciate that the removal of the interposer and the inner insulating layer 902 outside of the via and the outer conductive layer 802 outside of the via may be employed, for example, but not limited to chemical mechanical polishing (CMP) procedures. The removal of the interposer insulating layer and the inner insulating layer 9〇2 outside the channel and the outer conductive layer 8〇2 outside the channel exposes the top surface of the bottom insulating layer 106 and the bottom electrode ring formed顶部2 top surface 098127879 Form number A0101 Page 10 of 24 page 0893285547-0 201108307. The top surface of the bottom insulating layer 106 and the top surface of the bottom electrode ring 002 formed are parallel to the top surface of the substrate, thereby forming a flat surface for deposition of the phase change layer. The bottom electrode ring 1 002 is formed by the outer conductive layer 802 cup housed in the inner insulating layer 902. The bottom electrode ring 1 002 is housed within the bottom insulating layer 106. In a particular embodiment of the invention, the bottom electrode ring 1002 is positioned directly on the bottom contact 112. As shown in Fig. 11, the phase change layer 1102 and the top electrode 1104 are formed on the bottom insulating layer 106 and the bottom electrode ring 1002. In an embodiment of the invention, the phase change layer 1102 is a block that is at least as wide as the bottom electrode ring 1 002. The top electrode 1104 is formed on the phase change layer 1102. In a particular embodiment of the invention, the phase change layer 102 is comprised of 锗-锑-碲 (GST) and the top electrode 1104 is comprised of titanium nitride (TiN). Those of ordinary skill in the art will appreciate that various procedures can be employed for the formation of the phase change layer 1102 and the top electrode 1104, such as, but not limited to, CVD procedures for phase change material deposition and metal sputtering process for metal deposition. Moreover, since the bottom electrode 802 is formed as a result of the self-converging cavity 404 (see Fig. 4), the bottom electrode 802 has a diameter variation smaller than that of the phase change layer 1102. In an alternate embodiment of the invention, the phase change layer 1102 is formed within the phase change insulating layer 1106. The phase change insulating layer 1106 is formed on the bottom insulating layer 106 and on the bottom electrode ring 002. A trench is then formed over the bottom electrode ring 102 in the phase change insulating layer 1106 such that the bottom of the trench is the top surface of the bottom electrode ring 002 and the top surface of the bottom insulating layer 106. The top electrode 1104 is then formed on the phase change layer 098127879 Form No. A0101 page 11 / page 24 0983285547-0 201108307 1102 and the phase change insulating layer a 1〇6. In an embodiment of the invention, the phase change insulating layer is composed of a oxidized stone. Those skilled in the art will appreciate that the formation of the phase change insulating layer 11〇6, the trench formation, and the formation of the surface suitable for the top electrode 1104 can be employed in a variety of procedures. Production* <- These procedures may include and are not limited to the cvd program for the formation of the phase change insulating layer 、6, the lithographic mask for the trench opening and the RIE process, and for the excess phase Change the CMP program removed by layer 1102. ’
本發明具有對於子微影印刷方法(sub-lithographic printing method)所囀述的較佳實施例（其傾向作為 說月f生而非為限制）’然、而應注意到可以按照上述教導 可使領域具㈣#知識者可料行改隸改變。因此， 應可以了解到在該特定實施朗揭*者所進行的任何改 變均屬於在本發明的範圍與精神内而由所附加的申請專 利範圍所涵蓋於疋，具有本發明所描速的觀點以及帶 有由專利法所需的細節和特質，其是由專利特許證（The present invention has a preferred embodiment for the sub-lithographic printing method (which tends to be a life rather than a limitation), but it should be noted that it can be The field has (4) # knowledge can be changed to change. Therefore, it should be understood that any changes made by those skilled in the art are intended to be within the scope and spirit of the invention and are covered by the scope of the appended claims. And with the details and traits required by the patent law, which is patented (
Letters Patent)所請求並渴望保勒柄被提出在該附加 的申請專利範圍中。 【圖式簡單說明】 [0005] 被視為本發明的請求標的是在綱書的結論中特別地被 指出且在申請專利範圍中被具體請求。本發明的前述和 其他目的、特徵以及優點是從結合伴隨著圖式與採用以 下詳細描述而為明顯，其中： 第1圖表*起始晶圓、基材和絕緣層。 第2圖表示貫孔形成。 第3圖表示切口形成。 098127879 表單編號A0101 第12頁/共24頁 0983285547-0 201108307 第4圖表示間隔件材料沉積以及空腔形成。 第5圖表示階段間隔件形成。 第6圖表示底層電極環的通道形成。 第7圖表示階段間隔件移除。 第8至10圖表示底層電極環形成。 第11圖表示相改變組件以及頂部電極形成。 【主要元件符號說明】 ΟThe Letters Patent) is requested and is eager to be filed in the scope of this additional patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0005] The subject matter of the present invention is considered to be specifically indicated in the conclusion of the specification and is specifically requested in the scope of the patent application. The foregoing and other objects, features and advantages of the present invention will be apparent from Figure 2 shows the formation of through holes. Figure 3 shows the formation of the incision. 098127879 Form No. A0101 Page 12 of 24 0983285547-0 201108307 Figure 4 shows spacer material deposition and cavity formation. Figure 5 shows the formation of a stage spacer. Figure 6 shows the channel formation of the bottom electrode ring. Figure 7 shows the stage spacer removal. Figures 8 through 10 show the formation of the underlying electrode ring. Figure 11 shows the phase change assembly and top electrode formation. [Main component symbol description] Ο
[0006] 102 ' 1 002 起始 [0007] 104 基材 [0008] 106 ' 108 、 110 ί [0009] 112 底部接觸 [0010] 202 貫孔 [0011] 302 切口 [0012] 402 間隔件層 [0013] 404 空腔 [0014] 502 階段間隔件 [0015] 504 通道 [0016] 802 外部導電層 [0017] 902 内部絕緣層 [0018] 1102 相改變層 [0019] 1104 頂部電極 表單編號Α0101 起始晶圓、底部電極環 098127879 第13頁/共24頁 0983285547-0 201108307 相改變絕緣層 [0020] 1106 098127879 表單編號A0101 第14頁/共24頁 0983285547-0102 ' 1 002 Start [0007] 104 Substrate [0008] 106 ' 108 , 110 ί [0009] 112 Bottom contact [0010] 202 Through hole [0011] 302 Incision [0012] 402 Spacer layer [0013] 404 Cavity [0014] 502 Stage Spacer [0015] 504 Channel [0016] 802 External Conductive Layer [0017] 902 Internal Insulation Layer [0018] 1102 Phase Change Layer [0019] 1104 Top Electrode Form Number Α 0101 Starting Wafer , bottom electrode ring 098127879 page 13 / total 24 page 0893285547-0 201108307 phase change insulation layer [0020] 1106 098127879 form number A0101 page 14 / total 24 page 0983285547-0