201107761 六、發明說明： 【發明所屬之技術領域】 本發明係關於資料處理之領域。更〜 尺将疋έ之，本發明 係關於用於偵測供應電壓位準何時 叮肖b連到預定電壓位準 之電源供應偵測電路。 【先前技術】 在資料處理電路中，穿過電路之漏電流是電路消耗電 源的原因之一’因此希望減少漏電流之量以減少電源消 耗。一種用於減少漏電流的技術是用電源開關來間控供 應給電路區塊的電源。漏電流之量取決於電路上之電壓 差。因此，處理電路可能具有備用模式，其中將一給定 之電壓差供應給該電路以使處理操作能夠執行；及低漏 電模式，其中減少電路上之電壓差以避免漏電流但不能 執行處理》 然而，一旦將電路置於低漏電模式，將電路切換回備 用模式則吏電路開始IL常處理所&費的冑間將會導致效 能損失。當將電源軌自低漏電供應位準切換至外部供應 位準時，則當電源軌在外部供應軌之特定範圍内時可能 產生就緒訊號，以通知電路其可以進行重設並可運作。 希望減少與產生就緒訊號相關聯之面積間接費用 (overhead) ° 【發明内容】 自一態樣來看，本發明提供電源供應偵測電路，其叙 201107761 接至處理電路之電源供應轨，該電源供應偵測電路包含 至少一個電源供應偵測單元，其用於偵測當將該電源供 應軌之供應電壓位準自第一電壓位準切換至第二電麈位 準時，該供應電壓位準是否已經達到預定電壓位準，該 電源供應偵測單元包含： 一訊號輸出，其用於輸出指示該供應電壓位準是否已 經達到該預定電壓位準之一就緒訊號； 一訊號節點，其耦接至該訊號輸出，該訊號輸出視在 該訊號節點上之一訊號節點電壓位準而定，輸出該就緒 訊號； 一第一電晶體，其耦接至該電源供應軌及該訊號節 點；及 一第二電晶體’其耦接至該訊號節點及具有一外部電 壓位準之一外部電壓供應；其中： 當將該供應電壓位準自該第一電壓位準切換至該第二 電壓位準時，該第一電晶體及該第二電晶體經組態以使 得該第一電晶體與該第二電晶體競爭，該第一電晶體將 該訊號節點電壓位準拉向該供應電壓位準，該第二電晶 體將該訊號節點電壓位準拉向該外部電塵位準，該第一 電晶體經組態以當該供應電壓位準達到該預定電壓位準 時克服該第1一電晶體；及 該乱號輸出經組態以視該第一電晶體何時克服該第二 電晶體而定’輸出該就緒訊號。 當將處理電路之電源供應軌之供應電壓位準自第一電 201107761 壓位準切換至第二電壓位準時，電源供應偵測電路偵測 該供應電壓位準是否已經達到預定電壓位準並且輸出指 不疋否已經達到該預定電壓位準之就緒訊號。視耦接於 第一電晶體與第二電晶體之間的訊號節點上之訊號節點 電壓位準而定’輸出該就緒訊號。第一電晶體及第二電 晶體彼此競爭，纟中當供應電壓位準在第一電壓位準與 第二電壓位準之間切換時，該第一電晶體將該訊號節點 電壓位準拉向該供應電壓位準，且該第二電晶體與該第 一電晶體相反，將訊號節點電壓位準拉向由外部電壓供 應之外部電壓位準。第一電晶體與第二電晶體之間的相 互作用使得當供應電壓位準達到預定電壓位準時第一電 晶體克服第二電晶體。視第一電晶體何時克服第二電晶 體而定’輸出就緒訊號。處理電路可使用就緒訊號以觸 發一或多個處理運作，諸如初始化或重設運作。 由於在第一電晶體與第二電晶體之間的競爭足以偵測 供應電壓位準何時遑到預定電壓位準，故電路中需要極 少其他時序控制’以致本技術之電路設計簡單且面積間 接費用少。 處理電路可以為任何邏輯電路，諸如處理器、記憶體 或快取記憶體、或記憶體控制器。預定電壓㈣可為在 第-電壓位準與第二電壓位準之間的任何電壓位準，但 將通常為較接近第二電壓位準之電壓位準。舉例而言， 預定電壓位準可在第—電壓位準與第二電壓位準之二的 ㈣處’以使得在供應電壓位準達到第二電壓位準前不 201107761201107761 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to the field of data processing. Further, the present invention relates to a power supply detecting circuit for detecting when a supply voltage level is connected to a predetermined voltage level. [Prior Art] In the data processing circuit, the leakage current flowing through the circuit is one of the causes of the power consumption of the circuit. Therefore, it is desirable to reduce the amount of leakage current to reduce power consumption. One technique for reducing leakage current is to use a power switch to control the supply of power to the circuit blocks. The amount of leakage current depends on the voltage difference across the circuit. Therefore, the processing circuit may have a standby mode in which a given voltage difference is supplied to the circuit to enable processing operations; and a low leakage mode in which the voltage difference across the circuit is reduced to avoid leakage current but cannot be processed. Once the circuit is placed in the low-leakage mode, switching the circuit back to the standby mode will result in a loss of performance when the circuit begins to process the IL. When the power rail is switched from the low leakage supply level to the external supply level, a ready signal may be generated when the power rail is within a certain range of the external supply rail to inform the circuit that it can be reset and operate. It is desirable to reduce the area overhead associated with generating a ready signal. [Invention] In one aspect, the present invention provides a power supply detection circuit, which is connected to a power supply rail of a processing circuit, which is connected to the power supply rail of the processing circuit. The supply detection circuit includes at least one power supply detecting unit configured to detect whether the supply voltage level is changed when the supply voltage level of the power supply rail is switched from the first voltage level to the second power level. The power supply detecting unit includes: a signal output for outputting a ready signal indicating whether the supply voltage level has reached the predetermined voltage level; a signal node coupled to the signal node The signal output, the signal output is determined according to a signal node voltage level of the signal node, and outputs the ready signal; a first transistor coupled to the power supply rail and the signal node; and a first The second transistor is coupled to the signal node and has an external voltage supply of an external voltage level; wherein: when the supply voltage level is When the first voltage level is switched to the second voltage level, the first transistor and the second transistor are configured such that the first transistor competes with the second transistor, the first transistor will The signal node voltage level is pulled to the supply voltage level, the second transistor pulls the signal node voltage level to the external dust level, and the first transistor is configured to be the supply voltage level Overcoming the first transistor when the predetermined voltage level is reached; and the hash output is configured to output the ready signal depending on when the first transistor overcomes the second transistor. When the supply voltage level of the power supply rail of the processing circuit is switched from the first power 201107761 pressure level to the second voltage level, the power supply detection circuit detects whether the supply voltage level has reached a predetermined voltage level and outputs Refers to the ready signal that the predetermined voltage level has been reached. The ready signal is outputted depending on the voltage level of the signal node coupled to the signal node between the first transistor and the second transistor. The first transistor and the second transistor compete with each other, and when the supply voltage level is switched between the first voltage level and the second voltage level, the first transistor pulls the signal node voltage level toward the first voltage level The supply voltage level, and the second transistor is opposite to the first transistor, pulling the signal node voltage level to an external voltage level supplied by the external voltage. The interaction between the first transistor and the second transistor causes the first transistor to overcome the second transistor when the supply voltage level reaches a predetermined voltage level. The output ready signal is determined depending on when the first transistor overcomes the second transistor. The processing circuitry can use the ready signal to trigger one or more processing operations, such as initialization or reset operations. Since the competition between the first transistor and the second transistor is sufficient to detect when the supply voltage level reaches a predetermined voltage level, very little other timing control is required in the circuit 'so that the circuit design of the present technology is simple and the area overhead less. The processing circuit can be any logic circuit such as a processor, memory or cache memory, or a memory controller. The predetermined voltage (4) may be any voltage level between the first voltage level and the second voltage level, but will typically be a voltage level that is closer to the second voltage level. For example, the predetermined voltage level may be at the (four)th of the first voltage level and the second voltage level so that the supply voltage level does not reach the second voltage level before 201107761
第二電晶體達到飽和後第一電晶體可克服第二電 當將供應電壓位準自第一電壓位準切換至第二電壓位 準時，隨著調整供應電壓位準’流過第一電晶體及第二 電晶體之電流最初呈線性增加。當電流線性增加時，訊 號節點電壓位準並不顯著改變。然而 具有比第二電晶體更高之飽和電流， ，由於第一電晶體 第二電晶體將在第 一電晶體前達到飽和，故在第二電晶體達到飽和之後， 流過第一電晶體之電流將繼續增加而流過第二電晶體之 流過第一電晶體之電流現在變得 電流，因此第一電晶體開始克服 電流大體上保持不變。流過筹 大於流過第二電晶體之電流， 第二電晶體以將訊號節點電壓位準拉向供應電壓位準。 隨後視第一電晶體何時克服第二電晶體而定，輸出就緒 訊號。藉由選擇具有適當飽和電流之第一電晶體及第二 電晶體，第一電晶體可經配置以當供應電壓位準達到預 定電壓位準時克服第二電晶體，因此電路可以經組態以 當達到預定電壓位準時發出就緒訊號。如此提供了一種 7 201107761 用於產生就緒訊號之有效技術。 就緒訊號可具有一就緒狀態及一未就緒狀態，該就緒 狀態指示供應電壓位準已經達到預定電壓位準，該未就 緒狀態指示供應電壓位準尚未達到預定電壓位準。訊號 輸出為未就緒狀態，直至第一電晶體克服第二電晶體， 以將訊號節點電壓位準拉向供應電壓位準為止，隨後就 緒訊號將改變為就緒狀態。 電源供應偵測電路可包含耦接在訊號節點與訊號輸出 之間的邏輯，該邏輯經組態以當該第一電晶體克服該第 二電晶體時，將該訊號節點電壓位準拉動超過一臨限電 壓位準時，將該就緒訊號自該未就緒狀態切換至該就緒 狀態。該邏輯確保當第一電晶體克服第二電晶體，以將 訊號節點電壓位準拉動超過臨限電麼位準時，存在確定 的就緒訊號切換點。 該邏輯可包含各種電路元件（例如，緩衝器），但在一 示例性實施例中，該邏輯包含一反相器。 可將第二電晶體之一閘極端點耦接至該邏輯，以使得 當第一電晶體將訊號節點電壓位準拉動超過臨限電壓位 準時將第二電晶體關閉。因為一旦訊號節點電壓位準超 過臨限值即關閉第二電晶體使得第一電晶體成為主控並 將訊號節點電壓位準拉至供應電壓位準，所以此舉是有 益的。此舉防止訊號節點電壓位準在該邏輯已經翻轉就 緒訊號之後仍為接近臨限電壓位準。此意謂在已經達到 預定電壓位準後就緒訊號具有確定的就緒狀態，因此確 !!； 201107761 保在任何下游電路中對就緒訊號之適當回應。 回應於將供應電壓位準自第一電壓位準切換至第二電 麼位準之啟動，可開啟第一電晶體。因此，在供應電壓 位準開始自第-電壓位準切換至第二電壓位準時，開啟 第電曰曰體以使传第一電晶體及第二電晶體開始試圖將 該訊號節點電壓位準拉向與彼此相反的方向。在第一電 B曰體與第—電晶體之間的此競爭提供了用於偵測供應電 壓位準何時達到預定電壓位準之機制。 該電路可包含一第三電晶體，其耦接於該外部電源供 應與該訊號節點之間，在將該供應電壓位準自該第一電 壓位準切換至該第二電壓位準之前開啟該第三電晶體， 且回應於將該供應電壓位準自該第一電壓位準至該第二 電壓位準之該切換之啟動而關閉該第三電晶體。因此 該第三電晶體將該訊 在供應電壓位準之切換開始之前 號節點拉至外部電源供應電壓位準。在開始自第一電壓 位準至第二電壓位準之切換之後，關閉該第三電晶體以 使第二電晶體與第一電晶體競爭。 該第二電晶體亦可控制第二電晶體，使其在開始自第 一電壓位準至第二電壓位準之切換之前開啟。 儘管單個電源供應偵測單元可能足以偵測供應軌上之 供應電壓位準何時達到預定電壓位準，但是在一示例性 實施例中，電源供應偵測電路包含複數個該等電源供應 偵測單元。因為該等電源供應偵測單元之生產過程的製 程變異可以調整第一電晶體及第二電晶體之飽和電流，After the second transistor reaches saturation, the first transistor can overcome the second current. When the supply voltage level is switched from the first voltage level to the second voltage level, the first transistor is flowed through the adjusted supply voltage level. The current of the second transistor and the current of the second transistor initially increase linearly. When the current increases linearly, the voltage level of the signal node does not change significantly. However, having a higher saturation current than the second transistor, since the second transistor of the first transistor will be saturated before the first transistor, after the second transistor reaches saturation, it flows through the first transistor. The current will continue to increase and the current flowing through the first transistor through the second transistor now becomes current, so the first transistor begins to overcome the current substantially unchanged. The flow through is greater than the current flowing through the second transistor, and the second transistor pulls the signal node voltage level toward the supply voltage level. The ready signal is then output depending on when the first transistor overcomes the second transistor. By selecting a first transistor having a suitable saturation current and a second transistor, the first transistor can be configured to overcome the second transistor when the supply voltage level reaches a predetermined voltage level, so the circuit can be configured to A ready signal is sent when the predetermined voltage level is reached. This provides an effective technique for generating a ready signal for 7 201107761. The ready signal can have a ready state indicating that the supply voltage level has reached a predetermined voltage level, and a not ready state indicating that the supply voltage level has not reached the predetermined voltage level. The signal output is not ready until the first transistor overcomes the second transistor to pull the signal node voltage level to the supply voltage level, and then the signal will change to the ready state. The power supply detection circuit can include logic coupled between the signal node and the signal output, the logic configured to pull the signal node voltage level more than one when the first transistor overcomes the second transistor When the threshold voltage level is normal, the ready signal is switched from the not ready state to the ready state. The logic ensures that there is a determined ready signal switching point when the first transistor overcomes the second transistor to pull the signal node voltage level beyond the threshold level. The logic can include various circuit elements (e.g., buffers), but in an exemplary embodiment, the logic includes an inverter. A gate terminal of the second transistor can be coupled to the logic such that the second transistor is turned off when the first transistor pulls the signal node voltage level above the threshold voltage level. This is beneficial because once the signal node voltage level exceeds the threshold, the second transistor is turned off such that the first transistor becomes the master and the signal node voltage level is pulled to the supply voltage level. This prevents the signal node voltage level from being close to the threshold voltage level after the logic has flipped the signal. This means that the ready signal has a determined ready state after the predetermined voltage level has been reached, so sure!!; 201107761 guarantees an appropriate response to the ready signal in any downstream circuit. The first transistor can be turned on in response to the activation of the supply voltage level from the first voltage level to the second level. Therefore, when the supply voltage level starts to switch from the first voltage level to the second voltage level, the first electrical body is turned on to cause the first transistor and the second transistor to start to try to pull the signal node voltage level. In the opposite direction to each other. This competition between the first electrical B body and the first transistor provides a mechanism for detecting when the supply voltage level reaches a predetermined voltage level. The circuit may include a third transistor coupled between the external power supply and the signal node, and turning on the supply voltage level before switching from the first voltage level to the second voltage level a third transistor, and the third transistor is turned off in response to activation of the switching of the supply voltage level from the first voltage level to the second voltage level. Therefore, the third transistor pulls the node to the external power supply voltage level before the start of the switching of the supply voltage level. After switching from the first voltage level to the second voltage level, the third transistor is turned off to cause the second transistor to compete with the first transistor. The second transistor can also control the second transistor to turn on before starting switching from the first voltage level to the second voltage level. Although a single power supply detecting unit may be sufficient to detect when the supply voltage level on the supply rail reaches a predetermined voltage level, in an exemplary embodiment, the power supply detecting circuit includes a plurality of the power supply detecting units. . Because the process variation of the production process of the power supply detecting unit can adjust the saturation current of the first transistor and the second transistor,
S 9 201107761 進而使得電源供應偵測單元於與期望預定電壓位準稍微 不同的電壓位準觸發就緒訊號，所以此舉是有益的。藉 由提供複數個電源供應偵測單元，可減少此等製程變異 之效應。 在另一特徵結構中，該複數個電源供應偵測單元可包 含N個電源供應偵測單元之鏈；回應於該供應電壓位準 自該第一電壓位準至該第二電壓位準之該切換的啟動， 開啟在該鏈中之第一電源供應偵測單元之該第一電晶 體；回應於第（i-Ι)個電源供應偵測單元之該就緒訊號， 開啟在該鏈中之第i個電源供應偵測單元的該第一電晶 體，該就緒訊號指示該供應電壓位準已經達到該預定電 壓位準，其中挪N;且在該鏈中之U個電源供應偵 測單元之該就緒訊號向該處理電路指示該供應電壓位準 是否已經達到該預定電壓位準。 藉由提供電源供應偵測單元之鏈，來 電源供應偵測單元之發出就緒訊號的時 接之電源供應偵測單元中最慢地將就緒 狀態者，當先前的電源供應偵測單元之 之就緒訊號指示供S 9 201107761 in turn causes the power supply detection unit to trigger the ready signal at a voltage level that is slightly different from the desired predetermined voltage level, so this is beneficial. By providing multiple power supply detection units, the effects of such process variations can be reduced. In another feature, the plurality of power supply detecting units may include a chain of N power supply detecting units; and the supply voltage level is from the first voltage level to the second voltage level. Switching on, turning on the first transistor of the first power supply detecting unit in the chain; in response to the ready signal of the (i-Ι) power supply detecting unit, opening the first in the chain The first transistor of the power supply detecting unit, the ready signal indicates that the supply voltage level has reached the predetermined voltage level, wherein N is N; and the U power supply detecting units in the chain The ready signal indicates to the processing circuit whether the supply voltage level has reached the predetermined voltage level. By providing a chain of power supply detecting units, the power supply detecting unit sends the ready signal to the power supply detecting unit that is the slowest to be ready, when the previous power supply detecting unit is ready Signal indication
來自該鍵中的最終 時間，將取決於鏈 訊號切換至就緒 10 201107761 體競爭。第二電源供應彳貞測單元之第一電晶體可能花費 更長的時間來克服第二電晶體，因此到該第二單元發出 其就緒訊號為止’該供應電壓位準將繼續接近預定電壓 位準’進而抵消該快速第一電源供應憤測單元之效應。 由於該供應電壓位準將足以觸發該就緒訊號，故隨後任 何更快的下游電源供應偵測單元將在啟動之後幾乎立即 地發出其就緒訊號。電源供應偵測單元之鏈之最終結果 在於快速單元之效應可由其他較慢的單元抵消。由於若 處理電路在其上之電壓差不足以確保該電路之正確操作 時開始處理，則過早的就緒訊號可導致處理錯誤，故過 早發出就緒訊號可能比過遲發出就緒訊號更為有害，故 上述抵消作用是有益的。電源供應偵測單元之鏈提供保 護以免出現此等過早就緒訊號。 該電源供應軌可為處理電路之接地供應軌，且該第一 電壓位準及該外部電壓位準可高於該第二電壓位準。在 此實例中，該電源供應偵測電路可與註腳（f〇〇ter)電路連 用，該註腳電路用於將接地供應軌在一高電壓位準與一 接地電壓位準間切換。該接地供應軌之高電壓位準可在 低漏電模式期間使用以減少在該處理電路上之電壓差。 备切換至備用模式時，將該接地供應軌放電至接地電壓 位準以使得處理能夠開始。 或者，該電源供應軌可為處理電路之主要供應軌，且 边第一電壓位準及該外部電壓位準可低於該第二電壓位 準。在此實例中’該電源供應偵測電路可與標頭（header) 201107761 電路連用，該標頭電路用於將主要供應轨自一低漏電電 壓位準切換至比低漏電電壓位準高之一運作電壓位準。 自另一態樣來看，本發明提供一種處理裝置，其包含： 一處理電路；一電源供應軌，其用於向該處理電路供應 -供應電壓位準；電源控制電路，其用於將該供應電壓 位準自一第一電壓位準切換至一第二電壓位準；及根據 本技術之電源供應偵測電路。 忒電源供應偵測電路可包括於一處理裝置中，該處理 裝置包含：-處理電路、一電源供應軌及該電源控制電 路。在該電源供應軌為一vss軌且該電源控制電路為一 註腳電路之情況下，該電源供應偵測電路偵測vss執何 時自-高電壓位準切換至一接地電壓位準、該vss軌何 時達到一預定電壓位準（例如，在接地電壓位準之5% 内）。類似地，在該電源供應軌為一 VDD軌且該電源控 制電路為-標頭電路之情況下，該電源供㈣測電路可 用以伯測It VDD電壓位準何時自一低電壓位準切換至 一高電壓位準、該VDD電壓位準是否已經達到一預定電 壓位準（例如，在該高電壓位準< 5%内）。由於該電源 供應制電路之面積間接費用小且電路運作簡單，故可 減少該裝置之總電路負擔。 該處理電路彳回應於指示該供應電壓纟準已經達到預 定電壓位準之就緒訊號以觸發資料處理運作。舉例而 b ’若該處理f路為-記憶體，則#已經達到第二電麼 位準時，該記憶體可藉由電力開啟某些備用記憶體區塊 12 201107761 來回應於就緒訊號。 I-實施例中，該處理裝置可包含：-第一處理電路 及-第二處理電路，該第-處理電路及該第二處理電路 各自具有一相應的電源供應軌及電源控制電路，、= 第一處理電路具有一相應的電源供應债測電路；其中口 應於該第一處理電路之該電源供應偵測電路輸出指示談 第一處理電路之該供應電壓位準已經達到該預定電壓位 準的該就緒訊號，啟動將該第二處理電路之該供應電壓 位準自該第一電壓位準至該第二電壓位準之切換。 當一處理裝置自一低漏電狀態激活時，隨著電路上之 電壓差提高，該電路内可產生一突波電流。該突波電流 可引起供應電壓位準之瞬時下降，如此可引起電路錯 誤。為了減少突波電流的量，可將—處理裝置分成不同 的處理電路’該等處理電路可逐個電力開啟。本技術之 電源供應偵測電路可用以控制在該裝置内之不同處理區 塊之連續電力開啟，此是由於^貞測—第—處理電路的供 應電壓位準何時達到預定位準之電源供應㈣電路可隨 後發出就緒机號，以觸發一第二處理電路之供應電壓 位準自第一電壓位準至第二電壓位準之切換的啟動。若 在該裝置内存在兩個以上的處理電路，則類似地，當先 前的處理電路發屮扣_ &不已經達到預定電壓位準的就緒訊 號時可電力開啟每—德 母後繼處理電路。以此方式，本技術 之電源供應4貞漁丨I __r m J電路可用於以一種有效的方式來控制該 處理裝置之電力開啟 々间啟以減少突波電流。 201107761 I樣來看，本發明提供電源供應偵測電路，其 耦接至用於向一處理電路供應電源之電源供應構件，該 電源供應债測電路包含至少一個電源供應债測構件，二 用於摘測當將該電源供應構件之供應電壓位準自—第一 電壓位準切換至一第二電壓位準時，該供應電壓位準是 否已經達到預定電壓位準，該電源供應偵測構件包含： 訊號輸出構件，其用於輸出指示該供應電壓位準是否 已經達到該預定電壓位準之一就緒訊號； 訊號節點構件，其用於輸送一訊號節點電壓位準，該 訊號節點係耦接至該訊號輸出構件，該訊號輸出構件視 該訊號節點構件上之一訊號節點電壓位準而定，輸出該 就緒訊號； 第一電晶體構件，其用於耦接該電源供應構件及該訊 號節點構件；及 第二電晶體構件，其用於耦接該訊號節點構件及用於 供應一外部電壓位準之一外部電壓供應構件；其中： 該第一電晶體構件及該第二電晶體構件經組態，以當 將該供應電壓位準自該第一電壓位準切換至該第二電壓 位準時，使該第一電晶體構件與該第二電晶體構件競 爭，該第一電晶體構件將該訊號節點電壓位準拉向該供 應電壓位準’該第二電晶體構件將該訊號節點電壓位準 拉向該外部電壓位準’該第一電晶體構件經組態以當該 供應電壓位準達到該預定電壓位準時克服該第二電晶體 構件；及 201107761 該訊號輸出構件經組態以視該第一電晶體構件何時克 服該第一電晶體構件而定，輸出該就緒訊號。 自另一態樣來看，本發明提供一種用於偵測當將處理 電路的電源供應執之供應電壓位準自一第一電壓位準切 換至一第二電壓位準時，該供應電壓位準是否已經達到 一預疋電壓位準的方法’該方法包含以下步驟· 將該供應電壓位準自該第一電壓位準切換至該第二電 壓位準； 組態一第一電晶體及一第二電晶體，該第一電晶體係 耦接於該電源供應軌與具有一訊號節點電壓位準之一訊 號節點之間，該第二電晶體係耦接於該訊號節點與具有 一外部電壓位準之一外部電壓供應之間，以使得該第一 電晶體與該第二電晶體競爭，該第一電晶體將該訊號節 點電壓位準拉向該供應電壓位準’該第二電晶體將該訊 號節點電壓位準拉向該外部電壓位準，該第一電晶體經 組態以當該供應電壓位準達到該預定電壓位準時克服該 第一電晶體； 視該訊號節點電壓位準及該第一電晶體何時克服該第 二電晶體而定，輸出一就緒訊號。 本發明之上述及其他目標、特徵及優點將由結合隨附 圖式閱讀之說明性實施例之以下詳細描述可更加明白。 【實施方式】 第1圖圖示處理裝置2，其具有耗接於卿軌6與咖 執8之間的處理電路4。處理電路4可為（例如）任何 15 201107761The final time from this key will depend on the chain signal switching to ready 10 201107761 body competition. The first transistor of the second power supply sensing unit may take longer to overcome the second transistor, so that the supply voltage level will continue to approach the predetermined voltage level until the second unit issues its ready signal. In turn, the effect of the fast first power supply anger unit is offset. Since the supply voltage level will be sufficient to trigger the ready signal, any faster downstream power supply detection unit will then issue its ready signal almost immediately after startup. The net result of the chain of power supply detection units is that the effects of the fast cells can be offset by other slower cells. Since the premature ready signal can cause a processing error if the voltage difference across the processing circuit is insufficient to ensure proper operation of the circuit, prematurely issuing a ready signal may be more harmful than issuing a ready signal too late. Therefore, the above countervailing effect is beneficial. The chain of power supply detection units provides protection against such premature ready signals. The power supply rail can be a ground supply rail of the processing circuit, and the first voltage level and the external voltage level can be higher than the second voltage level. In this example, the power supply detection circuit can be coupled to a footer circuit for switching the ground supply rail between a high voltage level and a ground voltage level. The high voltage level of the ground supply rail can be used during the low leakage mode to reduce the voltage difference across the processing circuit. When switching to standby mode, discharge the ground supply rail to ground voltage level to allow processing to begin. Alternatively, the power supply rail can be the primary supply rail of the processing circuit, and the first voltage level and the external voltage level can be lower than the second voltage level. In this example, the power supply detection circuit can be used with a header 201107761 circuit for switching the main supply rail from a low leakage voltage level to one of the lower leakage voltage levels. Operating voltage level. In another aspect, the present invention provides a processing apparatus comprising: a processing circuit; a power supply rail for supplying a supply voltage level to the processing circuit; and a power control circuit for The supply voltage level is switched from a first voltage level to a second voltage level; and the power supply detection circuit according to the present technology. The power supply detection circuit can be included in a processing device, the processing device comprising: - a processing circuit, a power supply rail, and the power control circuit. In the case that the power supply rail is a vss rail and the power control circuit is a footnote circuit, the power supply detection circuit detects when vss is switched from a high voltage level to a ground voltage level, and the vss rail When a predetermined voltage level is reached (eg, within 5% of the ground voltage level). Similarly, when the power supply rail is a VDD rail and the power control circuit is a -head circuit, the power supply (four) measurement circuit can be used to switch from a low voltage level to a low voltage level. A high voltage level, whether the VDD voltage level has reached a predetermined voltage level (eg, within the high voltage level < 5%). Since the area of the power supply circuit is small in indirect cost and the circuit operation is simple, the total circuit load of the device can be reduced. The processing circuit responsive to a ready signal indicating that the supply voltage has reached a predetermined voltage level to trigger a data processing operation. For example, if the processing f path is a memory, then # has reached the second level, the memory can be turned on by the power to turn on some spare memory block 12 201107761 in response to the ready signal. In an embodiment, the processing device may include: a first processing circuit and a second processing circuit, each of the first processing circuit and the second processing circuit having a corresponding power supply rail and a power control circuit, The first processing circuit has a corresponding power supply debt measuring circuit; wherein the power supply detecting circuit output of the first processing circuit indicates that the supply voltage level of the first processing circuit has reached the predetermined voltage level The ready signal initiates switching of the supply voltage level of the second processing circuit from the first voltage level to the second voltage level. When a processing device is activated from a low leakage state, a surge current can be generated in the circuit as the voltage difference across the circuit increases. This surge current can cause an instantaneous drop in the supply voltage level, which can cause circuit errors. In order to reduce the amount of surge current, the processing device can be divided into different processing circuits. The processing circuits can be turned on one by one. The power supply detection circuit of the present technology can be used to control the continuous power on of different processing blocks in the device, because the supply voltage level of the first-processing circuit reaches a predetermined level of power supply (4) The circuit can then issue a ready machine number to trigger activation of a supply voltage level of a second processing circuit from a first voltage level to a second voltage level. If there are more than two processing circuits in the device, similarly, each of the previous processing circuits can be powered on when the previous processing circuit issues a ready signal that does not have reached a predetermined voltage level. In this manner, the power supply of the present technology can be used to control the power-on of the processing device in an efficient manner to reduce the surge current. 201107761 I, the present invention provides a power supply detection circuit coupled to a power supply component for supplying power to a processing circuit, the power supply measurement circuit includes at least one power supply component, and two When the supply voltage level of the power supply component is switched from the first voltage level to a second voltage level, whether the supply voltage level has reached a predetermined voltage level, the power supply detecting component includes: a signal output component for outputting a ready signal indicating whether the supply voltage level has reached the predetermined voltage level; a signal node component for transmitting a signal node voltage level, the signal node being coupled to the signal a signal output component, the signal output component is configured to output the ready signal according to a signal node voltage level of the signal node component; the first transistor component is configured to couple the power supply component and the signal node component; And a second transistor member for coupling the signal node member and an external voltage for supplying an external voltage level a member; wherein: the first transistor member and the second transistor member are configured to cause the first when the supply voltage level is switched from the first voltage level to the second voltage level The transistor member competes with the second transistor member, the first transistor member pulls the signal node voltage level toward the supply voltage level. The second transistor member pulls the signal node voltage level toward the outside Voltage level 'the first transistor component is configured to overcome the second transistor component when the supply voltage level reaches the predetermined voltage level; and 201107761 the signal output component is configured to view the first transistor The ready signal is output when the component overcomes the first transistor component. In another aspect, the present invention provides a method for detecting a supply voltage level when a supply voltage level of a power supply of a processing circuit is switched from a first voltage level to a second voltage level. Whether the method of pre-empting the voltage level has been reached, the method includes the following steps: switching the supply voltage level from the first voltage level to the second voltage level; configuring a first transistor and a first a second transistor, the first transistor system is coupled between the power supply rail and a signal node having a signal node voltage level, the second transistor system is coupled to the signal node and has an external voltage level Between one of the external voltage supplies, such that the first transistor competes with the second transistor, the first transistor pulling the signal node voltage level toward the supply voltage level 'the second transistor will The signal node voltage level is pulled toward the external voltage level, and the first transistor is configured to overcome the first transistor when the supply voltage level reaches the predetermined voltage level; depending on the voltage level of the signal node The A transistor when the second transistor to overcome this may be, for outputting a ready signal. The above and other objects, features and advantages of the present invention will become more apparent from [Embodiment] FIG. 1 illustrates a processing device 2 having a processing circuit 4 that is consumed between a clear track 6 and a coffee 8 . Processing circuit 4 can be, for example, any 15 201107761
邏輯電路’諸如處理器或記憶體。川轨8經由註腳電 路12耦接至接地供應1〇β儘管第丨圖圖示兩個註腳電 路12 ’但疋可存在更多個註腳電路。視電源閘控訊號14 而，，開啟及關閉註腳電路12。當電源閘控訊號14具 有高邏輯狀態時，開啟註腳開g 12且將州線8放電 至接地1〇，以使得處理電路4處於備用模式以備處理。 當電源閘控訊號14具有低邏輯位準時，藉由切斷註腳開 關12來使處理電路4處於低漏電模式，以允許聊轨8 浮動至高於接地位準之邏輯位準。在低漏電模式中，VDD 軌6與VSS軌8之間的電壓差與備用模式中之電廢差相 比較有所減少，因此穿過處理電路4之漏電流比備用模 式中之漏電流低。 田將處理電路4自低漏電模式切換至備用模式時，一 旦乂88線8上之供應電壓位準達到預定電壓位準，處理 電路4即可開始處理操作。提供電源位準偵測電路（或 就緒訊號產生器）2〇，偵 乂1貝劂VSS轨8上之供應電壓位 達到預定電壓位準。電源位準偵測電路20包含若 -I :原位準偵測早疋22 ’其係連接為鏈。儘管第1圖圖 不兩個偵測單元22 θ 以上L C疋或可存在-個偵測單元或兩個 以上的偵測單元。 每一偵測單元22包含：第一雷b妙 26、第-匕3帛電-體24、第二電晶: 第一電晶體28及反相器32。楚 ^ 係耦拯π 及反相器32帛-電晶體24之閘; 接至電源閘控訊號丨4，且其 VSSlfe 8且具源極及波極係輕接;A logic circuit 'such as a processor or a memory. The track 8 is coupled to the ground supply 1〇β via the footer circuit 12, although the second footnote circuit 12' is illustrated in the figure, but there may be more footnote circuits. The footer circuit 12 is turned on and off depending on the power gate signal 14. When the power gating signal 14 has a high logic state, the footer open g 12 is turned on and the state line 8 is discharged to ground 1〇, so that the processing circuit 4 is in the standby mode for processing. When the power gating signal 14 has a low logic level, the processing circuit 4 is placed in a low leakage mode by turning off the footswitch 12 to allow the chat track 8 to float to a logic level above the ground level. In the low leakage mode, the voltage difference between the VDD rail 6 and the VSS rail 8 is reduced as compared with the electrical waste difference in the standby mode, so the leakage current through the processing circuit 4 is lower than the leakage current in the standby mode. When the field processing circuit 4 is switched from the low leakage mode to the standby mode, the processing circuit 4 can start the processing operation once the supply voltage level on the 88 line 8 reaches the predetermined voltage level. The power level detection circuit (or ready signal generator) is provided 2〇, and the supply voltage level on the 劂1 劂 VSS track 8 reaches a predetermined voltage level. The power level detection circuit 20 includes if -I: in-situ quasi-detection early 22' is connected as a chain. Although the first picture does not have two detection units 22 θ or more L C疋 or there may be one detection unit or more than two detection units. Each detecting unit 22 includes: a first thunder, a second, a second, and a second transistor: a first transistor 28 and an inverter 32. Chu ^ coupling π and inverter 32 帛 - transistor 24; connected to the power gating signal 丨 4, and its VSSlfe 8 with light source and wave system;
與訊號節點A之間。電晶體24 A 电日日髖24為N型電晶體 16 201107761 第二電晶體2 6為P型電晶體’其係耦接於外部電源供 應3〇與訊號節點A之間。外部電源供應30具有比接地 供應高之電壓位準。訊號節點A上之訊號為反相器 32之輪入’反相n 32之輸出控制第二電晶體％之閘極。 第二電晶體26比第一電晶體24小，因此具有比第一電 晶體24低之飽和電流。 第三電晶體28為P型電晶體，其係耦接於外部電源供 應30與讯號節點A之間。視電源閘控訊號14而定開 啟及關閉第三電晶體28。 訊號節點B上之反相器32的訊號輸出表示一就緒訊 號，其指示VSS軌8是否已經達到預定電壓位準。當vss 軌8尚未達到預定電壓位準時，訊號節點B具有一低邏 輯位準，其指示就緒訊號之未就緒狀態；而在vss軌8 已經達到預定位準之後’反相器32將節點b切換至一高 邏輯位準，其指示就緒訊號之就緒狀態。 對於偵測單元22之鏈中之第一及任何中間級而言，節 點B上之就緒訊號被作為後續級之電源閘控訊號14而輸 入。就緒訊號穿過偵測單元22之鏈行進直至鏈中之最終 偵測單元22將就緒訊號40轉送至處理電路4，以指示 由於V S S線8已經達到所需電壓位準故處理電路現在可 開始處理運作。及閘36可組合來自最終偵測單元22之 就緒訊號、電源閘控訊號14及超越控制訊號34，以使 得若電源閘控訊號14、超越控制訊號34及就緒訊號40 之每一者皆確立，則處理電路4僅接收就緒訊號42之就 17 201107761 緒狀態。超越控制訊號34使裝置之使用者能夠超越就緒 訊號，以使得必要時即使電源位準偵測電路已經發出 就緒訊號40，處理電路4仍不開始處理。 第2圖圖示第1圖之處理裝置之運作。在第2圖時間 〇處，電源閘控訊號14處於低邏輯狀態，其指示處理電 路4處於低漏電節點。因此，註腳開關12關閉，且vss 轨8漂移至高電壓位準Vl。第一電晶體24關閉，且第 二電晶體2 8開啟，以使得訊號節點a上之電壓處於相當 於外部電源供應電壓Vex與第三電晶體28之臨限電壓之 間的差之電壓位準。由於節點A上之訊號節點電壓位準 比反相器32之臨限電壓Vth高，故反相器32將訊號節 點B上之電Μ位準控制為低㈣位準，進而指示就緒訊 號處於未就緒狀態。此舉使得第二電晶體26開啟，以使 得第二電晶體26及第三電晶體28皆將節點a上之訊號 節點電壓位準拉向電源供應電壓Vex 。 在第2圖之時間t丨處’將電源閘控訊號14向高邏輯狀 態切換，其指示向備用（通電）模式之切換。此舉接通 註腳12 ’以使VSS軌8朝向接地供應電壓％放電。由 於處理電路4包括RC負載，故電源控制訊號及vss軌 化費-些時間來達到其切換之位準。電源控制訊號Μ逐 漸提高至-較高之位準@ vss轨8逐漸減少至一低位 準。在時間處達到目標電壓位準V—(亦即，將觸 發就緒訊號之預定電壓位準）^在此實例中，預定電壓位 準在接地供應電壓％之百分之幾内。Between the signal node A and the signal. The transistor 24 A is connected to the external power supply 3 〇 and the signal node A. The external power supply 30 has a higher voltage level than the ground supply. The signal on signal node A is the in turn of inverter 32. The output of inverting n 32 controls the gate of the second transistor %. The second transistor 26 is smaller than the first transistor 24 and therefore has a lower saturation current than the first transistor 24. The third transistor 28 is a P-type transistor coupled between the external power supply 30 and the signal node A. The third transistor 28 is turned on and off depending on the power gating signal 14. The signal output of inverter 32 on signal node B represents a ready signal indicating whether VSS rail 8 has reached a predetermined voltage level. When the vss track 8 has not reached the predetermined voltage level, the signal node B has a low logic level indicating the not ready state of the ready signal; and after the vss track 8 has reached the predetermined level, the inverter 32 switches the node b. To a high logic level, it indicates the ready state of the ready signal. For the first and any intermediate stages in the chain of detection units 22, the ready signal on node B is entered as the power gate signal 14 of the subsequent stage. The ready signal travels through the chain of detection unit 22 until the final detection unit 22 in the chain forwards the ready signal 40 to the processing circuit 4 to indicate that the processing circuit can now begin processing because the VSS line 8 has reached the desired voltage level. Operation. The gate 36 can combine the ready signal from the final detection unit 22, the power gating signal 14 and the override control signal 34 such that if each of the power gating signal 14, the override control signal 34 and the ready signal 40 is established, Then, the processing circuit 4 only receives the ready signal 42 and the state of the 2011. The override control signal 34 enables the user of the device to override the ready signal so that the processing circuit 4 does not begin processing even if the power level detection circuit has issued the ready signal 40 if necessary. Fig. 2 is a view showing the operation of the processing apparatus of Fig. 1. At time 第 of Figure 2, the power gating signal 14 is in a low logic state indicating that the processing circuit 4 is at the low leakage node. Therefore, the footer switch 12 is turned off, and the vss rail 8 is drifted to the high voltage level V1. The first transistor 24 is turned off, and the second transistor 28 is turned on so that the voltage on the signal node a is at a voltage level corresponding to the difference between the external power supply voltage Vex and the threshold voltage of the third transistor 28. . Since the signal node voltage level on the node A is higher than the threshold voltage Vth of the inverter 32, the inverter 32 controls the power level on the signal node B to a low (four) level, thereby indicating that the ready signal is not present. Ready state. This causes the second transistor 26 to be turned on so that both the second transistor 26 and the third transistor 28 pull the signal node voltage level on the node a toward the power supply voltage Vex. At time t丨 of Fig. 2, the power gating signal 14 is switched to a high logic state, which indicates a switch to the standby (power on) mode. This turns on the foot 12' to discharge the VSS rail 8 toward the ground supply voltage %. Since the processing circuit 4 includes the RC load, the power control signal and the vss orbiting fee take some time to reach the level of its switching. The power control signal is gradually increased to - the higher level @ vss track 8 is gradually reduced to a lower level. The target voltage level V is reached at time (i.e., the predetermined voltage level at which the ready signal will be triggered). In this example, the predetermined voltage level is within a few percent of the ground supply voltage %.
S 18 201107761 當在時間tl處電源控制訊號14向高狀態切換時，第一 電晶體24開啟且第三電晶體28關閉，因此使第一電晶 體24及第二電晶體26相互競爭。第一電晶體24將節點 A上之訊號節點電壓位準拉向VSS電壓位準（其逐漸降 低），而第二電晶體26將訊號低電壓位準A拉向外部電 源供應位準vex。在時間tl處，第一電晶體24及第二電 晶體26上之電壓差起初小，因此流過此等電晶體之電流 低。隨著VSS電壓位準在時間ti與之間下降，電晶體 24、電晶體26間之電壓差下降，因此穿過第一電晶體 24及第一電明體26之電流線性提高。由於穿過電晶體 24、電M體26之電流大致相等，故電晶體24、電晶體 26皆不成為主控，因此節點a上之電壓位準在時間q 與h之間不顯著減少。 第二電晶體26具有比第一電晶體24之飽和電流込… 低之飽和電流込⑴。在時間處，穿過第二電晶體26之 電流達到飽和電流isat2，且停止增加，即使第二電晶體 26上之電壓差隨著vss位準下降而繼續提高。然而，由 於第一電晶體24之飽和電流匕…高於第二電晶體26之 飽和電流，故穿過第一電晶體24之電流繼續提高，因此 現在第一電晶體24開始比第二電晶體26流過更多的電 流。因此，在時間tz與h之間，第一電晶體24開始克 服第二電晶體26之反作用，且將訊號節點a上之訊號節 點電壓拉向VSS線8上之供應電壓位準。第2圖圖示訊 號節點A電壓位準在時間tz與t3之間降低。 19 201107761 在時間t3處，訊號節·點A電壓位準達到臨限電壓ι , 以切換反相器32。此舉引起至訊號節點B上之就緒訊號 ^就緒（高邏輯）狀態之確定的切換。當反相器32將訊 號節點B切換至高邏輯狀態時，關閉第二電晶體％。現 在，對第一電晶體24不再存在任何反作用，因此第一電 晶體24將訊號節點a電壓位準拉低至vss電壓位準。 藉由調整第一電晶體24及第二電晶體26之相對尺寸 及因此之飽和電流，可配置電路以使得時間“與vss線 上之電壓位準達到預定電壓位準的時刻相重合， 在時間t3處就緒訊號自未就緒狀態切換至就緒狀態。 將節點B上之就緒訊號供應給後續之偵測電路2〇的電 源位準偵測級22,以觸發後續級執行與先前級相同之動 作。然而’在後續級22中，似線8上之電壓位準將已 經變得接近於預定電壓位準，因此第一電晶體24及第二 電晶體26間之電壓差將已經足夠大，以使得第一電晶體 24接近於克服第二電晶體26。因此，後續級將不會花費 如先前狀態一般長的時間來將就緒訊號切換至就緒狀 態。一旦偵測電路20中之所有偵測級皆已經產生具有就 緒狀態之就緒訊號，即將最終就緒訊號4〇發至處理電路 4。提供多個偵測級22有助於減輕快速切換偵測級22之 效應，以使得在視偵測電路2〇内之多個偵測級22中之 最慢偵測級而定的時間，發出最終就緒訊號4〇。此舉有 助於避免過早產生就緒訊號4〇之情況，過早產生就緒訊 號40在處理電路4中會引起錯誤。 20 201107761 第3圖圖示一時序圖，其呈示第！圖所示的電路之模 ㈣果13圖呈示節點A及節點β如何保持相對穩定 直至vss電壓位準降低接近於第二電>1位準。—旦vss 電麼位準達到職„位準，則節點A及節點B切換以 指示電Μ位準已經降低至足以允許處理電路4執行處理 運作。-旦偵測電路20之第一級22已經產生就緒訊號， 則允許開始後續級22。在第叫貞測級22與第㈣測級 之間的將其各別就緒訊號切換至就緒狀態之延遲太短以 至於在第3圖中不可見。 第3圖亦呈不了當自備用模式切換至低漏電模式時之 訊號轉變（參閲第3圖在20如與2“3之間的時段卜 當將電源閘控訊號14切換回低位準時，關閉註腳開關 X允許VSS電壓位準向上浮動。此舉切斷第—電晶體 24且接通第三電晶體28 ’第三電晶體28將訊號節點a 拉：高位準，進而使得節點B上之就緒訊號返回至指示 未就緒狀態之低位準狀態。 第4圖圖示摘測供應電壓位準何時達到預定電壓位準 之方法。起初，處理裝置2處於低漏電模式，因此VSS 線8處於高電壓狀態。第三電晶體以開啟，以將訊號節 點A拉向外部電源供應電壓。 在步驟1〇0,切換電源閘控訊號以啟動裝置之電力開 啟。因此’註腳開關12開始將VSS軌8拉向接地供應 位準。在步請’開啟第—電晶體24且關閉第三電晶 體28’以允許電晶體24、電晶體％在步驟1〇4競爭， 21 201107761 其中第一電晶體24將訊號節點A拉向VSS供應位準， 且第二電晶體26將訊號節點a拉向外部電源供應3〇之 外部電源供應位準。第一電晶體24及第二電晶體26有 效地彼此抵銷直至在步驟1〇6第二電晶體26達到飽和。 一旦第二電晶體26已經達到飽和，則第一電晶體24 開始比第二電晶體26流過更多電流，此是由於第一電晶 體24在第二電晶體26達到飽和的時刻尚未達到飽和。 因此’在步驟1〇8，第一電晶體24克服第二電晶體％ 之作用’且將訊號節點A上之電壓拉向VSS電壓位準。 在步驟110,將訊號節點A上之電壓位準拉動超過反相 器32之臨限電壓Vth ’因此反相器32將訊號節點b之位 準切換至高狀態》此舉使得第二電晶體26在步驟112關 閉。因此’第一電晶體24不再面臨來自第二電晶體％ 之任何競爭，因此第一電晶體24將訊號節點A上之電壓 位準拉至VSS電壓位準。 同時，在步驟114’訊號節點B上之高電壓位準產生 自领測級22輸出之就緒訊號，以指示已經達到預定電壓 位準Vurget。在步驟116，決定本電源位準偵測級22是 否為裝置20之末級。若本級不是末級，則在步驟118, 向下一級22提供就緒訊號，且在下一級重複第4圖中之 步驟102至步驟114〇當在步驟Π6達到末級時，在步驟 向處理電路提供經產生之就緒訊號，以在步驟122 觸發處理電路4内之處理運作。隨後第4圖之方法結束。 產生就緒訊號之時間視第一電晶體24及第二電晶體 22 201107761 26之飽和電流而定。為了使第一電晶體24最終能夠克 服第二電晶體26之反作用’第一電晶體24之飽和電流 應比第二電晶體26之飽和電流高。第5圖圖示飽和電流 隨著不同類型電晶體之電晶體尺寸的變化。飽和電流與 電晶體寬度成比例。飽和電流亦視用於電晶體之製程規 模而定。 第5圖圖示飽和電流隨著30 nm之nmos電晶體及34 nm之nmos電晶體及30 nm之pmos電晶體的電晶體寬 度的變化。第5圖考慮到最壞情況之製程邊界。對於30 nm之nmos電晶體而言’在最壞情況下飽和電流小於3〇 nm之pmos電晶體在整個電晶體寬度範圍内的最壞情況 下飽和電流，因此30 nm之nmos電晶體將永遠不能克服 30 nm之pmos電晶體的活動。相反地，若電晶體尺寸適 §，則34 nm之nmos電晶體具有比30 nm之pmos電晶 體高之飽和電流。因此，第5圖圖示0.8 μιη之nm〇s電 晶體具有比0.2 μηι之pmos電晶體高之飽和電流，因此 此等電晶體可用作本技術之第一電晶艟24及第二電晶 體26❶藉由選擇具有適當位準之尺寸及飽和電流的第一 電晶體24及第二電晶體26,可配置電源位準偵測電路 20以觸發就緒訊號，使其在vss電源軌8達 』只心览壓 第1圖至第5圖圖示一實施例’其中電源位準 路20偵測VSS電源軌8上之電壓位準。 '冤 第6圖圖示一替代性實施例，其中提供電源位準偵測 23 201107761 電路220以偵測VDD電源轨208上之電源供應何時達到 預定位準。第6圖之電路以類似於第1圖之方式運作。 在低漏電狀態’ VDD軌208處於低電壓位準。當將電源 閘控訊號214切換至通電狀態時，標頭開關212將VDD 執拉向電源供應2 1 0之電壓位準。此時，電源位準彳貞測 電路220内之電晶體224、電晶體226經組態以彼此競 爭’其中第一電晶體224將訊號節點Α拉向VDD電壓位 準，而第二電晶體226將訊號節點A拉向比電源供應位 準210低之外部電源供應位準230。一旦第二電晶體226 進入飽和區，第一電晶體224即克服第二電晶體226。 當第一電晶體224已經將訊號節點a電壓位準拉動超過 臨限位準時，反相器232翻轉訊號節點B以將就緒訊號 改變為就緒狀態。隨後就緒訊號穿過任何剩餘電源位準 偵測單元222行進。 與第1圖不同，在第6圖中，就緒訊號之低邏輯位準 指示就緒狀態’以指示VDD軌2Q8已經違到目標位準。 就緒訊號之高邏輯位準為未就緒狀態，其指示目標位準 尚未達到。又，在第6圖中，電源閘控訊號214之低邏 輯位準指示通電狀態，且電源閘控訊號214之高邏輯位 準指示低漏電狀態。或閘236將最終電源位準偵測單元 222之就緒訊號240、電源閘控訊號214及超越控制訊號 234組合，以使得僅當所有此等訊號為邏輯低時，才向 處理電路204供應處於邏輯低狀態之就緒訊號25〇,其 指示VDD上之電屋位準足以允許開始處理。處理電路 24 201107761 204回應於就緒訊號25〇之低位準而觸發處理運作。 第7圖圖示資料處理裝置3〇〇之一實例，其中電源位 準偵測電路（或就緒訊號產生電路）2〇可用以控制裝置 3〇〇内之不同處理區塊310之通電。裝置3〇〇包含若干 處理區塊310。當將裝£ 300自低漏電模式切換至通電 模式時’電源控㈣塊320依:欠電力肖啟各別處理區塊 31〇 (在此實例中，電源控制區塊32〇為註腳電路 電源位準偵測電路20_0偵測第一處理區塊31〇 〇之 VSS線VSS〇上之供應電壓何時達到預定位準，且隨後向 下一處理區塊310-1之註腳電路320-丨發出就緒訊號， 以指示可啟動處理區塊SiO·〗之電力開啟。註腳電路 320-1藉由開始將VSS線VSSi放電至接地以回應於就緒 訊號。 類似地’當先前處理區塊310_i已經達到預定電壓位 準時，相應的電源位準偵測電路20-i發出一就緒訊號以 觸發下一處理區塊310-( i+Ι)之電力開啟。以此方式， 就緒訊號產生電路20可控制各別處理區塊3 1〇之個別電 力開啟。因為同時電力開啟所有不同處理區塊將會產生 極大的突波電流’該突波電流可導致本說明書中之處理 錯誤’而在不同時間連續地電力開啟處理區塊3丨〇產生 較低衝擊電流，所以此舉是有益的。 儘管第7圖圖示具有電源位準偵測電路20之裝置 300 ’電源位準偵測電路20用於偵測VSS線何時達到預 定電壓位準’但是可將本技術類似地應用於裝置内之 25 201107761 VDD線’以使得用於電力開啟各別處理區塊3 10之標頭 電路回應於就緒訊號開始將VDD線自低位準電壓切換 至主要供應電壓’該就緒訊號係由先前處理區塊31〇之 電源位準偵測電路220發出。 儘管已在本文中參閱隨附圖式詳細地描述本發明之說 明性實施例，但應理解，本發明不限於彼等精確實施例， 且在不脫離由附加申請專利範圍界定之本發明之範疇及 精神的情況下，熟習此項技術者可進行各種變化及修改。 【圖式簡單說明】 / 第1圖示意性圖示了具有電源供應偵測電路之處理裝 置，該電源供應偵測電路用於偵測vss軌上之供應電壓 位準何時達到預定位準； 第2圖圖示了 一示例性時序圖，其圖示第1圓的電路 之運作； 第3圓圖示第i圖的電路之模擬運作； 第4圖圖示一種偵測供應電壓位準何時達到預定電壓 仇隼的方法； 第5圖圖示不同類型之電晶體的飽和電流與電 寸之間的關係； 圖圖示包含用於㈣卿執上之供應電壓位準何 時達到預定位準的電路的處理裝置；及 :7圖圖不使用電源供應偵測電路來控制處理裝置内 、別處理區塊的連續電力開啟。 【主要元件符號說明】 26 201107761 2 處理裝置 4 ‘處理電路 6 VDD 執 8 VSS 線/VSS 轨 10 接地供應 12 註腳電路/註腳開關 14 電源閘控訊號 20 電源位準偵測電路/裝置 20-0 電源位準偵測電路 22 電源位準偵測單元/偵測級 24 第一電晶體 26 第二電晶體 28 第三電晶體 30 外部電源供應 32 反相器 34 超越控制訊號 36 及閘 40 就緒訊號 42 就緒訊號 100 步驟 102 步驟 104 步驟 106 步驟 108 步驟 27 201107761 110 步驟 112 步驟 114 步驟 116 步驟 118 步驟 120 步驟 122 步驟 204 處理電路 208 VDD電源轨 210 電源供應/電源供應位準 212 標頭開關 214 電源閘控訊號 220 電源位準偵測電路 222 電源位準偵測單元 224 第一電晶體 226 第二電晶體 230 外部電源供應位準 232 反相器i 234 超越控制訊號 236 或閘 240 就緒訊號 250 就緒訊號 300 資料處理裝置 310-0 第一處理區塊S 18 201107761 When the power control signal 14 is switched to the high state at time t1, the first transistor 24 is turned on and the third transistor 28 is turned off, thereby causing the first transistor 24 and the second transistor 26 to compete with each other. The first transistor 24 pulls the signal node voltage level on node A toward the VSS voltage level (which is gradually reduced), while the second transistor 26 pulls the signal low voltage level A toward the external power supply level vex. At time t1, the voltage difference across the first transistor 24 and the second transistor 26 is initially small, so the current flowing through the transistors is low. As the VSS voltage level decreases between time ti and the voltage difference between the transistor 24 and the transistor 26 decreases, the current passing through the first transistor 24 and the first transistor 26 linearly increases. Since the currents passing through the transistor 24 and the electric M body 26 are substantially equal, neither the transistor 24 nor the transistor 26 is mastered, so the voltage level at the node a is not significantly reduced between the times q and h. The second transistor 26 has a saturation current 込(1) lower than the saturation current 込... of the first transistor 24. At time, the current through the second transistor 26 reaches the saturation current isat2 and stops increasing, even if the voltage difference across the second transistor 26 continues to increase as the vss level decreases. However, since the saturation current 第一 of the first transistor 24 is higher than the saturation current of the second transistor 26, the current passing through the first transistor 24 continues to increase, so that the first transistor 24 now begins to be larger than the second transistor. 26 flows more current. Thus, between time tz and h, the first transistor 24 begins to overcome the reaction of the second transistor 26 and pulls the signal node voltage on signal node a toward the supply voltage level on VSS line 8. Figure 2 illustrates the signal node A voltage level decreasing between times tz and t3. 19 201107761 At time t3, the signal section and point A voltage level reach the threshold voltage ι to switch the inverter 32. This causes a switch to the determined ready signal (high logic) state on signal node B. When the inverter 32 switches the signal node B to the high logic state, the second transistor % is turned off. Now, there is no longer any reaction to the first transistor 24, so the first transistor 24 pulls the voltage level of the signal node a down to the vss voltage level. By adjusting the relative sizes of the first transistor 24 and the second transistor 26 and thus the saturation current, the circuit can be configured such that the time " coincides with the time at which the voltage level on the vss line reaches a predetermined voltage level, at time t3 The ready signal is switched from the not ready state to the ready state. The ready signal on the Node B is supplied to the power level detection stage 22 of the subsequent detection circuit 2〇 to trigger the subsequent stage to perform the same action as the previous stage. 'In subsequent stage 22, the voltage level on line 8 will have become close to the predetermined voltage level, so the voltage difference between first transistor 24 and second transistor 26 will already be large enough that the first The transistor 24 is close to overcoming the second transistor 26. Therefore, the subsequent stage will not take as long as the previous state to switch the ready signal to the ready state. Once all of the detection stages in the detection circuit 20 have been generated A ready signal with a ready state, that is, a final ready signal 4 is sent to the processing circuit 4. Providing a plurality of detection stages 22 helps mitigate the effects of the fast switching detection stage 22 so that the view is in view The final ready signal 4〇 is issued for the time determined by the slowest detection level of the plurality of detection stages 22 in the circuit 2, which helps to avoid premature generation of the ready signal 4, prematurely generated The ready signal 40 causes an error in the processing circuit 4. 20 201107761 Figure 3 illustrates a timing diagram showing the mode of the circuit shown in Fig. (4). Figure 13 shows how node A and node β remain relatively stable until vss The voltage level decreases close to the second power > 1 level. Once the vss level reaches the level, node A and node B switch to indicate that the power level has been reduced enough to allow processing circuit 4 to execute. Processing operations. Once the first stage 22 of the detection circuit 20 has generated the ready signal, the subsequent stage 22 is allowed to begin. The delay between switching the respective ready signal to the ready state between the first measurement level 22 and the fourth (fourth) measurement level is too short to be visible in Fig. 3. Figure 3 also shows the signal transition when switching from standby mode to low leakage mode (refer to Figure 3, when the power gating signal 14 is switched back to the low level between 20 and 2"3. Turning off the footswitch X allows the VSS voltage level to float upwards. This cuts the first transistor 24 and turns on the third transistor 28'. The third transistor 28 pulls the signal node a: high level, thereby causing the node B to The ready signal returns to the low level state indicating the not ready state. Figure 4 illustrates the method of extracting when the supply voltage level reaches the predetermined voltage level. Initially, the processing device 2 is in the low leakage mode, so the VSS line 8 is at the high voltage. State. The third transistor is turned on to pull the signal node A to the external power supply voltage. In step 1〇0, the power gating signal is switched to activate the power of the device. Therefore, the footnote switch 12 starts to pull the VSS rail 8 The grounding level is supplied. In the step, 'the first transistor 24 is turned on and the third transistor 28' is turned off to allow the transistor 24 and the transistor % to compete in the step 1〇4, 21 201107761 wherein the first transistor 24 signals Node A Pulling to the VSS supply level, and the second transistor 26 pulls the signal node a to the external power supply level of the external power supply 3. The first transistor 24 and the second transistor 26 are effectively offset each other until the step The second transistor 26 reaches saturation. Once the second transistor 26 has reached saturation, the first transistor 24 begins to flow more current than the second transistor 26, since the first transistor 24 is at The time at which the second transistor 26 reaches saturation has not yet reached saturation. Therefore, 'at step 1 〇 8, the first transistor 24 overcomes the action of the second transistor %' and pulls the voltage on the signal node A toward the VSS voltage level. In step 110, the voltage level on the signal node A is pulled beyond the threshold voltage Vth of the inverter 32. Therefore, the inverter 32 switches the level of the signal node b to a high state. This causes the second transistor 26 to be in the step. 112 is turned off. Therefore, 'the first transistor 24 no longer faces any competition from the second transistor %, so the first transistor 24 pulls the voltage level on the signal node A to the VSS voltage level. Meanwhile, at step 114 'High voltage bit on signal node B The ready signal generated from the lead level 22 is generated to indicate that the predetermined voltage level Vurget has been reached. At step 116, it is determined whether the power level detection stage 22 is the final stage of the device 20. If the level is not the last stage, Then, in step 118, the ready signal is provided to the next stage 22, and steps 102 to 114 in FIG. 4 are repeated in the next stage. When the final stage is reached in step Π6, the generated ready signal is supplied to the processing circuit at the step. The processing operation in the processing circuit 4 is triggered in step 122. The method of Fig. 4 then ends. The time at which the ready signal is generated depends on the saturation current of the first transistor 24 and the second transistor 22 201107761 26. In order for the first transistor 24 to eventually overcome the reaction of the second transistor 26, the saturation current of the first transistor 24 should be higher than the saturation current of the second transistor 26. Figure 5 illustrates the saturation current as a function of transistor size for different types of transistors. The saturation current is proportional to the width of the transistor. The saturation current is also dependent on the process size of the transistor. Figure 5 illustrates the change in transistor width for a saturated current with a 30 nm nmos transistor and a 34 nm nmos transistor and a 30 nm pmos transistor. Figure 5 considers the worst-case process boundary. For a 30 nm nmos transistor, the worst-case saturation current of the pmos transistor with a saturation current less than 3 〇 nm in the worst case over the entire transistor width, so a 30 nm nmos transistor will never be able to Overcome the activity of the 30 nm pmos transistor. Conversely, if the transistor size is appropriate, the 34 nm nmos transistor has a higher saturation current than the 30 nm pmos transistor. Therefore, FIG. 5 illustrates that a 0.8 μm nm 〇s transistor has a higher saturation current than a 0.2 μm pmos transistor, and thus these transistors can be used as the first transistor 24 and the second transistor of the present technology. The power level detection circuit 20 can be configured to trigger the ready signal to be on the vss power rail 8 by selecting the first transistor 24 and the second transistor 26 having the appropriate size and saturation current. FIG. 1 to FIG. 5 illustrate an embodiment in which the power supply level 20 detects the voltage level on the VSS power rail 8. '冤 Figure 6 illustrates an alternative embodiment in which a power level detection is provided 23 201107761 Circuit 220 to detect when the power supply on the VDD supply rail 208 has reached a pre-positioning. The circuit of Figure 6 operates in a manner similar to Figure 1. In the low leakage state, the VDD rail 208 is at a low voltage level. When the power gating signal 214 is switched to the power-on state, the header switch 212 pulls VDD to the voltage level of the power supply 2 1 0. At this time, the transistor 224 and the transistor 226 in the power level detection circuit 220 are configured to compete with each other 'where the first transistor 224 pulls the signal node to the VDD voltage level, and the second transistor 226 Signal node A is pulled to an external power supply level 230 that is lower than power supply level 210. Once the second transistor 226 enters the saturation region, the first transistor 224 overcomes the second transistor 226. When the first transistor 224 has pulled the voltage level of the signal node a beyond the threshold level, the inverter 232 flips the signal node B to change the ready signal to the ready state. The ready signal then travels through any remaining power level detection unit 222. Unlike Fig. 1, in Fig. 6, the low logic level of the ready signal indicates the ready state' to indicate that the VDD rail 2Q8 has violated the target level. The high logic level of the ready signal is not ready, indicating that the target level has not been reached. Also, in Fig. 6, the low logic level of the power gating signal 214 indicates the power-on state, and the high logic level of the power gating signal 214 indicates the low leakage state. The OR gate 236 combines the ready signal 240, the power gating signal 214, and the override control signal 234 of the final power level detection unit 222 such that the processing circuit 204 is only in logic when all of the signals are logic low. The low state ready signal 25 〇 indicates that the electric house level on VDD is sufficient to allow processing to begin. Processing Circuit 24 201107761 204 Triggers the processing operation in response to the low level of the ready signal 25〇. Figure 7 illustrates an example of a data processing device 3, wherein a power level detection circuit (or ready signal generation circuit) 2 can be used to control the energization of different processing blocks 310 within the device 3. The device 3A includes a number of processing blocks 310. When the switch 300 is switched from the low leakage mode to the power-on mode, the power control (four) block 320 depends on: the underpowered power processing block 31 〇 (in this example, the power control block 32 is the footnote circuit power supply bit) The quasi-detection circuit 20_0 detects when the supply voltage on the VSS line VSS of the first processing block 31〇〇 reaches a predetermined level, and then sends a ready signal to the footer circuit 320- of the next processing block 310-1. The power is turned on to indicate that the bootable processing block SiO· is turned on. The footer circuit 320-1 responds to the ready signal by initially discharging the VSS line VSSi to ground. Similarly, 'when the previously processed block 310_i has reached the predetermined voltage level On time, the corresponding power level detection circuit 20-i sends a ready signal to trigger the power on of the next processing block 310-(i+Ι). In this way, the ready signal generating circuit 20 can control the respective processing areas. Block 3 1 〇 individual power is turned on. Because the power turns on all the different processing blocks, it will generate a huge surge current 'this surge current can cause the processing error in this specification' and continuously turn on the power at different times. The block 3丨〇 generates a lower inrush current, so this is beneficial. Although FIG. 7 illustrates the device 300 with the power level detection circuit 20, the power level detection circuit 20 is used to detect the VSS line. When the predetermined voltage level is reached', but the technique can be similarly applied to the 25 201107761 VDD line ' in the device such that the header circuit for powering on the respective processing block 3 10 responds to the ready signal to start the VDD line. The low level voltage is switched to the primary supply voltage 'this ready signal is issued by the power level detection circuit 220 of the previous processing block 31. Although an illustrative embodiment of the present invention has been described in detail herein with reference to the accompanying drawings It is to be understood that the invention is not limited to the precise embodiments, and various modifications and changes can be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. Brief Description] / Figure 1 schematically illustrates a processing device with a power supply detection circuit for detecting when the supply voltage level on the vss rail is Reaching a predetermined level; Figure 2 illustrates an exemplary timing diagram illustrating the operation of the circuit of the first circle; the third circle illustrates the analog operation of the circuit of Figure i; Figure 4 illustrates a detection The method of supplying the voltage level to the predetermined voltage enemies; Figure 5 illustrates the relationship between the saturation current and the capacitance of different types of transistors; the diagram shows the supply voltage level for (4) a processing device for a circuit that reaches a predetermined level; and: 7 Figure does not use a power supply detection circuit to control continuous power on of the processing device and other processing blocks. [Main component symbol description] 26 201107761 2 Processing device 4 ' Processing circuit 6 VDD 8 VSS line / VSS track 10 Ground supply 12 Foot circuit / foot switch 14 Power gate signal 20 Power level detection circuit / device 20-0 Power level detection circuit 22 Power level detection unit /Detection stage 24 First transistor 26 Second transistor 28 Third transistor 30 External power supply 32 Inverter 34 Override control signal 36 and gate 40 Ready signal 42 Ready signal 100 Step 102 Step 104 Step 106 Step 108 Step 27 201107761 110 Step 112 Step 114 Step 116 Step 118 Step 120 Step 122 Step 204 Processing Circuit 208 VDD Power Rail 210 Power Supply/Power Supply Level 212 Header Switch 214 Power Gate Signal 220 Power Level Detection Circuit 222 power level detection unit 224 first transistor 226 second transistor 230 external power supply level 232 inverter i 234 over control signal 236 or gate 240 ready signal 250 ready signal 300 data processing device 310-0 Processing block
S 28 201107761 310-1 320-1 下一 註腳 處理區塊 電路 29S 28 201107761 310-1 320-1 Next foot processing block circuit 29