201106630 六、發明說明： 【發明所屬之技術領域】 本發明係有關於位準移位器’特別是關於一種具差動形式之 位準移位器’其可在半橋或全橋上橋驅動器中執行共模突波 消除。 、…傻 【先前技術】201106630 VI. Description of the Invention: [Technical Field] The present invention relates to a level shifter 'particularly to a level shifter with a differential form' which can be used in a half bridge or full bridge upper bridge driver Perform common mode surge cancellation. Stupid [previous technique]
在說明本發明相關技術前，本案將先介紹一位準移位器與一 半橋或全橋上橋驅動器之關係。請參照圖1，其繪示一典型半橋驅 動器100之架構。如圖1所示，該典型半橋驅動器1〇〇至少包含 一脈衝產生器101、一位準移位器1〇2、一脈衝濾波器1〇3及一 鎖器104。 該脈衝產生器101係用以產生一第一時脈信號CLK及一第二 時脈信號CLKB ’其巾該第-時脈信號ακ係_第二時脈信 CLKB交錯產生。 1 該位準移位器102係用以將低侧該第一時脈信號clk及第二 時脈信號CLKB之位準上#以在上橋提供對應之信號以驅動該脈& 濾波器103。 該脈衝濾波器103係用以消除伴隨電源線¥晴及耶之共模突 波干擾’及產生一设置信號vSET和一重置信號Vreset以驅動該閂鎖器 104該閃鎖ϋ 1〇4係用以發送一信號至一驅動器以 上 功率 MOSFRT。 在該開、關期間，突波係因該電容c騰之電容特性而產生， 即突波係因2電容Οοστ兩極㈣之龍差不會突纽變而產生， =’該電谷Οοατ之電壓趨翻間會造成—突波觸^該脈衝遽 乃因此用以處理突波之問題，以防止該閃鎖器104被錯 ί W以提升半橋或全橋上橋驅動11其突波抗擾性之解決 ，、糸4用具對稱架構之位準移位器。請參照圖2，其緣示一習知 201106630 位準移位器200驅動一閂鎖器21〇之電路圖。如圖2所示，該習 知位準移位器200具有一對負載電阻2〇1〜2〇2、一第一對顺〇s 電晶體203〜204及一第二對丽〇s電晶體2〇5〜206。 藉由該對稱架構，在該第一對NM〇S電晶體2〇3〜2〇4汲極端 之電塵位準VSET及應會在—突波產生於電源線^時同時改 變’而使該第一對NM0S電晶體203〜204其汲極端間之電壓差伴 持不變，以避免該21G被假觸發。 差保Before explaining the related art of the present invention, the present invention will first introduce the relationship between a quasi-shifter and a half bridge or a full bridge upper bridge driver. Referring to Figure 1, the architecture of a typical half bridge driver 100 is illustrated. As shown in Fig. 1, the typical half bridge driver 1A includes at least a pulse generator 101, a one-bit shifter 1, 2, a pulse filter 1〇3, and a locker 104. The pulse generator 101 is configured to generate a first clock signal CLK and a second clock signal CLKB. The first clock signal ακ system_second clock signal CLKB is alternately generated. 1 The level shifter 102 is configured to level the first clock signal clk and the second clock signal CLKB on the low side to provide a corresponding signal on the upper bridge to drive the pulse & filter 103 . The pulse filter 103 is configured to eliminate the common mode surge interference accompanying the power line and the generation of a set signal vSET and a reset signal Vreset to drive the latch 104 to the flash lock ϋ 1〇4 Used to send a signal to a power MOSFRT above a driver. During the on and off periods, the spur wave system is generated due to the capacitance characteristic of the capacitor c. That is, the spur wave system is generated due to the difference between the two poles (4) of the two capacitors Οοστ, and the voltage of the electric valley Οαατ is generated. The tumbling will cause the glitch to be used to deal with the glitch, so as to prevent the flash lock 104 from being erroneously raised to enhance the spur immunity of the half bridge or the full bridge. The solution is to use a level shifter with a symmetric structure. Referring to FIG. 2, a schematic diagram of a conventional 201106630 level shifter 200 driving a latch 21A is shown. As shown in FIG. 2, the conventional level shifter 200 has a pair of load resistors 2〇1 to 2〇2, a first pair of transistors 203 to 204, and a second pair of 〇s transistors. 2〇5~206. With the symmetrical structure, the electric dust level VSET of the first pair of NM〇S transistors 2〇3~2〇4汲 and the time should be changed when the surge is generated on the power line ^ The voltage difference between the first poles of the first pair of NMOS transistors 203-204 is not changed to avoid the 21G being falsely triggered. Differential protection
然而’若該第一對NM0S電晶體203〜204其没極端之電壓位 準Vset及Vreset低於一臨界電壓，以致該第一對刚〇s電晶體2〇3〜 204及該第二對_電晶體2〇5〜2〇6被迫工作於三極管區 閂鎖器210可能會被假觸發。 μ 因此’麵提供-強健之位準移位器，其可減少因突波所造 成之设置信號及重置信號之壓降，以保證閂鎖器正 【發明内容】 本，明之-目的在於提出—财效邱健之裝置，以供一位 準移位II處理-半橋或全橋上橋縣料電源線之固有突波、。 另目的在於提供-㈣之具差細式之位準移位 器：、可減〉一半橋或全橋上橋驅動器其電源線之固有突波。 ^^上述目的’本發明提供了—具差動形式之位準移位 以=:其::對第一端點_接至-第-二 及第4脈W，一電流源，其係輕接 地之間’以提供-觸流;以及一對負載“ f考 接點及-對輸出接點，其中該缩置其具有-共同 信號 對輸出接點係稱接至該對第二端點；其中用而該 應，時脈信號及該第二時脈信號丄 為使貴審查委員能進-步瞭解本發明之結構、特徵及其目 201106630 的’兹附關式及較佳具體實施例之詳細說明如后。 【實施方式】 。清參照圖3’其繪示依本發明一較佳實施例實現之一位準移仇 器300及受該位準移位器3〇〇驅動之一閂鎖器31〇之電路圖其 中，位準移位H 300可降低—半橋或全橋上橋驅動器之電源線固 有突波。如圖3所示’該位準移位器具有一對負載電阻3〇ι 302、一差動對顺〇s電晶體303〜304及一電流源NM0S電晶體 305。However, if the first pair of NMOS transistors 203-204 have no extreme voltage levels Vset and Vreset below a threshold voltage, the first pair of gangs s transistors 2〇3~204 and the second pair _ The transistor 2〇5~2〇6 is forced to work in the triode area latch 210 and may be falsely triggered. Therefore, the 'surface-provided-strong position shifter can reduce the voltage drop caused by the surge signal and the reset signal to ensure that the latch is positive. [Inventive content] - Qiu Jian's device for financial efficiency, for a quasi-shift II treatment - the inherent spur of the half-bridge or full-bridge Shangqiao county power line. Another purpose is to provide - (d) differential level shifters: reduce the inherent glitch of the power line of a half bridge or full bridge bridge driver. ^^ The above object 'The present invention provides a level shift with a differential form to =: its:: to the first endpoint _ to - the second and fourth pulse W, a current source, which is light Between the groundings to provide-touch current; and a pair of loads "f test contacts and - pairs of output contacts, wherein the indentation has - a common signal pair output contacts are connected to the pair of second terminals; Wherein, the clock signal and the second clock signal are used to enable the reviewing committee to further understand the structure and features of the present invention and the accompanying drawings and preferred embodiments of the 201106630 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment] Referring to FIG. 3', a level shifter 300 and a latch driven by the level shifter 3 are implemented according to a preferred embodiment of the present invention. The circuit diagram of the latch 31〇, the level shift H 300 can reduce the inherent surge of the power line of the bridge driver of the half bridge or the full bridge. As shown in FIG. 3, the level shifter has a pair of load resistors 3〇ι 302, a differential pair of s transistors 303~304 and a current source NM0S transistor 305.
在該實施例中’該對負載電阻301〜302具有-共同接點及一 對輸出接點’其巾該共同接點餘接至-電麟V_，而該對輪出 接點則耦接至該NMOS電晶體303及該顺〇s電晶體3〇4。 山該差動對NMOS電晶體303〜304具有一對閘極端、一對没極 端及-共同源極端’其中轉汲極端係雛至該對輸出接點，談 對閘極端係祕至-第—時脈信號ακ及—第二時脈信號ωΒ，Λ 而該共同源極端則耦接至該電流源NM〇s電晶體3〇5。 山該電流源NMOS電晶體305具有一没極端、一開極端及一源極 端，其中献極端係雛至該差動對NM〇s電晶體綱〜施之該In this embodiment, the pair of load resistors 301-302 have a common contact and a pair of output contacts, and the common contacts are connected to the electric bridge V_, and the pair of wheel contacts are coupled to The NMOS transistor 303 and the 〇s s transistor 3〇4. The differential pair of NMOS transistors 303~304 has a pair of gate terminals, a pair of non-extreme and - common source extremes, wherein the extremes of the transition are tied to the pair of output contacts, and the gate is extremely secreted to the first - The clock signal ακ and the second clock signal ωΒ, 该 and the common source terminal are coupled to the current source NM〇s transistor 3〇5. The current source NMOS transistor 305 has a terminal, an open terminal, and a source terminal, wherein the extreme pair is applied to the differential pair NM〇s transistor.
St端失極:ί耦接至一直流偏麵％’而該源； 則雛至-參考地，其中該電流源嶋電晶體咖侧以提供一 1，：該差動對_電晶體303〜304之汲極端則係用以 反應該第-時脈信號CLK及該第二時脈信號ακΒ而產生 號VSET及一重置信號Vreset。 °置^ :一3之電路工作原理將以該第一時脈信號ακ處於一高位 ,’第一時脈㈣CLKBS於-低位準為例作說明，而 CLK、CLKB、V随、^及V_等相關信號之波形請參照圖^ 號St低位準變至一高位準而該第二‘ CLKB V留在-低位準時’該嶋t晶體編將被 電晶體304將被關閉’使得該設置信號Vsct呈現出一正常之^脈衝 201106630 2該重置織鋪在-高辦。_ i f玄有觸發而使該閃鎖器⑽送出—高位準以驅動一上 橋功率開關（未示於圖3中）。 經-傳播延遲tPD後，魏線v_之電壓會從^爬升至剛… ^ =變化會透過該_電晶體3{)3纽極與閘極間之問汲 寄生電谷舰而在該第-時脈信號ακ上產生—突波， 該刪電晶體304其沒極與間極間之閑_ 兮 脈信臟Β上產生—綠。卿—日械The St terminal loses polarity: ί is coupled to the constant flow surface %' and the source; then to the reference ground, wherein the current source is on the transistor side to provide a 1, the differential pair _ transistor 303~ The extreme of 304 is used to generate the number VSET and a reset signal Vreset by reacting the first clock signal CLK and the second clock signal ακΒ. ° Set the circuit operation principle of 1:3, the first clock signal ακ is at a high level, and the first clock (four) CLKBS is at the low level as an example, while CLK, CLKB, V follow, ^ and V_ For the waveform of the related signal, please refer to the figure “St low” to a high level and the second 'CLKB V to stay at the low level. The 晶体t crystal will be turned off by the transistor 304', so that the setting signal Vsct Presenting a normal ^pulse 201106630 2 The reset weaving is in the high office. _ i f Xuan has a trigger to cause the flash lock (10) to be sent out - a high level to drive an upper bridge power switch (not shown in Figure 3). After the warp-propagation delay tPD, the voltage of the Wei line v_ will climb from ^ to just... ^ = change will pass through the _ transistor 3{) 3 between the gate and the gate, the mistletoe electric valley ship - A pulse is generated on the clock signal ακ, and the power-cut crystal 304 generates a green color between the immersed pole and the inter-electrode. Qing-Japan
可使該_S t晶體303導通而該第二時脈信號⑽之突波可使 = NM〇S電晶體304導通，故該設置信號及該重置信號v 出現一受感染之負脈衝。 由於本發明之差動形式設計，係使該電流源刪電晶體娜 電流I約略分為二電流1/2、1/2以分職_ n廳電晶 體303及該NMOS電晶體304，因此該設置信號Vsct及該重置作號 W其受感染負脈衝之波谷位準Vu會遠高於—臨界電壓^，而可 P方止該⑽H 被錯糊發。細，在胃知其位轉位器 狀巾’其傭舰界雜Vth之該·#號VSCT及該 重置WV_之波谷位準Vl2，卻可能會使該_器副被錯誤觸 發。 *為了進-步降低該第-時脈信號CLK及該第二時脈信號CLKB 之大波’-疊接之差動對乃進一步被採用。請參照圖4，轉示依 本發明另-較佳實施例實現之-位準移位器姻及受該位準移位 器400驅動之-閃鎖n 410之電路圖，其中該位準移位器麵可 降低一半橋或全橋上橋驅動器之電源線固有突波。 如圖4所示’該位準移位器400具有一對負載電阻4〇1〜4〇2、 第-差動對NMOS電晶體403〜404、-第二差動對_電晶體 405〜406及一電流源NMOS電晶體407。 201106630 在該實施例中’該對負载電阻4〇1〜4〇2具有一共同接點及— 對輸出接點，其^該共同接點係輕接至一電源線—，而該對輸出 接點則祕至該第-差動對麵s電晶體備〜·。 該第-差動對_電晶體〜侧具有一第一對閘極端、 端及—第—對源極端，其中該第-歧極端係輕接 至該對負載電阻4〇1〜之該對輸出接點，該第—對閘極端係輕 考地’而該第一對源極端則耦接至該第二對蘭0s電晶體 405〜406 。 NM0S taa^ 405^406 > ;ϊ:=Γ;ί嶋端，其中該第二對汲極端係捕至 該t對雜端，該第二制極端係顧至—第—時脈信號ω 脈信號⑽，而該共同源極端_接至該電流源臟 該電流源_s電晶體術具有_汲極n極端及 端，其中該錄端係輕接至該共同源極端，該間極端係输至一 ί 源極端_接至該參考地。職源_電 該第-時脈信號ακ及該第二時脈信號⑽f係用以反應 -及-重綱w。 _而產生一設置信號 由圖4可以看$，該第二對祕端與料 沒寄生電容可獲得該第一對臓電晶體〜姻之參屏=，之I— =時=α:Γ該第二時脈信號⑽受該電源線“干 擾之域—從而進-步防止該問鎖器410被錯誤觸發。 所以經由本發明上述較佳實施例之實施，即^ 建r準移位器以處理-半橋或全橋上橋= 本案所揭示者，乃較佳實補，舉凡局部 :本案之技術思想而為熟習該項技藝之人所易於推知^二不脫、 201106630 本案之專利權範_。 綜上所陳，本案無論就 社會，實感德便 【圖式簡單說明】 =:技，，且其首先發二二== =要tfl責審查委員明察，並析早日賜予專利，ίΛ 圖1為-不意圖’其繪示一典型半橋驅動器之架構。 圖2為-二意圖’其♦示—習知位準移位器之電路圖。The _S t crystal 303 can be turned on and the spur of the second clock signal (10) can turn on the =NM〇S transistor 304, so that the set signal and the reset signal v exhibit an infected negative pulse. Because of the differential form design of the present invention, the current source de-energized crystal current I is roughly divided into two currents 1/2, 1/2 to be divided into the _n hall transistor 303 and the NMOS transistor 304, so Setting the signal Vsct and the resetting flag W will cause the valley level Vu of the infected negative pulse to be much higher than the -threshold voltage ^, and the P (10)H can be confused. Fine, in the stomach knows its position indexer towel 'its servant boundary miscellaneous Vth · # VSCT and the reset WV_ trough level Vl2, but may cause the _ instrument pair to be wrongly triggered. * A differential pair for the large-wave'-stacking of the first-clock signal CLK and the second clock signal CLKB for further step-down is further employed. Referring to FIG. 4, a circuit diagram of a level shifter implemented in accordance with another embodiment of the present invention and a flash lock n 410 driven by the level shifter 400 is illustrated, wherein the level shift The face reduces the inherent spur of the power line of the bridge driver on half of the bridge or the full bridge. As shown in FIG. 4, the level shifter 400 has a pair of load resistors 4〇1 to 4〇2, a first-differential pair NMOS transistor 403-404, and a second differential pair_transistor 405-406. And a current source NMOS transistor 407. 201106630 In this embodiment, the pair of load resistors 4〇1~4〇2 have a common contact and, for the output contact, the common contact is lightly connected to a power line, and the pair of outputs are connected. The point is secret to the first-differential opposite s transistor preparation ~·. The first differential pair _ transistor has a first pair of gate terminals, a terminal and a first-to-source terminal, wherein the first-dividend terminal is lightly connected to the pair of load resistors 4〇1~ The first pair of source terminals are coupled to the second pair of blue 0s transistors 405 to 406. NM0S taa^ 405^406 >;ϊ:=Γ; 嶋 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , a signal (10), and the common source terminal is connected to the current source. The current source _s transistor has a _pole n-terminus and an end, wherein the recording terminal is lightly connected to the common source terminal, and the extreme terminal system loses To the source of the source _ to the reference ground. Source_Electricity The first-clock signal ακ and the second clock signal (10)f are used to react - and - to h. _ and generate a setting signal can be seen from Figure 4, the second pair of secret end and material without parasitic capacitance can obtain the first pair of 臓 臓 〜 〜 姻 姻 = = = = = = = = = The second clock signal (10) is "interfered by the power line" - thereby preventing the challenger 410 from being erroneously triggered. Therefore, by implementing the above preferred embodiment of the present invention, Processing - half bridge or full bridge upper bridge = the case disclosed in this case, is better to make up, for the part: the technical idea of the case is easy for people who are familiar with the skill to know ^二不 off, 201106630 patent rights of this case _ In summary, the case, regardless of the society, the real sense of virtue [simplified description] =: technology, and its first to send two or two == = tfl responsible for reviewing the committee, and analysis of the early patent, Λ Λ Figure 1 For the sake of - not intended, it depicts the architecture of a typical half-bridge driver. Figure 2 is a circuit diagram of a conventional level shifter.
圖3為一不意圖，其繪示依本發明一較佳實施例實現之一位 準移位ϋ及受該辦雜ϋ軸之-關m關，其中該位 準移位器可降低一半橋或全橋上橋驅動器之電源線固有突波。 圖4為一示意圖，其繪示依本發明另一較佳實施例實現之一 位準移位器及受該位準移位器驅動之一閂鎖器之電路圖，其中該 位準移位器可降低一半橋或全橋上橋驅動器之電源線固有突波。 圖5為'一不思圖’其繪不圖3電路之工作波形圖。 【主要元件符號說明】 半橋驅動器100 脈衝產生器101 位準移位器102、200、300、400 脈衝濾波器103 閂鎖器 104、210、310、410 電阻 201 〜202、301 〜302、401 〜402 NMOS 電晶體 203〜204、205〜206、303〜304、305、403〜404、 405〜406、407FIG. 3 is a schematic diagram showing the implementation of a level shift ϋ and the off-axis of the ϋ ϋ , according to a preferred embodiment of the present invention, wherein the level shifter can reduce the bridge by half. Or the power line of the full bridge upper bridge driver is inherently glitch. 4 is a schematic diagram showing a circuit diagram of a level shifter and a latch driven by the level shifter according to another preferred embodiment of the present invention, wherein the level shifter It can reduce the inherent surge of the power line of the bridge driver on half of the bridge or full bridge. Fig. 5 is a diagram showing the operation waveform of the circuit of Fig. 3, which is not considered. [Description of main component symbols] Half-bridge driver 100 Pulse generator 101 Level shifter 102, 200, 300, 400 Pulse filter 103 Latches 104, 210, 310, 410 Resistors 201 to 202, 301 to 302, 401 ~402 NMOS transistors 203~204, 205~206, 303~304, 305, 403~404, 405~406, 407