TW201106174A - Discrete cosine transformation circuit and apparatus utilizing the same - Google Patents

Abstract

A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises a first and a second arithmetic logic unit (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive and perform another calculation on the result from the path in a clock cycle next to the first clock cycle.

Description

201106174 VI. Description of the Invention: [Technical Leadership of the Invention] [0001] The present invention relates to a Discrete Cosine Transformation (DCT) technology, in particular to a discrete cosine transform circuit for performing two-dimensional discrete cosine transform . [Prior Art] [0002] Discrete cosine transform is often used for data compression of images. The forward discrete cosine transform uses the discrete cosine function to convert the image data into the frequency domain data. The inverse discrete cosine transform uses the discrete cosine function to inversely convert the frequency domain data into the original image data. The discrete cosine transform can be used. Representing forward discrete cosine transform or inverse discrete cosine transform [0003] Discrete cosine transform devices typically perform a complete binary transform on a macro: block, for example, first-order discrete for each column of an 8x8 pixel block Cosine transform, and then perform another dimensional discrete cosine transform on each line of the 8x8 pixel block. Video coding standards such as H.264, VC-1, and MPEG2 use block conversion, the only difference being the block size and coefficient. Different video coding methods are usually designed with a dedicated discrete cosine conversion circuit. In order to integrate these dedicated circuits in one exhibition to support different video coding methods, the circuit design is complicated and the circuit miniaturization is difficult. When the device wants to support the new video coding method, the circuit design The leaf must be changed again. It is more flexible to use a general purpose processor to perform different ^ encoding methods, but it is relatively inefficient. SUMMARY OF THE INVENTION [0004] In view of the above, it is desirable to provide a discrete cosine transform circuit and an image processing apparatus using the same. ~ 098126121 Form No. A0101 Page 4 of 45 0982044783-0 201106174 [0005] A discrete cosine transform circuit includes a butterfly calculus circuit having a pipeline of an extraction stage, a memory stage, and an operation stage. The fetch stage receives and decodes the butterfly calculus instruction set. The memory level includes a memory repository for storing image data coefficients and intermediate calculation data output by the operation level, and outputting the first stored in the memory level in the first clock cycle according to the at least one decoded butterfly calculation instruction a set of data. The operation stage includes a plurality of registers, a first operation logic unit, and a second operation logic unit, the plurality of registers receiving the first set of data from the memory repository as input data of the operation stage, the first operation logic And the second arithmetic logic unit receives a set of input data from the plurality of registers and performs a first calculation on the set of input data, according to the at least one decoded butterfly calculation instruction after the first clock cycle The second clock cycle outputs the calculation result of the first calculation formula. The butterfly calculation circuit includes a line leading the calculation result from the operation level to the memory level in the same clock cycle in which the first calculation operation is completed, so that at least one register is after the second clock cycle The third clock cycle may choose to receive the calculation result from the line or the memory bank to receive the next set of data. An image processing apparatus includes a discrete cosine transform circuit having a pipeline of an extraction stage, a memory stage, and an operation stage. The fetch stage receives and decodes the butterfly calculus instruction set. The memory level includes a memory storage for storing image data coefficients and intermediate calculation data output by the operation level, and outputting the first group of data in the first clock cycle according to the at least one decoded butterfly calculation instruction. Memory level. The operation stage includes a plurality of registers, a first operation logic unit, and a second operation logic unit, the plurality of registers receiving the first group of data from the memory bank as an input of the operation level 098126121 Form No. 1010101 Page 5 / Total 45 pages 0982044783-0 201106174 [0007] [0008] [0009] [0010] [0011] 098126121 资科, the first - transported a number of registers received - planted in a single 7 ^ two arithmetic logic unit from the In the calculation formula, the second clock cycle calculation command after the first pulse period is executed according to at least the f material and the set of input data is at the first time. The rn + ^3—the line of the calculation result of the butterfly calculation circuit U is calculated from the same level in the same-_« of the first calculation type, so that at least one temporary storage + guide to. In the Hei 5 recall period, the next-group data can be selected from the third clock period after the line=second clock period. Receipt reading or storage from the memory library [Embodiment] Embodiments of the discrete cosine conversion circuit and its apparatus are as follows: 1. System Overview Π = Γ discrete cosine conversion circuit can be implemented in various boxes or any image 2 = digital camera, lap, etc. is built-in image processing capability: drink and change - the embodiment of the TM 1.1 image processing device discrete cosine conversion circuit 165 is rationally opened, the center of the image processing device 100 The processor 151 in the processor 151 can be constructed from a wafer. Power supply s m components. Quartz heart, power to image (4) (8) Disk w provides a clock signal to the processing of other components in the processing device 100. Figure u shows an example

under

Form No. A0101 Page 6 of 45 0982044783-0 201106174 The connection of each component in the device ιο〇 can be connected through a serial bus or a parallel bus. Input and output devices include control buttons, seven-segment display, and an infrared receiver or transceiver that communicates with the remote controller. The 164 is connected to an external computer for debugging the image processing apparatus 100.埠164 may be in accordance with the regulations of the Electronic Industry Association (EIA)

232 (Recommended Standard-232, referred to as 232) and / or the recommended standard (Rec〇mfflended Standard-u 'RS_U) physical connection 串, Serial ATA (Serial ΑΤΑ 'referred to as SATA) and / or high Sharpness multimedia interface (

High Definition Multimedia Interface, referred to as HDMI HDMI). The non-selective memory 】 53 stores the operating system and application executed by the processor i51. The processor 151 loads the running program and data into the main memory 152 and stores the digital content in the mass storage device 154. The main memory 152 may be a random access memory (RAM), such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). ). The non-volatile memory U3 can be an electronic erasable programmable read-only memory (Electrically

Erasable Programmable Read-Only Memory (EEPROM) ‘for example, reverse (N0R) flash memory or reverse (NAND) flash memory. The content protection unit 155 provides access control for the digital content generated by the image processing apparatus 100. The content protection unit 155 includes the memory and necessary means for implementing the universal interface (DVB_CI) and/or conditional access (DVB-CA) for digital video broadcasting. The image processing apparatus 100 can obtain the digital signal from the antenna 165, the tuner 157, and the demodulator 156 by 098126121 Form No. A0101, Page 7 of 45, 0982044783-0 201106174. In another embodiment, the image processing device 1G1 obtains digital content from a network such as the Internet through a network access interface. The video output unit 162 includes the wave # and the amplifier for filtering and amplifying the (four) video signals transmitted by the processing signal 1. The audio output unit 161 includes a digital analog converter for converting the audio signal rotated by the processor 151 from an analog format to a digital format. [0014] [0014] 098126121 1.2 Embodiment of Discrete Cosine Transform Circuit FIG. 2 shows a block diagram of a structure of an embodiment of a discrete cosine transform circuit 2QG. Discrete cosine transform circuit 200 is an embodiment of FIG. 1A and/or discrete cosine transform circuit 165. The discrete cosine transform circuit 2〇〇 includes a butterfly operation circuit for performing a butterfly algorithm, which is described in detail below. The butterfly and calculus circuit is designed as a pipeline architecture and includes three levels: an extraction stage 3〇1, a record 302, and an operation stage 303. As shown in Fig. 2, each element in the discrete cosine transform circuit 2 is connected through a bus bar. The instruction memory 253 stores an instruction to perform a discrete cosine conversion. The register Regl is used to store instructions read from the instruction memory 253. The extraction stage 301 receives and decodes the butterfly calculation command obtained from the register Regl in a clock cycle (or the first-clock cycle), and controls the memory level 3〇2 and the operation stage in the subsequent clock cycle. 3〇3. The control lines from the extraction stage 301 to the memory level 302 and the respective units in the operation stage 3〇3 are not shown in the figure. The memory level 302 includes a data memory 252 as a memory storage for storing image data coefficients, and a memory 251 for storing intermediate calculation results output by the arithmetic level 3〇3. According to the decoded instruction, the data set is read from the data memory 252 and the memory 251 in another clock cycle (or the second clock cycle) and directed to the multiplexer via the multiplexers 241, 242 and 23 0982044783-0 Form No. A0101 Page 8 / Total 45 Pages 201106174 [0015] ❹ [0016] 输出 Output of 231~234. The bus connects the outputs of the multiplexers 231 to 234 in the memory stage 302 to the corresponding registers Reg2 to Reg5 in the arithmetic stage 303. In this example, the operational stage 303 includes four registers Reg2~Reg5 and four arithmetic logic units ALU1~ALU4. Each of the registers in the registers Reg2~Reg5 receives a set of data from the corresponding multiplexers 231~234 and outputs them to the corresponding arithmetic logic unit as their input data. The entities of the corresponding multiplexer, arithmetic logic unit, or any other scratchpad are multiplexers, arithmetic logic units, or multiplexer entities that are linked to the scratchpad. The arithmetic logic unit ALU ALU4 respectively executes the same or different calculation formulas according to the received input data and outputs the calculation result in the -clock period (or the third clock period) according to at least the _resolved (four) instruction. Each _ arithmetic logic unit (such as ALU1) contains _ shifters (such as shifter 2〇1) for performing arithmetic shift operations and - adders/subtractors (such as adder/subtractor 221) To perform addition and subtraction. It is noted that _ and 252 can be formed by one or more memory blocks or wafers. The scratchpad includes an edge-triggered flip-flop, such as a D-type positive and negative [0017] 098126121 Discrete cosine transforming electrons, including lines 27〇 and 271, used to calculate the leaf results in the same clock cycle completed by the aforementioned calculation formula The arithmetic stage 3〇3 is passed to the memory stage 302. The calculation is 蛀 丹 丹 J. The multiplexers 231 to 234 are supplied as optional inputs. According to the decoded instructions, the registers Reg2~Reg5 can select the ^^ calculation result from lines 270 and 271 via multi-work-m in a clock cycle. For example, the multiplexer 233 includes an optional wheel entry 31. «One coffee, to line 270, optional input 32 and page 9 / total 45 pages form number A0101 0982044783-0 201106174 33 respectively via multiplexer 241 The 242 is coupled to the memories 251 and 252 and the optional input 34 is used to receive the binary digits 〇, for example, according to the bus width and the ALUs, the 52-bit long binary digits formed by the ALUs. According to the decoded instruction 'multiplexer 233, the calculation result can be output to the register Reg4' via the selection input 31. The selection input 32 or 33 reads the next set of data from the memory 251 or 252, and the selection input 34 receives 52 bits. Long binary digits 〇. As shown in FIG. 2, the input 44 of the multiplexer 234 can also receive a binary number of 52 bits long. [0018] 2. Butterfly Algorithm Architecture Embodiment [0019] 2. 1 Butterfly Algorithm Embodiment [0020] [0021] The image processing device 2_codes and displays the digitized still image or the video clip. The digital image is usually a matrix of image elements (or suffixes) - a ~ jin, double value clothing. For example, in the YCbCr color (four) system, the three main elements include - a luminance element Y and two chrominance elements Cb and Cr. The values of the luminance and chrominance elements are used to describe things like money and chrominance. The image processing device 200 can also be sunny at the "color material", "three primary colors TM color _. A digital image of the mother can be represented as three rectangles _, and each of the rectangular arrays (4) contains the values of the three elements of the image.像素J Hugh image formed by the pixel block, 4 material by 8 image (4) (4) can be 4 pixels by 4 pixel block, 8 pixel m block, 16 pixels by 16 pixel block or any other / A , , _ and the heart of the block. The image of the giant (four) block towel is like a ', έ t bar is also poor (for example, a main element in the YCbCr Baxin system) is formed by 7 white _ an image data 俜 098126121 Form No. A0101 Page 10 / Total 45 pages 0982044783-0 201106174 ❹ [0022] Matrix. It is assumed that the discrete cosine transform converts the vector X of length 根据 into a new vector coefficient X according to the linear transformation function Χ==Ηχ, where Η is a matrix, and X can be a row or column of a matrix of image data coefficients. The discrete cosine transform converts the image data coefficients from the spatial domain to the frequency domain. In the latter part of the paper, the image data matrix is represented by an array of two-dimensional indices. The elements in the matrix can be expressed as F [ i ] [ j ], where [i ], [ j ] are indices, i, j are integer variables, and the first (leftmost) index [i] is vertical. The index, while the second (rightmost) index [j] is the index in the horizontal direction. For example, F[3] [5] represents a matrix element located in the vertical position 3 and the horizontal position 5 in the matrix F.离散 Discrete cosine transform in image processing involves one-dimensional (1D) row conversion and column conversion of the image data coefficient matrix. Both 1D row conversion and column conversion are product operations of a series of multiple matrices, which increases the complexity of circuit design. A butterfly algorithm that is mathematically equivalent to a matrix multiplication product (as hereinafter referred to as a butterfly operation) is well suited for implementing a discrete cosine transform circuit without a matrix multiplication circuit. Different image or video compression specifications have different butterfly operations. For example, the 264 standard developed by the International Telecommunications Union (ITU) is also the MPEG-4 Part 10, or MPEG-4 Advanced Video Coding. , abbreviated as AVC), using discrete cosine transform X = H x, where: 098126121 Form number A0101 Page 11 / Total 45 pages 0982044783-0 201106174 [0023]

[0025] FIG. 3 shows a butterfly algorithm corresponding to a discrete cosine transform equation (〇). Figure 3 contains four wheeled nodes represented by x[〇], x[l], Χ[2], and Χ[3], represented by Χ[〇], Χ[1], ΧΕ2], Χ[3] The four output nodes, with the operation node mm of the eight plus sign '' + '. The plus sign '' + '' in the node indicates that the node performs the addition operation. The node in Figure 3 is directional. The lines are connected to represent their operation flow: the algorithm transfers the output value of each node from the node to the next node connected to the transfer line via the transfer line. _丨, 2 or _2, etc. marked next to the transfer line The constant table is not multiplied by the multiplication during the transfer process. The input values χ[〇], χ[1], x[2], and χ[3] can be substituted into the matrix elements in the column vector or row vector of the image data coefficient matrix. The basic unit in the butterfly algorithm is represented by a butterfly calculation unit in the present embodiment, such as a butterfly calculation unit ln. A butterfly calculation unit includes two input nodes and two output nodes. For example, the butterfly unit 111 includes Two output nodes x[l] and X[2] and two operation nodes 122 and 123 as output nodes. Nodes 122 and 123 respectively represent Addition of two input values. Node 122 performs an addition on the input value pair 1] and on the 2] value and produces an output value. Node 123 takes the input value x[l] and (-1 098126121 Form number A0101 page 12 / A total of 45 pages 0982044783-0 201106174 χ x[2]) performs an addition operation and produces an output value x[l] + (- lxx[2]), where the butterfly calculation unit 111 displays the multiplicand x[2] and the constant multiplied The number-1 is multiplied by the input value of node 123. The multiplier is represented by the number indicated by the transition line in Figure 3. The nodes x[0], x[3], 122, and 124 form another butterfly calculation. The nodes 121, 122, 125, and 126 form another butterfly unit. The output values of the nodes 122 and 123 are transmitted to the nodes 1 25-1 28 via the transfer line. When all the butterfly calculation units of FIG. 3 perform the foregoing After the operation, the algorithm shown in Fig. 3 is executed. Similarly, the other parts of Fig. 3 can also be interpreted in this way. ◎ [0026] The discrete cosine transform circuit 200 shown in Fig. 2 is designed to implement various Different butterfly algorithms. The corresponding butterfly calculation unit realized by the discrete cosine transform circuit is as follows. 2.2 Butterfly Calculation Unit Embodiment [0028] The control unit 261 receives and decodes the butterfly calculation instruction acquired from the instruction memory 253, and controls the discrete cosine circuit ^ 200 according to the decoded butterfly operation instruction to implement the butterfly shape. The butterfly calculation unit in the algorithm. One of the operations of the discrete cosine conversion circuit 200 is as follows. [0029] Please refer to FIG. 4, wherein the butterfly calculation unit 112 is expressed as: [0030] D[0],= D[0]x9 + D[l]x5 (1) [0031] D[IY = D[0]x5-D[l]x9 (2) [0032] The discrete cosine transform circuit includes performing an operation bit shift Cartridge shifter. In the present embodiment, x is indicated by a real variable χ and a positive integer variable y ((y represents 补 is a two's complement and is shifted to the right by y bit. Shift right 098126121 Form No. A0101 Page 13 of 45 Page 0982044783-0 201106174 The value of the Most Significant Bit (MSB) should be the same as the value of the most significant bit before the x-shift. Similarly, 'x((y means X is the complement of two and Shift y bit to the left. The value of the least significant bit after shifting to the left should be 0. Multiplication is performed by displacement operation, and equations (1) and (2) can be derived as: [0033] D[0], = D[0]x9 + D[l]x5 [0034] - D[0]x(8 + 1) + D[1]x(4 + 1) [0035] = (D[0]x8+ D[0] Xl) + (D[l]x4+ D[l] xl) [0036] = (D[0]x23+ D[QD +(D[1]x22+ D[l]) [0037] =(D[0]« 3+ D[0] ) + (D[l]«2+ D[.l] ) (3) [0038] D[l], =D[0]x5 -D[l]x9 [0039] = D [0]x(4 + 1)-D[1]x(8 + 1) [_] - (D[0]x4+ D[0]xl)-(D[l]x8+ D[l] :xl) [Delta][D[0]x22+ D[0]&gt; -(D[1]x23+ D[l]) [0_ = (D[0]«2+ D[0]) - (D[l] &lt;&lt;3+ D[l] ) (4) [0043] Assume that the image data coefficient converted as the ID column is 2X2 C, where [0044] c ά 0982044783-0 a C = b [0045] a, b, c and d are real numbers. 098126121 Form number A0101 Page 14 of 45 201106174 [_ _ calculus unit m with 2 χ 2 matrix c When performing _conversion, each matrix s of the matrix of the matrix will be respectively substituted for D[0] and D[l] in the butterfly calculus unit 112. (: matrix element C of the first column vector in the matrix [0][0] and C[0][1] will be substituted into the cores of equations (1) and (2) and D[l], respectively, and then the matrix elements of the second column vector in the C matrix are 丨][〇] and C[1][1] will be substituted into d[〇] and d[1] in equations (1) and (2), respectively. 2x2 matrix C is 2x2 matrix C is converted into 1 d column by butterfly calculation unit 丨丨2. Output examples, where: ο cai?f and [0048] C, [〇][〇]=a, =C[0][0]x9 + C[0][l]x5, (5) [0049] C, [〇][l]=c, =C[l][0]x9+C[l][l]x5, (6) [0050] C, [l][〇]=b, =C[ 0][0Jx5 - C[0][l]x9, (7) [0051] C [l][l]=d,:=ttl][〇]x5-C[l][l]x9. (8 [0052] Another image data coefficient 2x2 matrix Y is an embodiment of ID line conversion: [0053] p -, es ν - 6 rh [0054] where e, f, g, and h are real . [0055] When the butterfly calculation unit 112 performs ID line conversion of the 2x2 matrix Y, the matrix γ 098126121 Form No. A0101 Page 15 / Total 45 pages 0982044783-0 201106174 The matrix elements in each row vector are respectively substituted into the butterfly calculation D[〇] and D[1] in the unit. That is, the matrix elements Y[〇][G] and Y[1][G] in the first row vector are substituted into D[0] and Dm'no](1) and Y[1 in the equations (!) and (2), respectively. ][1] substituting D[0] and DU] in equations (1) and (2), respectively. 2x2 matrix Υ, which is an output example of 2D2 matrix conversion by the butterfly calculation unit 112 for 1D line conversion, where: [0056] Yr= _r h\ nmm , and [0057] r [0][0]=e' = Y[〇][0]x9 + Y[l][〇]x5, (5a) [0058] Y, [〇][l]=g, =Y[0][0]x5 - Y[l][ 〇]x9, (6a) [0059] [1][〇] = ί( = Y[〇][1]x9 + Y[1][1]x5, (7a) [0060] Y&gt; = Υ[〇 ][1]χ5-Υ[1]Π3χ9&lt;(8a) [〇〇61] 21) Discrete cosine substitution of matrix ¥ can be substituted into equations 5a, 6a, 7 and 8a by matrix γ by matrix γ The matrix Y is done. 3. Discrete Cosine Transform Circuit Operation Embodiment [0063] As described above, the butterfly calculation unit 112 can be expressed by equations (3) and (4). The discrete cosine transform circuit can implement the butterfly operation unit 112 by performing equations (3) and (4). That is, the image processing apparatus 1 includes at least three instructions for implementing the butterfly calculation unit 112. The first butterfly calculation command controls the butterfly 0982044783-0 discrete cosine transform circuit 200 to perform (D[l] &lt;&lt;2 + D[l]) of equation (3) and (D[0] of equation (4) &lt;<2 + D[0]). That is, the first _ form number A0101 page 16 / a total of 45 pages 201106174 calculus instructions are used to achieve: _] tl = (D[l]&lt;&lt;2+ D[l]); and (8) _5] t2= 〇 ) [〇] "2+ D[0]). (1〇) [1] The setting of 1; 1 and t2 is variable ' can be implemented via a register, but is not limited thereto. Equation (9) is equivalent to the transition line from D [丨] to node 丨丨2 j in the butterfly calculation unit 丨丨2. Equation (10) corresponds to a transition line from D[〇] to node 1122 in butterfly calculation unit 112. Ο [〇〇67] The second butterfly calculation command controls the discrete cosine transform circuit 200 to perform (D[0]&lt;3+ ΰ[0]) of equation (3) and (d[1] of equation (4) ]&lt;&lt;3 + D[l]). That is, the second butterfly calculation instruction is used to realize: Country 1:3= 〇)[0]&lt;&lt;3+ D[〇]); and ((1) _] t4= (D[l]«3+ D[i] ) (12) [0070] Equation (11) corresponds to a transition line from D[ 0 ] to node 1121 in the butterfly calculation unit 112. Equation (12) is equivalent to a butterfly from the butterfly calculation unit 12 [j] 转移 to the transfer line of node 112 2. [〇〇71] The third butterfly calculation command controls the discrete cosine transform circuit 200 to perform the operations of equations (3) and (4). That is, the third butterfly calculation instruction is It is used to realize: [0072] D[0]' = t3 + tl; and (13) just D[l], = t2 - t4. (14) [0074] Equation (13) is equivalent to the butterfly calculation unit 112. Node 1121. Equation (14) corresponds to node 1122 in butterfly calculation unit 112. [0075] The control information obtained by operation 7L (operand) is also included in butterfly calculation finger 098126121 Form No. A0101 Page 17 of 45 </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> Discrete cosine The bus in the switching circuit has sufficient bandwidth to transmit the data in a clock cycle. The connection of the control signals is not shown in Figures 5 through 8. Each multiplexer of the memory stage 302 is based on the decoded instructions. Select one of the optional inputs and output it. [0076] 3.1 jth clock cycle [0077] 3. 1. 1 extraction stage [〇〇78] in the jth clock cycle, where j is an integer, when The discrete cosine circuit 200 executes the butterfly calculus unit 112 in a matrix C. The control unit 261 of the extraction stage 301 receives and decodes the first butterfly calculus instruction in the jth clock cycle to control the memory stage 302 in subsequent clock cycles. And the operation stage 303. [0079] 3.2 (j + l) clock cycles; . :: !;

[0080] 3.1.1 Memory Level [0081] Referring to FIG. 5, in the (j+1)th clock cycle, the memory level 3〇2 prepares data according to two calculation formulas in the first butterfly calculation instruction. To the register Keg2~Reg5 in the operation stage 303, wherein the two calculation formulas in the first butterfly calculation instruction are the operation elements of the first column and the second column of the matrix C, respectively. As shown in FIG. 5, the image data coefficients c[〇][〇] and C[l][〇] are read from the data memory 252 at the optional input 12 and the multiplexer 2 3 3 that are transmitted to the multiplexer 231. Optional input W, read data image coefficients (:[〇][1] and [[1][1] from the data memory 2 5 2 and transmit to the optional input 22 and multiplexer of the multiplexer 232 Optional rounding of 234 is 43. 098126121 Form No. A0101 Page 18 of 45 0982044783-0 201106174 [2.22] 3.2.2 Extraction Stage The control unit 261 in the first extraction stage receives the code second in the same clock cycle. Butterfly calculation command. ^ [0084] 3.3 (j + 2) clock cycles _] ^ Refer to Figure 6, detailing the three levels of the (j + 2) clock cycles

Level &quot; IX 3 3 ο [Each register in the _ computing stage receives the corresponding data from the corresponding multiplexer in the previous stage and provides it to the arithmetic logic unit ALUWLU4 via the link. Each arithmetic logic unit takes two input values from the data provided by the scratchpad. As shown in Figure 6, the input to each arithmetic logic unit_value_ is next to the corresponding arithmetic logic unit. The value indicated by the link cylinder shift H or the adder/subtracter is the input value transmitted to the cartridge shifter or adder/subtractor via the link. For example, the shifter 201 and the adder/subtractor 221 respectively receive 〇C[〇][〇] as an input ash element. [0088] The operation of the first column of the matrix c according to the first butterfly calculation instruction, the operation logic The unit ALU1 substitutes the input value C[0][0] into D[0] to complete the nose of the formula (1〇) and outputs 5C[〇][〇] 'the nose logic unit ALU3 with the input value C[〇][i Substituting D[l] to complete the operation of equation (9) and output. The arithmetic logic unit ALU1 completes the operation of connecting from D[0] to the node U22 in the butterfly calculation unit (1) in the clock cycle. Specifically, the shifter and the adder/subtracter in each of the arithmetic logic units respectively perform the shift operation and the addition/subtraction operation in the corresponding equation. For example, when 098126121 form number A〇101 page 9/45 page field 〇 982 〇 44783-〇201106174 arithmetic logic unit ALU1 substitutes C[0][0] into D[0] for equation (10) When calculating, the shifter 2〇1 in the arithmetic logic unit obtains 4xC[0][0] by shifting (:[〇][〇] to the left by 2 bits and outputs the operation result 4xC[0][0] Go to adder/subtractor 2 21. Adder/subtracter 2 21 receives and adds two input values ' 4xC[0][0] and C[0][0], and then outputs 5xC[0][0]. The internal operation modes of other arithmetic logic units are also similar. [0092] According to the operation of the first butterfly calculation instruction in the second column of the matrix C, the operation logic unit ALU2 takes the input value C[1]. [0] Substituting D[0] to complete the operation of the formula (1〇) and output 5C[1][0], the arithmetic logic unit ALU4 substitutes the input value C[l][l] into D[l] to complete the formula (9) The operation is output and the output values 5C[〇][〇], 5C[1][0], 5C[0][1], and 5C[1][1] are stored in the memory 251 as intermediate calculation results. The logical unit ALU ALU4 performs the same calculation in parallel with different data in the image data coefficients to achieve a single finger. Single instruction stream &amp; nd multiple data streams 'SIMD' architecture. It should be noted that the discrete cosine transform circuit is not limited to SIMD. Two of the arithmetic logic unit ALU ALU4 can perform the same calculation to implement a SIMD. Architecture, the other two arithmetic logic units can perform another calculation to implement another 81-inch architecture, thus implementing the Multiple instruction streams and multiple data streams (MIMD) architecture. 2 Memory level 凊 Referring to FIG. 6, in the (j+2)th clock cycle, the memory level is according to the second 098126121 Form No. A0101 Page 20/45 pages 0982044783-0 201106174 [0093] [0094] [0095] [0098] 098 098126121 The butterfly calculation instruction is used by the operands of the first column and the second column of the matrix C to provide the data data to the register in the operation stage. As shown in FIG. The memory 252 reads the image data coefficients C[0][0] and c[1][〇] and transmits them to the optional input 12 of the multiplexer 231 and the optional input 33 of the multiplexer 233 from the memory 252. Reading image data system C [0] [1] and c [1] [1] and transmitted to the multiplexing unit 22, optionally 232, optionally with an input 234 of the multiplexer 43 input. 3. 3. 3 Extraction Stage The control unit 261 in the extraction stage 301 receives and decodes the third butterfly calculation instruction in the same clock cycle. 3. 4 (j + 3) clock cycles Please refer to Figure 7' for a detailed description of the operation of three stages in the (j + 3) clock cycle. 3. 4. The calculation level is calculated according to the second butterfly calculation instruction in the first column of the matrix C. The operation logic unit ALU1 substitutes C[0][0] into D[0] to complete the operation of the equation (11) and outputs 9C[0][0], the arithmetic logic unit AL1I3 substitutes C[0][1] into D[l] to complete the operation of equation (12) and outputs 9C[0][1]. According to the operation of the second butterfly calculation instruction in the second column of the matrix C, the operation logic unit ALU2 substitutes D[0] into C[1][0] to complete the operation of the equation (11) and outputs 9C[1][0]. The arithmetic logic unit ALU4 substitutes C[l][l] into D[l] to complete the operation of equation (12) and outputs 9C[1][1]. The discrete cosine transform circuit 200 includes connection lines 2 70 and 271 for outputting values 9C[0][0], 9C[1][0], 9C[0][1], and 9C[1][1] (j + 3) The clock cycle leads to the previous memory level. Output value 9C[0][0], 9C[1][0], 9C[〇ni], form number A0101 Page 21/45 pages 0982044783-0 201106174 9C[1][1], 5C[0] [0], 5C[1][0], 5C[0][1], and 5C [1] [1] are intermediate calculation results. [0102] [0102] [0104] 098126121 3. 4 · 2 memory level In the (j + 3) clock cycle, the memory level 302 is used according to the third butterfly calculation instruction The two calculations of the intermediate data provide additional data to the registers in the operational stage 303. The intermediate data includes an output of the two computational expressions of the operational logic unit corresponding to the first butterfly computational instruction and an output of the two computational expressions of the operational logic unit corresponding to the second butterfly computational instruction. It should be noted that the 'output logic unit ALII1 and the output of the arithmetic logic unit ALU2', such as 9C[0][〇] and 9C[1][〇], are routed via the data transmission line 27 to the optional input 31 of the multiplexer 233. Without juxtaposition 9C[0][0] and 9C[1] [〇] in memory. The outputs of the arithmetic logic unit ALU3 and the arithmetic logic unit 乩 ", such as 9C[0][1] and 9C[1][1], lead to the optional input 41 of the multiplexer 234 without storing 9C[0][1] And 9C[i][i] in the memory. Therefore, the operation stage 330 selectively receives 9C[0][0], 9C[l][〇], and stored 5C in the next clock cycle. 0][0] and 5C[l][〇] are output from the memory 251 and output to the multiplexer 232, and 5C[0][1] and 5C[1][1] are read from the memory 251 and output. Go to the multiplexer 231. 3. 4. 3 The control unit 261 in the extraction stage extraction stage 301 can receive and decode other butterfly operation instructions in the (j + 3) clock cycles. 3. 5 (j + 4) Clock cycle Please refer to FIG. 8 for details of the operation level of the (j + 4) clock cycle, 0982044783-0 Form No. Α0101, page 22/45 pages, 201106174. [0105] 3. 5. The calculation level is used according to the calculation formula of the intermediate calculation data relative to the first column of the matrix c according to the third butterfly calculation instruction, and the arithmetic logic unit ALU1 substitutes 5C[0][1] into t3 and 9C[0]. [0] Substituting t1 to complete the operation of equation (13), and output 5C[0][1] + 9C[0][0], which is equivalent to equation (5). The arithmetic logic unit ALU3 substitutes 5C[〇][〇] into t2, 9c[〇][1] and substitutes t4 to complete the operation of the equation [0107] (14), and inputs A5C[0][0]-9c[〇 ][1], which is equivalent to the formula (7). &quot;:. . . . Ο [0108] The calculation equation for the intermediate calculation data relative to the second column of the matrix C according to the third butterfly calculation instruction ALU2 substitutes 5C[1][1] into t3, 9C[1][0] and substitutes ti to complete the operation of equation (13), and outputs 5C[1 ] [1 ] + 9C[l ] [〇], which is equivalent to Equation (6). The arithmetic logic unit ALIM substitutes 5C[l][〇] into t2, 9C[1][1] and substitutes into t4 to complete the operation of equation (14), and outputs it, which is equivalent to equation (8). The discrete cosine transform circuit can execute the three butterfly calculus commands to apply the butterfly unit 112 to the matrix C. Note that '5C[0][0], 5C[0][1], 5C[l] [〇], 5C[1][1], 9C[0][0], 9C[0][1], 9C[1][0] and 9C[1][1] are in the (j + 4) In the clock cycle, 8 are input to different values of the arithmetic logic units ALU1 to ALU4. Of the 8 values, 4 are read from the memory 251, and the remaining values are calculated by the arithmetic logic units ALU1 to ALU4. Transferred by lines 270 and 271. The memories 251 and 252 can each have 2 埠, and the bandwidth of the 2 足够 is enough to pass 8 of the values 098126121 Form No. A0101 Page 23 / Total 45 Page 0982044783-0 201106174 I. Therefore, the memory in the memory level does not need to have 4 为了 in order to simultaneously transfer 8 values to 4 arithmetic logic units. 4. Variations [0110] FIGS. 9A to 9E show different embodiments of the butterfly calculation unit. Referring to FIG. 9A, since there is no constant multiplier in the butterfly calculation unit 113, the operation of the node 1131 or 1132 can be realized and completed by one of the arithmetic logic units ALU1 A ALU4 in one clock cycle. Referring to FIG. 9B, a horizontal transfer line from the node D[0] to the node 1141 and a horizontal transfer line from the node D[1] to the node 1142 respectively have a constant η, if the value of η is an integer 2 or The fraction 1/2 k-th power (that is, n = 2k or n = mk ), where k is an integer, the operation represented by the transition line from node D[0] to node 1141 and the slave node D [ 1 ] The operation represented by the transfer line to node 114 2 can be accomplished via a bit shift operation in the shifter. One of node 1141 and node 114 2 can be represented as an addition done by the adder. Thus, the operations represented by the transition lines in node 1141 and node 1142 and associated nodes can be accomplished in one clock cycle via one of operational logic units ALU1 through ALU4. [0112] Similarly, in FIG. 9C, if the value of m is an integer 2 or a fraction 1/2 of the f-th power (that is, m = 098126121 form number A0101 2' page 24 / total 45 pages 0982044783-0 201106174 or m = where f is an integer Ο 攸 攸 攸 攸 到 到 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 115 Dan Huacheng. In the first example, 'n4m and the integer 2 or fraction 1/2 of the integer under-squares, the expression represented by each transfer line may need to be separated: more logic in the cosine conversion The unit is completed via more clock cycles. In the first example, the butterfly calculation command in the 'Word memory 253 can control the discrete cosine transform. The paste is preferentially executed next to the transfer line. There is no constant next to the transfer line. The operation of the multiplier. ^ [0113] 〇

Referring to Figure 9D, if n and the singularity are integer 2 or fractional 1/2 integer power, the operation represented by any of the transfer lines to node 1161 can be accomplished via a bit shift operation of the cartridge shifter. The operation represented by the other transfer lines to the node 1161 can be completed by one of the arithmetic logic units in one clock cycle. Thus, the operations represented by node 1161 and the transitions represented by the transition lines connected to node 1161 can be accomplished in two clock cycles by the arithmetic logic unit ALUWLU4. ^ The operation corresponding to point 1162 can be understood as the same. P

[0114] In addition, in the second fiscal n is an integer 2 or a fractional power of 1/2, _ is different from the integer power of 2 or fraction 1/2} (that is, ^2' ±1 or m= 098126121) Form No. A0101 Page 25 of 45 0982044783-0 201106174 ± 1 ) The operation represented by the node 1161 and the transition line connected to the node 仍6丨 can still be performed by the arithmetic logic unit ALU1~ALU4 One of them is completed in two clock cycles. In this case, the arithmetic logic unit preferentially executes the operation of the transfer line associated with m and then performs the operation of the transfer line associated with n. In the second example, the butterfly calculation command in the instruction memory 253 can control the discrete cosine transform circuit 200 to perform an operation related to m and then perform an operation related to n. Similarly, in the third example, it is an integer 2 or a fractional power of 1/2, and η is an integer two of the integer 2 or fraction 1/2 (that is, 仏2k ±1 or η: mk ±1), the operation represented by the node 1161 and the operation represented by the transfer line connected to the node 1161 can still be completed in one of two clock cycles by one of the arithmetic logic units ALU1 to ALU4, in this case Next, the arithmetic logic unit preferentially executes the operation of the transfer line associated with n and then performs the operation of the transfer line associated with m. In the third example, the butterfly calculation command in the instruction memory 253 can control the discrete cosine transform circuit 2 to perform an operation related to η before performing an operation related to m. The second example applies equally to the node 1162 and the transition line connected to the node 1162 as in the third example. FIG. 9E is an operation example related to the butterfly calculation unit 117. Figure 1〇12 shows the discrete cosine transform circuit 2〇〇 butterfly calculation unit 117 to matrix c 098126121 Form No. A0101 Page 26 of 45 0982044783-0 201106174 [0116] 运作 Operation in three consecutive clock cycles . The transition line 1173 associated with the node 1171 is associated with the constant multipliers 9 and 8, respectively, with 9 = 23 + 1 and 8 = 23, respectively. As shown in FIGS. 10 to 12, when the discrete cosine transform circuit 2 performs column conversion on the matrix c using the butterfly calculation unit 117, the arithmetic logic unit 八1^141^4 first performs the transfer line 1173 associated with the multiplier 9. The corresponding operation then performs the operation corresponding to the transfer line 1174 of the multiplier 8. Similarly, the transfer lines 1175 and 1176 of the butterfly calculation unit 117 connected to the node 1172 are associated with constant multipliers 8 and 9, respectively, where 8 = Ο

+ 1. As shown in FIGS. 10 to 12, the arithmetic logic unit ALU ALU4, the arithmetic logic units ALU1 to ALU4 first execute the operation corresponding to the transfer line 1176 associated with the multiplier 9 and then execute the transfer line 1175 associated with the multiplier 8. The operation. The operation of the arithmetic logic unit in the matrix c in the butterfly calculation unit 117 can be completed in only two clock cycles. [0118] 098126121 5. Conclusion As described above, the image processing apparatus can store different butterfly calculation instructions to complete different butterfly algorithms by form number A〇W page 27/45 pages 0982044783-0 201106174 A discrete cosine transform circuit for implementing different image and video compression standards, such as a discrete cosine transform circuit for MPEG2 and H.264. As more and more compression standard applicable instructions are integrated into the instruction memory, the flexibility and standard compatibility of the image processing apparatus 100 will also increase. The four arithmetic logic units simultaneously perform different operations according to different image data coefficients to achieve MIMD and improve the overall efficiency of the discrete cosine transform circuit. In addition, the use of discrete cosine transform circuit memory does not require four passes through the data transfer path. In summary, the discrete cosine transform circuit proposed by the present invention is applicable to various image processing apparatuses, including but not limited to set top boxes, media players, televisions, and video conferencing apparatuses. [0125] [0125] In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above-mentioned embodiments are merely preferred embodiments of the present invention, and those skilled in the art will be able to incorporate the equivalent modifications and variations in the spirit of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram showing an embodiment of an image processing apparatus 100 including a discrete cosine transform circuit 165. 1B is a block diagram showing the structure of a second embodiment of an image processing apparatus, showing how to receive digital content from a network. 2 is a block diagram showing the structure of one embodiment of a discrete cosine transform circuit. Figure 3 is a schematic diagram of a butterfly algorithm. Figure 4 is a schematic diagram of one of the units of the butterfly algorithm. Figure 5 is a diagram showing the operation of the discrete cosine transform circuit in the (j +1)th clock cycle. 098126121 Form No. A0101 Page 28 of 45 0982044783-0 201106174 Intention [0126] Figure 6 is a discrete cosine transform circuit (Ten clock cycle operation indication [0127] Γ: Discrete cosine conversion circuit in the ((10) clock cycle operation just y is the discrete cosine conversion circuit at the (j+4)th intent. The demonstration [reward ~ 9E is the implementation of the butterfly calculation unit (four) I 1: 0130] Figure 1 〇 ~ 12 is the discrete cosine conversion circuit, the butterfly calculus in the continuous clock cycle of the operation of the matrix Circle. [Main component symbol description] [〇13!] Image processing device 1〇〇, 1〇1 Ο [0132] Processor 151 [0133] Main memory 152 [_ Non-volatile memory 153 [0135] Mass storage device 154 [0136] Content protection unit 丨 55 [0137] Demodulator 156 [_] Tuner 15 7 [0139] Power supply 158

Kf'irrv [0140] Crystal Oscillator 1 5 9 098126121 Form No. A01.01 Page 29 of 45 〇982〇44783~〇201106174 [0141] I/O Unit 160 [0142] Audio Output Unit 161 [0143] Video Output Unit 162 [0144] Antenna 1 6 3 [0145] 埠 164 [0146] Discrete Cosine Transform Circuits 165, 200 [0147] Network Interface 170 [0148] Shifters 201, 202, 203, 204 [0149] /Subtractor 221, 222, 223, 224 [0150] Multiplexer 231, 232, 233, 234, [0151] 241 '242 [0152] Memory 251 [0153] Data Memory 252 [0154] Instruction Memory 253 [0155] Control Unit 261 [0156] Lines 270, 271 [0157] Extraction Stage 301 [0158] Memory Level 30 2 [0159] Operation Stage 303 098126121 Form Number A0101 Page 30 / Total 45 Page 0982044783-0 201106174 [0160] Registers Regl, Reg2, Reg3, Reg4, Reg5 _1] arithmetic logic units ALU1, ALU2, [0162] ALU3 'ALU4 [0163] Butterfly calculation units in, n2, 113, 114, 115, 116, 117

G

098126121 Form No. A0101 Page 31 of 45 0982044783-0

Claims (1)

201106174 Seven patent application scope: • A discrete cosine transform circuit, - extraction stage, - memory level and 'item calculation circuit, with % heterogeneous, its φ, the extraction stage receives and solves the Ma butterfly shape calculation refers to the human set /. The memory level includes a memory memory bank for storing the intermediate calculation data outputted by the shadow operation level, the image data and the calculation instruction, and the butterfly memory is decoded on the first day of the butterfly calculation circuit. a first set of data of the stage; and the cycle of the cycle of the cycle is stored in the operation stage comprising a plurality of registers, a first operation. Calculating a logical unit, the complex register is from the data; the data is used as the round entry data of the operation level, and the fourth storage library receives the first set of second operational logic units respectively from the = arithmetic logic unit and the pair Input data execution register receiving-group input data shape calculation instruction in the first-clock cycle &amp; according to at least - decoded butterfly-calculated calculation result; - clock cycle output of the first of the 'the _ calculus circuit In the same-clock cycle including 1 way, the count is calculated in the 4th-calculation operation, so that at least one register is in the first;;;; from the operation level to the record During the period, the third set of data received from the line and after the pulse period can be selected to receive the next set of data. The calculation result or the discrete cosine conversion circuit according to item 1 of the memory storage, wherein the operation stage performs the second group of data obtained by the library in the third clock cycle. The second result and the discrete cosine transform circuit as recited in claim 1, wherein the memory stage includes at least a conversion circuit 'where the» is such that at least the register is at least one of 098 丨26121 Form No. A010I Page 32 of 45 201106174 The decoding butterfly algorithm can choose to receive the calculation result from the line or obtain the next set of data from the memory bank. 4. As described in claim 1 a discrete cosine transform circuit, wherein the first arithmetic logic unit and the second operational logic unit respectively perform calculations substantially equal to multiplication with different data, the data comprising at least one set of image data coefficients or the calculation result. The discrete cosine transform circuit of claim 4, wherein the first operational logic unit and the second operational logic unit respectively comprise a cylinder shifter and an addition 6. The discrete cosine transform circuit of claim 4, wherein the arithmetic stage includes a third operational logic unit and a fourth operational logic unit, in the first calculation At the same time, another second calculation formula is executed according to different data, and the third operation logic unit and the fourth operation logic unit respectively perform a third calculation formula according to at least one set of image data coefficients or the calculation result. The discrete cosine transform circuit of claim 1, wherein the operation stage comprises a third operation logic unit and a fourth operation logic unit, and the third calculation formula is executed according to different data, respectively, while the first calculation formula is executed, The third arithmetic logic unit and the fourth arithmetic logic unit respectively perform a third calculation formula according to at least one set of image data coefficients or the calculation result. 8. The discrete cosine transform circuit according to claim 1, wherein The butterfly calculation unit operation performed by the calculation stage includes multiplying the first image data coefficient by the first constant, The image data coefficient is multiplied by the second constant, and the two multiplication results are added together, if the first constant differs from the integer power of 2 or 1/2 by one and the second constant is an integer power of 2 or 1/2. The multiplication operation of the first image data coefficient takes precedence over the second image data coefficient multiplication 098126121. Form No. A0101 Page 33/45 pages 0982044783-0 201106174 The calculation operation is performed. 9. An image processing apparatus includes: The discrete cosine transform circuit includes an extraction stage, a memory stage and an operation stage, wherein the extraction stage receives and decodes a butterfly calculation instruction set; the memory stage includes a memory storage for storing image data coefficients and the operation level Outputting intermediate calculation data, and outputting, according to at least one decoded butterfly calculation instruction, a first set of data stored in the memory level in a first clock cycle of the butterfly calculation circuit; and wherein the operation stage includes a plurality of registers, a first arithmetic logic unit and a second operational logic unit, the complex register receiving the first set of data from the memory repository as an input to the computational stage The first arithmetic logic unit and the second arithmetic logic unit respectively receive a set of input data from the complex register and perform a first calculation formula on the set of input data, according to the at least one decoded butterfly calculation instruction. a second clock cycle after the first clock cycle outputs a calculation result of the first calculation formula; wherein the butterfly calculation circuit includes a line that is to be used in the same clock cycle in which the first calculation operation ft is completed The calculation result is guided from the operation level to the memory level, so that at least one register can select to receive the calculation result from the line or receive from the memory repository in a third clock cycle after the second clock cycle. a set of data. 10. The image processing apparatus of claim 9, wherein the calculation stage performs the second calculation formula in the third clock cycle with the calculation result and the second set of data obtained from the memory storage. The image processing device of claim 9, wherein the memory level further comprises at least one multiplexer, such that at least one register is based on at least one solved 098126121, form number A0101, page 34, total 45 pages 0982044783-0 201106174 The code butterfly algorithm can choose to receive the calculation result from the line or obtain the next set of data from the memory repository. 12. The image processing apparatus of claim 9, wherein the first arithmetic logic unit and the second arithmetic logic unit respectively perform calculations substantially equivalent to multiplication with different data, the data comprising at least one set of images Data coefficient or the result of the calculation. The image processing device of claim 12, wherein the first arithmetic logic unit and the second operational logic unit respectively include a cartridge shifter and an adder for performing the calculation substantially equivalent to multiplication. The image processing device of claim 12, wherein the operation stage comprises a third operation logic unit and a fourth operation logic unit, and while the first calculation formula is executed, respectively performing another according to different data In a second calculation formula, the third operation logic unit and the fourth operation logic unit respectively perform a third calculation formula according to at least one set of image data coefficients or the calculation result. 15. The image processing apparatus of claim 9, wherein the operation stage comprises a third operation logic unit and a fourth operation logic unit, and performing the third calculation according to different data while executing the first calculation formula The third arithmetic logic unit and the fourth operational logic unit respectively perform a third calculation formula according to at least one set of image data coefficients or the calculation result. The image processing device of claim 9, wherein the butterfly calculation unit operation performed by the calculation stage comprises multiplying the first image data coefficient by the first constant, the second image data coefficient and the second Multiplying the constants and adding the two multiplied results. If the first constant is different from the integer power of 2 or 1/2 and the second constant is an integer power of 2 or 1/2, the first image is obtained. The multiplication of the data coefficients is performed in preference to the multiplication of the second image data coefficients. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. 098126121 Form No. A0101 Page 36 of 45 0982044783-0