201106164 ViT(39-UO 10100-TW 31323twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種資料提取方法及裝置，且特別是 有關於一種可確保資料有效性的資料預先提取方法及裝 置。 【先前技術】 一般匯流排裝置要讀取記憶體中的資料時，會透過匯 流排傳送一個記憶體存取請求給晶片組。此時，晶片組除 了會到處理器或記憶體中提取裝置所請求的資料外，為了 保註讀取速度，還會預先提取（Pre-fetch) —部分資料並 存放於一個預先提取缓衝器中，藉以在匯流排裝置提出下 一個記憶體存取請求時，能夠直接以預先提取的資料作回 應’進而縮短匯流排裝置讀取資料的時間。 以週邊元件互連（peripherai Component Interconnect， PCI)匯流排上的直接記憶體存取（Direct Memory Access， DMA)引擎為例，當其要讀取記憶體中4個位元組（Byte) 的寅料日守，若資料的位址是在記憶體的buffer[0]，則晶片 組除了會將buffer[0]的資料回應給DMA引擎外，還可預 先提取64個位元組的資料（除了會取到buffer[〇]，還可能 會取到buffer[l]中的資料），並將此資料儲存於預先提取 缓衝器中。據此，不僅可提供DMA引擎所需的資料，存 放在預先提取緩衝器中的資料也可在DMA引擎提出下一 個記憶體存取請求時，直接提供給DMA引擎。 201106164 VIT09-001OIOO-TW 31323twf.doc/n 一然而’若在DMA引擎提出下—個記憶體存取請求之 前，系統更新了記憶體中的資料，則原先由晶片組預先提 取亚存放在預先提取缓衝器中的資料就會失效。若此時晶 片組仍敵㈣先提取緩衝H巾的失效賴來回應應八 引擎，勢必會造成DMA引擎讀取到錯誤的資料/ 對於上述預先提取貧料可能存在錯誤的情形， 術提供了許多對應的解決方案。舉例來說，當系統 接收到處理n對於記㈣的以㈣（cpu tQ __ wnte cycle)時，抑或是偵測到有中斷（如如耶〇發 即可ί斷記憶體的資料已被更新，此時可藉由將預先提寸取 級衝裔中的貧料宣告無效，從而避免讀取到錯誤的資 、士然而’即便習知技術能_應上述系統絲的改 適日守地將預先提取資料宣告無效以避免讀 許多情況是晶片組無法债測或判斷的，例如^理哭本】 我更新内部的快取記憶體（Cache)時，晶片組即& 結果仍有可能造成資料讀取錯誤。 于〇, f發明内容】 本發明提供—種資料預先提取方法，針 預測的資料，設定触提取#料的有效時間，可確 提取資料的有效性。 保預先 本發明提供—種資料預先提取裝置，利用計 預先棘資料的存續時間，並在其存續超過有效時=計 立即旦告其失效，從而避免可能的讀取錯誤。 τ’ 201106164 viujy-u01〇l〇〇.Tw 31323twf.doc/n 本發明提出-種資料預先提取方法，適用於晶片組。 ^方法係在触龍輯裝置對於第—㈣的讀取指八 =預=取接續在第-資料之後的第二資料並儲存於^ 也累計此第二資料存放在緩衝器内的存 間是否達到或超過-有致時 二或超過有效時間時，即宣告預先提 叶時一 Π料預先提取褒置，其包括緩衝器、 所提取 間。控制器係雛至暫存器、緩衝哭及内：存績時 續在第-資料之後的第時，預先提取接 時器累計第二資料存放在緩衝器’亚利用計 器所累計的存續時間達到或超過有效ΘΙ^Γ間’而當計時 所儲存之第二資料宣告無效。“叫，即將缓衡器 本發明更提出一種計算機系 組及匯流聽置。料記憶體儲.二記憶體，晶片 —資料之後的第二資料。晶片組貝t及接續在第 置耦接至晶片組。其中晶月細 / 5己憶體。匯流排裝 緩衝器，並利用計時 器。其中緩衝器儲存從記憶“=_計，及控制 資料存放在缓衝器内的存續時間。貝D t計時器累計 =器，當控制器接收到匯流排接3衝器及 伯令時，預先提取第二資料以儲存於、弟一貝料的讀取 201106164201106164 ViT(39-UO 10100-TW 31323twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a data extraction method and apparatus, and in particular to a method for ensuring data validity. Pre-extraction method and device for data. [Prior Art] When a bus device reads a data in a memory, it transmits a memory access request to the chip set through the bus bar. At this time, the chip group goes to the processor. Or in addition to the data requested by the extraction device in the memory, in order to save the reading speed, pre-fetch is also extracted (pre-fetch) - part of the data is stored in a pre-fetch buffer, so that the next device is presented in the busbar device. When the memory access request is made, the data can be directly responded to by the pre-extracted data, thereby shortening the time for the bus device to read the data. The direct memory access on the peripheral component interconnect (PCI) bus bar ( Direct Memory Access, DMA) engine, for example, when it wants to read 4 bytes of memory in the memory, if the data The address is in the buffer[0] of the memory, in addition to the buffer group will respond to the DMA engine, the chipset can also extract 64 bytes of data in advance (except for buffer [〇], It is also possible to retrieve the data in buffer[l] and store this data in a pre-fetch buffer. According to this, not only the data required by the DMA engine but also the data stored in the pre-fetch buffer can be provided. The DMA engine can be directly supplied to the DMA engine when the next memory access request is made. 201106164 VIT09-001OIOO-TW 31323twf.doc/n One, however, if the DMA engine proposes a memory access request, the system If the data in the memory is updated, the data stored in the pre-extraction buffer by the chipset will be invalidated. If the chipset is still enemies (4), the failure of the buffered H-bucket will be extracted first. The engine will inevitably cause the DMA engine to read the wrong data. For the above-mentioned pre-extraction of poor materials, there may be many corresponding solutions. For example, when the system receives the processing n for the record (4) (4) (cpu tQ __ wnte cycle), or if an interrupt is detected (for example, if the message is stunned, the data of the memory has been updated, and this can be done by pre-empting the grading The poor material is declared invalid, so as to avoid reading the wrong capital, but 'even if the know-how can _ the above-mentioned system silk, the pre-extracted data will be invalidated to avoid reading many cases, the chip group can not be tested. Or judge, for example, crying] When I update the internal cache (Cache), the chipset is & the result may still cause data read errors. The invention provides a method for pre-extracting data, and for predicting the data, setting the effective time of extracting the material, and determining the validity of the data. Pre-existing The present invention provides a pre-extraction device for data, which utilizes the duration of the pre-pigment data and, when its surpassing is valid, expires immediately, thereby avoiding possible read errors. τ' 201106164 viujy-u01〇l〇〇.Tw 31323twf.doc/n The present invention proposes a method for pre-extracting data, which is suitable for a wafer set. ^ Method is in the touch dragon device for the reading of the first (four) refers to eight = pre = take the second data after the first data and stored in ^ also accumulate this second data stored in the buffer When the time is reached or exceeded - when the time is two or more than the effective time, the pre-extraction device is pre-extracted when the pre-leaf is announced, which includes the buffer and the extracted space. Controller system to the scratchpad, buffering crying and inside: when the performance is continued at the first time after the first data, the pre-extraction timer accumulates the second data stored in the buffer, and the accumulated time of the sub-meter is reached. Or exceed the valid ΘΙ^Γ' and the second data stored in the timing is invalid. "Call, the sooner, the present invention further proposes a computer system and a sinking device. The second memory, the memory, the second data after the data. The chip group and the connection are coupled to the chip at the first place. Group. The crystal moon is fine / 5 memory. The bus buffers the buffer and uses the timer. The buffer stores the memory from the memory "=_ meter, and the control data is stored in the buffer for the duration. When the controller receives the bus 3 and the order, the second data is pre-fetched to be stored in the reading of the younger one. 201106164
VITO9-0O10I0O-TW 31323twf.doc/D 器累計第二資料存放在缓衝器内的存續 到或超過有效時間時，宣告緩= 纟發明之資料預先提取方法及 3 片組預先提取資料存續的安== 先純貧料有可能因為記憶體更新而發生錯誤^ 效，從而避免匯流排裝置讀取到錯誤資料。 7 /、失 舉貝施例，並配合所附圖式作詳細說明如下。 【實施方式】 盆右十對更新週期可以預測的資料設定一個可確保 提取資料二，晶片組中設置-個計時器以累計預先 ί的 而當預先提取資料的存續時間超過 間而有可能會被更新時，即齡此預先提取資料失 效，攸而避免匯流排裝置讀取到錯誤的資料。 番古=1疋依照本發明—實施例崎示之資料預先提取裝 ⑽^，圖2則是依照本發明一實施例所繪示之電腦系 牛㈣Ϊ圖。請同時參照圖1及圖2，本實施例之資料預 =取衣置1GG例如是配置在電腦系統的晶片組22〇 而轉系統200之處理器21〇中的快取記憶體212 ===㈣峨，細睛_流排裝置 /、中，所述的晶片組例如是北橋晶片、南橋晶片或是 201106164 VIT09-0010I00-TW 31323twf.doc/n 結合南北橋的晶片組；所述的匯流排例如是週邊元件互連 (Peripheral Component Interconnect，PCI)匯流排；所述的 匯流排裝置例如是直接記憶體存取（Direct Memory Access, DMA)引擎，本實施例不限定其範圍。 資料預先提取裝置100係在匯流排裝置240提出記憶 體存取請求時，由處理器210的快取記憶體212中，或是 由系統記憶體230中預先提取資料，以供匯流排裝置240 ^ 讀取。資料預先提取裝置1〇〇包括暫存器110、缓衝器12〇、 計時器130及控制器H0，其功能分述如下： <存為110係儲存用以判斷資料是否無效的有效時 間。具體而言，針對更新週期固定的資料（例如視訊資料 或音§fl資料），可歸納出一個資料的有效時間。意即，每 次裝置讀取此類資料之後的這一段有效時間内可保證電腦 系統200不會再對資料進行更新’因此可確保資料預先提 取裝置100所預先提取的資料是有效的。此有效時間，舉 例而言，可以由電腦系統200之基本輸入輸出系統（Basic _ input 〇卿ut system，BIOS )(未緣示）根據電腦系統2⑽ 之視訊/音訊驅動程式（video/audio driver)(未奢示）得 到其對資料的一相對固定的更新週期。 緩衝器120係用以儲存由資料預先提取裝置1〇〇預先 提取的資料。此資料例如是根據匯流排裝置24〇所發送的 έ己憶體存取請求，而由系統記憶體230或處理器21〇的快 取記憶體212中取得的資料。 計時器130係用以累計上述預先提取資料存放在缓衝 201106164 V1T09-0010I0Q-TW 31323twf.doc/n 器120内的存續時間。此計時器13〇例如是在 衝器12G的_即開始累計，而累計的存續_即可用ί 作為預先提取資料疋否有效的判斷依據。 控制器140係分別耦接至暫存器11〇、緩衝哭12〇 計時器13Q，並與匯流排裝置連接，而可接i匯流排 裝置240所發出的讀取指令，並預先提取系統記㈣23〇 或處理器21〇之快取記憶體212中的資料，以供匯流排農 置240讀取。 又 詳細地說，圖3是依照本發明—實施例所纟會示之資料 預先提取方法的流程圖。請同時參照圖丨、圖2及圖3，'本 實施例之資料預先提取方法適用於上述的資料預先提取裝 置100，其步驟如下： t 首先，由控制器140接收匯流排裝置24〇對於第一資 料的讀取指令（步驟S302)。其中’控制器M〇例如會根 據讀取指令中記錄的資料位址，到處理器21〇之快取記憶 體212或是系統記憶體230中找尋匯流排裝置24〇所請求 的第一資料’以回應給匯流排裝置24〇。 此外’為了增加匯流排裝置240讀取資料的速度，控 制器140還包括預先提取接續在上述第一資料之後的一筆 苐一資料以儲存於缓衝器120中，並在此同時啟動計時器 130開始累計此第二資料存放在缓衝器12〇内的存續時間 (步驟S304)。詳細地說，上述的第一資料例如是儲存在 記憶體的第一區域，而控制器丨4〇預先提取的第二資料則 是在記憶體中接續在此第一區域之後之第二區域中儲存的 201106164 VIT09-0010IOO-TW 31323twf.doc/n 資料。 值得注意的是，上述控制器140在提取資料時，例如 會同時檢視系統記憶體230及處理器21〇之快取記憶體 212中是否有所需的資料’若系統記憶體23〇及處理器2川 之快取記憶體212兩者之中都有所需的資料，則選擇提取 其中最新的資料，並儲存於缓衝器12〇，以確保所提取資 料的有效性。 'VITO9-0O10I0O-TW 31323twf.doc/D The accumulated second data stored in the buffer survives or exceeds the valid time, and the data is pre-extracted and the pre-extracted data of the three-chip group is pre-extracted. == The first lean material may have an error due to memory update, thus preventing the bus device from reading the wrong data. 7 /, Missing Bay example, and with the accompanying drawings as detailed below. [Embodiment] The data of the right ten pairs of the update period can be set to ensure that the data is extracted. The timer is set in the chipset to accumulate the pre-extraction, and when the pre-extraction data exceeds the duration, it may be When updating, the pre-extracted data of the age is invalid, and the busbar device is prevented from reading the wrong data. According to the invention, the data of the embodiment is pre-extracted (10), and FIG. 2 is a computer (four) diagram of the computer according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2 simultaneously, the data pre-setting device 1GG of the embodiment is, for example, a cache memory disposed in the processor group 21 of the computer system and transferred to the processor 21 of the system 200. (4) 峨, 细流_流流装置/, the chip group is, for example, a north bridge wafer, a south bridge wafer or a 201106164 VIT09-0010I00-TW 31323twf.doc/n combined with a north-south bridge chip set; the bus bar For example, a Peripheral Component Interconnect (PCI) bus bar; the bus bar device is, for example, a Direct Memory Access (DMA) engine, and the scope of the embodiment is not limited. The data pre-fetching device 100 pre-fetches data from the cache memory 212 of the processor 210 or the system memory 230 for the bus bar device 240 when the bus bar device 240 requests a memory access request. Read. The data pre-fetching device 1 includes a register 110, a buffer 12, a timer 130, and a controller H0, the functions of which are as follows: <Save as 110 stores a valid time for judging whether the data is invalid. Specifically, for the data with a fixed update period (such as video data or audio §fl data), the effective time of one data can be summarized. That is, the period of validity after each device reads such data ensures that the computer system 200 will no longer update the data' so that it is ensured that the data pre-fetched by the data pre-fetching device 100 is valid. The effective time, for example, can be based on the basic input/output system (Basic_input ut system, BIOS) of the computer system 200 (not shown) according to the video/audio driver of the computer system 2 (10). (not shown) get a relatively fixed update cycle for the material. The buffer 120 is for storing data previously extracted by the material pre-extracting device 1. This information is, for example, data acquired by the system memory 230 or the memory 21 of the processor 21 in accordance with the memory access request transmitted from the bus device 24A. The timer 130 is configured to accumulate the duration of the pre-extracted data stored in the buffer 201106164 V1T09-0010I0Q-TW 31323twf.doc/n 120. This timer 13 is, for example, started to accumulate in the buffer 12G, and the accumulated survival_ can be used as a basis for judging whether or not the data is valid in advance. The controller 140 is respectively coupled to the register 11〇, the buffering crying timer 13Q, and is connected to the busbar device, and can be connected to the read command issued by the busbar device 240, and pre-extract the system record (4) 23 The processor or processor 21 caches the data in the memory 212 for reading by the busbar 240. In more detail, Figure 3 is a flow diagram of a method of pre-fetching data in accordance with an embodiment of the present invention. Referring to FIG. 2, FIG. 2 and FIG. 3 simultaneously, the data pre-extraction method of the present embodiment is applied to the above-mentioned data pre-extracting apparatus 100, and the steps are as follows: t First, the controller 140 receives the busbar device 24 for the first A data read command (step S302). The controller M, for example, searches for the first data requested by the busbar device 24 in the cache memory 212 of the processor 21 or the system memory 230 according to the data address recorded in the read command. In response to the busbar device 24〇. In addition, in order to increase the speed at which the bus bar device 240 reads the data, the controller 140 further includes extracting a piece of data subsequent to the first data to be stored in the buffer 120, and simultaneously starting the timer 130. The accumulation of the second data stored in the buffer 12 is started (step S304). In detail, the first data is stored in the first area of the memory, for example, and the second data extracted by the controller 是4 is in the second area after the first area in the memory. Stored 201106164 VIT09-0010IOO-TW 31323twf.doc/n information. It should be noted that, when the data is extracted, for example, the controller 140 can simultaneously check whether the system memory 230 and the cache memory 212 of the processor 21 have the required data, if the system memory 23 and the processor are If there is a required data among the two cache memories 212, the latest data is selected and stored in the buffer 12 to ensure the validity of the extracted data. '
而在計時器130累計第二資料之存續時間的同時，控 制器140會將此存續時間與暫存器11〇中記錄的有效時^While the timer 130 accumulates the duration of the second data, the controller 140 compares the duration with the time recorded in the register 11〇^
相比較，據以判斷此存續時間是否達到或超過有效 驟 S306)。 W 其中，控制器140例如會依據匯流排裝置對於資料的 存取週期’而判斷第二資料的更新時間，並用以作為判斷 預先提取之第二㈣是否無效的有效時間。而當計時哭 ^ ^的存續時間達到或超過此有效時間時，即代表^ 在糸統記憶體23〇或處理器2丨。之快取記憶體212 =弟=貧料可能會被更新，因此由控制器刚預先提取 2 -讀就有可能是錯誤的。此時控織14 ^緩衝器12(3中的第二資料宣告無效（步㈣= 避免可能的讀取錯誤。 在本發明另一實施例中，計時器 式，計時器n〇饮媸靳六。。Η木用疋日守的方 gp B , ° W日存為110中記錄的有效時間而編程。 到該有效時間時，计時哭累計該存續時間達 了叫物益130會計數溢出，則發出—中斷 201106164 VJ1T09-001OIOO-T W 31323^^(10-控制訊號至控㈣140。當控繼⑽接彳_钟斷㈣ 信號時^即代表原先儲存在系統記賴23()或處理 之快取記憶體212中的第二資料可能會被更新。因此。在 驟S308,控制器140將儲存在缓衝器12〇中的第二 告無效。 —貝竹旦In comparison, it is determined whether the duration has reached or exceeded the effective step S306). For example, the controller 140 determines the update time of the second data according to the access period of the bus device for the data, and uses it as a valid time for judging whether the second (four) extracted in advance is invalid. When the duration of the time crying ^ ^ reaches or exceeds this effective time, it means that the memory is 23 or the processor 2丨. The cache memory 212 = brother = poor material may be updated, so the controller just pre-fetched 2 - read may be wrong. At this time, the second data declaration in the buffer 12 is invalid (step (4) = avoiding possible read errors. In another embodiment of the present invention, the timer type, the timer n 〇 six The eucalyptus is programmed with the daily gp B , ° W day storage as the effective time recorded in 110. When the effective time is reached, the time of the crying accumulates the duration of the call to reach the benefit 130 will overflow. Then issue - interrupt 201106164 VJ1T09-001OIOO-TW 31323 ^ ^ (10 - control signal to control (four) 140. When the control (10) is connected to the _ _ _ (four) signal ^ means that the original is stored in the system record 23 () or processing fast The second data in the memory 212 may be updated. Therefore, in step S308, the controller 140 invalidates the second ticket stored in the buffer 12A.
藉由上述方法，貧料預先提取裝置100即可在預先提 取資料的情況下，確保所提取資料的有效性。而在匯流排 裝240向晶片、组220提出下一個記憶體存取請求時，資料 預先提取裝置i〇〇m可直接以儲存在緩衝器m中的預先 提取資料作回應’藉以增加匯流職置讀取資料的速 度’以下則再舉一實施例詳細說明。 圖4是依照本發明-實施例所績示之資料預先提取方 法的流程圖。請同時參照圖卜圖2及圖4,本實施例之資 料預先提取方法同樣適用於上述的資料預先提取裝置 100，其步驟如下：By the above method, the poor material pre-extraction device 100 can ensure the validity of the extracted data in the case where the data is extracted in advance. When the bus bar 240 requests the next memory access request to the chip and the group 220, the data pre-fetching device i〇〇m can respond directly to the pre-extracted data stored in the buffer m to increase the confluence position. The speed at which data is read' is described in detail below with reference to an embodiment. Figure 4 is a flow diagram of a method of pre-fetching data in accordance with the present invention. Referring to FIG. 2 and FIG. 4 simultaneously, the data pre-extraction method of the present embodiment is also applicable to the above-mentioned data pre-extracting apparatus 100, and the steps are as follows:
首先，由彳工制器140接收匯流排聚置240對於第一資 料的讀取指令（步驟S402)。其中，控制器丨4〇例如會根 據讀取指令中記錄的資料位址，到處理器21〇之快取記憶 體212或是系統記憶體230中找尋匯流排裝置24〇所請^ 的第一資料，以儲存於缓衝器120 (步驟S4〇4)，除了提 取第一資料之外，控制器M0還包括預先提取接續在第— 貧料之後的一筆第二資料，以儲存於緩衝器12〇中（步驟 S406)，然後以缓衝器i20内的第一資料回應給匯流排裝 置 240 (步驟 S408)。 10 201106164 VIT09-0010I00-TW 31323twf.doc/n 其中，如同先前實施例所述，控制器14〇在將第二資 料存入緩衝器120後，即會啟動計時器13〇開始累計此第 ^資料存放在缓衝器120内的存續時間，據以判斷此第二 貧料是否仍然有效，並適.時將第二資料宣告無效，以避免 匯流排裝置讀取到錯誤的資料。 、值得注意的是，在本實施例中，控制器14〇在預先提 取並儲存第二資料之後，可再接收匯流排裝置240對於第 =身料的讀取齡（步驟S41〇)，而選擇以先前儲存在缓 禮i器120内的第二資料來回應。 然而，儲存在緩衝器120内的第二資料有可能會因為 〜存續時間超過有效時間而被控制器14〇宣告失效，因此 ^制器140在回舰輯裝置的請权前，必需先判 畸儲存於緩衝器m⑽第二資料是否有效（步驟$則。 =中’ W彳斷第二純減有效，即可以緩衝器内的 座了^料直接回應給匯流排裝置（步驟S414)。然而，若 ^斷第—詩無效’則需重糊處理器2iq之快取記憶體 宽2-ΐ是系統記憶體230中找尋匯流排裝置240所請求的 驟：t料，並用以更新緩衝$ 120内儲存的第二資料（步 2 ，而成夠以更新後的第二資料回應給匯流排裝置 240 (步驟 S418)。 ^藉由上述方法，資料預先提取裝置1(H)可在提取記情 2提取接續的資料，以便回應匯流排； 肩德择、。仏财取請求，而在以預先提取的資料回 應後績的記憶體存取請树，本制會先觸預先提取的 201106164 VJ.T09-0010IOO-TW 31323twf.doc/n 資料是否有效，從而提高了匯流排裝置讀取資料的準 確性。而當預先提取的資料過了有效時間日夺，仍可藉由再 次提^資料來作回應，而可保有提取資料的彈性。 、.’不上所述’本發明之資料預先提取方法及裝置係根據 匯流财置對於資料的存取來觸資料可能被更新的 期間’亚藉由程式化計時器，以在預先提取資料的存續時 間達到或超過其有效_時，將預先提取資料缓衝器中的 貧1宣告失效’目此可在贱提取龍以增加讀取速度的 同4 ’確保預先提取資料的有效性，而避免 取到錯誤資料。 「衣貝 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 t發明之精朴範#可作些狀更賴潤飾，故本 啦明之保護範圍當減附之申請專娜_界定者為準。 【圖式簡單說明】 塊圖 置方=是依照本發明一實施例所繪示之資料預先提取裝 圖2則是依照本發明-實施例所繪示之電腦系統的方 取方 法的=依照本發明一實施例所繪示之資料預先提 法的流程圖First, the read command of the bus arrangement 240 for the first data is received by the processor 140 (step S402). The controller 丨4〇, for example, searches for the busbar device 24 in the cache memory 212 or the system memory 230 of the processor 21 according to the data address recorded in the read command. The data is stored in the buffer 120 (step S4〇4). In addition to extracting the first data, the controller M0 further includes pre-extracting a second data subsequent to the first poor material for storage in the buffer 12 In the middle (step S406), the first data in the buffer i20 is then returned to the bus device 240 (step S408). 10 201106164 VIT09-0010I00-TW 31323twf.doc/n wherein, as described in the previous embodiment, after the second data is stored in the buffer 120, the controller 14 starts the timer 13 and starts accumulating the first data. The duration of the storage in the buffer 120 is determined to determine whether the second lean material is still valid, and the second data is invalidated when appropriate, to prevent the busbar device from reading the wrong data. It should be noted that, in this embodiment, after the second data is extracted and stored in advance, the controller 14 may receive the read age of the bus bar device 240 for the body material (step S41〇), and select The second data stored in the mitigation device 120 is responded to. However, the second data stored in the buffer 120 may be declared invalid by the controller 14 because the duration exceeds the effective time. Therefore, the controller 140 must first determine the distortion before returning the device to the ship. Whether the second data stored in the buffer m(10) is valid (step $: = 'W' breaks the second pure subtraction, that is, the block in the buffer can directly respond to the bus device (step S414). However, If the "breaking of the first poem is invalid", the memory of the memory 2iq is required to be wide 2. The memory memory 230 searches for the request of the bus bar device 240: t material, and is used to update the buffer within $120. The stored second data (step 2 is sufficient to respond to the bus bar device 240 with the updated second data (step S418). ^ By the above method, the data pre-extracting device 1 (H) can extract the note 2 Extract the continuation of the data in order to respond to the bus; the stipulations of the shoulders, the pledge of the money, and the memory access to the data with the pre-extracted data, please contact the pre-extracted 201106164 VJ.T09 -0010IOO-TW 31323twf.doc/n Is the data valid? Thereby, the accuracy of reading data by the busbar device is improved, and when the pre-extracted data has passed the effective time, the data can be retrieved by re-sending the data, and the flexibility of extracting the data can be retained. The method and device for pre-extracting the data of the present invention are based on the access period of the data exchange for accessing the data, and the program may be updated by the staging timer to achieve the duration of the pre-extracted data or When it exceeds its effective _, the pre-extraction of the lean 1 in the data buffer is invalidated. This allows the extraction of the dragon to increase the read speed of the same 4 ' to ensure the validity of the pre-extracted data, and avoid getting the wrong data. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person having ordinary knowledge in the technical field can do some refinement without departing from the invention of the invention. Therefore, the scope of protection of Benjamin is deducted from the application of the application. The definition of the figure is a block diagram = the data in advance according to an embodiment of the present invention. FIG 2 is fetched in accordance with the present invention - depicted flowchart of an embodiment of a computer system illustrating a method of taking party information in accordance with embodiments = depicted embodiment of the present invention is a method of previously mentioned
Lti依照本發明一實施例所繪示之資料預先提取方 201106164 V1T09-0010I00-TW 31323twf.doc/n 【主要元件符號說明】 100 :資料預先提取裝置 110 暫存器 120 缓衝器 130 計時器 140 控制器 200 電腦糸統 210 處理器 212 快取記憶 220 晶片組 230 系統記憶 240 :匯流排裝置 S302〜S308 :本發明之資料預先提取方法之各步驟 S402〜S418 :本發明之資料預先提取方法之各步驟Lti according to an embodiment of the present invention, the data pre-fetching party 201106164 V1T09-0010I00-TW 31323twf.doc/n [main component symbol description] 100: data pre-fetching device 110 register 120 buffer 130 timer 140 Controller 200 computer system 210 processor 212 cache memory 220 chipset 230 system memory 240: busbar device S302~S308: steps S402~S418 of the data pre-extraction method of the present invention: the data pre-extraction method of the present invention Each step
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