201104658 六、發明說明： 【發明所屬之技術領域】 特別是有關於一 電路與相關方法。 本發明有關於顯示控制電路之耗電 種極低耗電（ultra-low power )之顯示控制 【先前技術】 弟一圖顯示習知技藝之顯示器內邱 1ΠΛ .. 円的顯示電路方塊圖 100 ’包含電源電路11〇、縮放控制 工取1益丨2〇以及背光模紅 130’電源電路no經由交流電泝〗 、' η, 11Λ 原112供電轉換成適當· 114、116，而分別供電給背光模έ g 賴、'且130及縮放控制器120 之運作。顯示電路方塊圖1〇〇可 r , 了以應用於電腦監視器 (麵加〇、類比電視或者數位電視當中 世界潮、户Φ，产士 th從丄 名咸反的 介潮机甲，4人廠商皆致力於顯 ^ ^ „ .. — 不态於待機狀態下的耗電201104658 VI. Description of the invention: [Technical field to which the invention pertains] In particular, there is a circuit and related method. The invention relates to the display control of the power consumption of the display control circuit and the ultra-low power. [Prior Art] The figure shows the display circuit block diagram 100' of the display of the conventional technology. The power supply circuit 11〇, the zoom control device 1 丨 2〇, and the backlight mode red 130' power circuit no are converted to the appropriate · 114, 116 via the AC power trace, ' η, 11 Λ original 112 power supply, and respectively supplied to the backlight mode έ g 赖, 'and 130 and the operation of the zoom controller 120. The display circuit block diagram is shown in Figure 1. It can be used in computer monitors (face-twisting, analog TV or digital TV, world tide, household Φ, maternal th from the name of the salty anti-industry mech, 4 people Manufacturers are committed to display ^ ^ „ .. — not in the standby state of power consumption
.、孜1用父流/直流轉換（AC/DC conversion)之電源電路11〇進行省電。 耗n 切而要|展出—討以低成本實現的極低 耗％之顯不電路與相關方法。 【發明内容】 次侧出一種極低耗電顯示控制電路，包括具有 顯干控制^側之變壓器々接至變壓器之電容，穩壓篆 ‘工4及電壓比例單元；變壓器用以於一次側接 201104658 高壓直流電壓以轉換成 + 直流電麼；穩屋器_至=於二次側；電容用以穩定 直流槔壓輸出.ME - ^ '夺，用以接收直流電壓並產生 出’顯木控制器耦 穩塵輸出而運作；電屢比例單=二=接收直流 壓哭之-+也丨ra 平兀耦接至顯不控制器以及變 -欠：· if顯:：以接收參考提供-電壓比例於二 使仔顯不控制器可於省電模式藉由通用型輸入於出 腳位改變電壓比例。 用尘輸入輸出.孜1 Use the power circuit 11〇 of the parent/DC conversion to save power. Consumption is cut and it is necessary to showcase the extremely low-cost circuit and related methods that are realized at low cost. [Summary of the Invention] The secondary side has a very low power consumption display control circuit, including a capacitor having a display of the dry control side connected to the transformer, a voltage regulator, a power 4 and a voltage proportional unit; the transformer is used for one side connection 201104658 High-voltage DC voltage to convert to + DC; stable house _ to = secondary side; capacitor used to stabilize DC 输出 output .ME - ^ ', used to receive DC voltage and produce 'display controller Coupling the dust output and operating; electric repeat ratio single = two = receiving DC pressure crying - + also 丨 ra flat 兀 coupled to the display controller and variable - owed: · if display:: receive reference to provide - voltage ratio In the second power saving mode, the voltage ratio can be changed in the power saving mode by the universal type input to the output pin. Dust input and output
示控種極低耗電顯示控制方法，包括:顯 交—之二次側之輪出麵位準；以及將 : 器穩彻產蝴輸出供顯網二 ☆為了使釣局能更進一步瞭解本發明特徵及技術内 月參閱以下有關本發明之詳細說明與附圖，然而所附 圖式僅提供參考與朗，並_來對本發明加以限制。 【實施方式】 第二圖顯示根據本發明具體實施例之極低耗電顯示控 制電路300’交流電源3〇2供應交流電壓給整流器31〇,例 如80至220伏交流電壓；而整流器31〇整流輸出直流電壓 、’偏壓电路320與變壓器（transf〇rmer) 330，例如是i2〇 至375伏直流電壓，整流器31〇例如是全橋式整流器；經 過偏壓電路320偏壓為直流電壓訊號VDDp供電給電源轉 換控制器340運作，直流電壓訊號VDDP例如是2〇伏直 201104658 流電壓，電源轉換控制器340為類比電路晶片，通常封裝 為八個腳位，由於成本考量有腳位數量之限制。變壓器 利用線圈感應將其-次侧之高壓.直流電壓轉換成其他適當 的直流電壓於二次側輸出，供其他電路運作，例如輸出直 流電壓訊號VCC14V與VCC5V，分別提供14伏與=伏直 流電屢’ 14伏直流電遷可供應背光模組之運作，例如冷产 極燈管或者發光二極體之背光餘之運作。直流電壓^ VCC5V經過穩壓器35〇，例如低壓差線性穩壓器（1〇= dn>P-_ regulator，簡稱LD〇)，穩壓輪出直流電壓訊號 VDD3V3而供電給縮放控制器遍之運作。縮放控制器规 根據變壓11330輸出之錢電壓職VCC5V上的電壓狀 況控制電源轉換控制器34〇之運作，舉例而言，將直流電 屢訊號VCC5V經過電阻R5、R6之感測職ν(χ5ν細e 送進縮放控制器360之逐步逼近暫存器類比數位轉換器 (suCCessive approximati〇nADc，簡稱 saradc)偵測直 流電壓訊號VCC5V上的電壓狀況，熟知此技藝人士可以 了解逐步逼近暫存器類比數位轉換器是低成本可以實現的 低速類比數位轉換器，或者，將感測訊號VCC5VS_送 進縮放控制器360之-比較器（未示出）與—參考電壓， 例如4伏，制直流電壓訊號VCC5V上的電壓狀況；然 後，縮放控制器360可利用通用型輸入輸出（柳㈣ 啊⑽⑽，簡稱GPI0)腳位經過_合元件（〇pt〇·咖 或稱Ph0t0C0upler) 370划電源轉換控制器之補償腳 位C〇MP’回授控制電源轉換㈣器_之開啟運作時 機，達到極低耗電之㈣。應注意到，熟知此技藝人士可 201104658 以了解電源轉換控制器340為類比電路晶片， ，其中補償腳位C〇MP於電源轉換控制器34二 4扶供有電流源342，例如為2〇〇微安培（Ma ) 偏壓電路划包括電阻如鲁奶二極軸^ =體Ql、Q2、Q3。偏壓電路32〇利用電阻幻i、Ri2、 ^將高壓直流電壓偏壓為直流電壓訊號 仏电給電源轉換控制器340運作。 φ電源轉換控制器340利用電容C1所儲存的電荷，於 鲁 Qi _而停止供電時，可以短暫供應電源轉換控 °。 之運作，但是，熟知此技藝人士可以了解電容d 亦關係到電源啟動時，真正開始供應正常直流電麗運作所 需要的時間’所以電容口也不能太大，例如為22微法拉 U士F)。而縮放控制器36〇則可以利用電容C2，於切斷電 源铃’可以短暫供應縮放控制器36〇之運作，典型地電容 C2相田大’例如為·Q微法拉（㈣，應注意到電容Q 可提供的儲存電力遠較電容C1大。 籲 圖所顯示之極低耗電顯示控制電路·，在關閉 系、、先电源後’利用電容C2短暫供電於縮放控制器360之 ’ Ik過壓杰350穩廢輸出直流電壓訊號VDD3V3而 仏包，’’口鈿放控制盗360之運作，只要直流電壓訊號VCC5V 、’二過知壓益350穩壓輸出之直流電壓訊號VDD3V3高於縮 放才工制=360之工作電壓之狀況下，皆可運作縮放控制器 36〇 ’穩壓$ 350之耗電量極低，並使得直流電壓訊號 VCC5V與直流電壓訊號VDD3 v3間之電壓降叩極 小。假设縮放控制器36〇之工作電塵為3 3伏，經由電容 201104658 C2之逐漸放電，只要直流電壓訊號VCC5V超過（3.3伏 +LD〇Drop)，皆可使縮放控制器360運作。 在關閉系統電源後’縮放控制器360利用GPIO.腳位 送出訊號AC一OFF將縮放控制器360之電壓狀態，經由電 阻R4以及光耦合元件370反應給電源轉換控制器34〇端 以沒取電流，電源轉換控制器340則利用補償腳位c〇MP 使電流源342經由電阻R13、二極體D21、D22與電晶體 Q3供應此電流，舉例而言，光耦合元件37〇之電流轉換比 例（current transfer mti〇n，簡稱 CTR)為 u，則光耦合 元件370兩側所汲取之電流為1:1，訊號AC—〇FF之主張 (assertion )期間相關於直流電壓訊號vcc5V之位準。當 電源轉換控制器340於補償腳位c〇MP感測到縮放控制器 360之電壓低於一預定位準時，短暫驅動訊號以打開 電晶體Q4，短暫啟動變壓器33〇之一次側汲取外部電源， 以對電容C1充電以及對變壓器33〇之二次側之大電容 充電以供下個循環期間縮放控制器360之運作。第二圖 ☆中箭頭方向標示㈣個電路分射社要電紐向，使得 熟知此技藝人士可以更了解本實施例之運作。 电你锊換徑制器340，當主張訊號AC 〇FF時 ，如為高位準’光耦合元件37G產生叙合電流，經由節 、D22與光轉合元件370沒取所需之氣 二二:电晶體Q3之基極電愿下降，導通電晶體叫 ;二1、D22，使得補償腳位C0MP上電壓下降1 才1電日日體Q2，使得電晶體〇 ； 體Q1，·電晶體03罝古Γ 下降而關閉電j 體Q3具有電流放大之作用，可以加速電流0 201104658 342之放電速度，如果電源轉換控制器34〇内之電流源342 之電流能力低，則可以省掉電晶體Q3，直接靠二極體D22 進行放電。另一方面，當解主張訊號AC—〇FF時.，例如為 低位準，無感應電流產生，導通電晶體Q1而對電容C1充 電，然後補償腳位COMP上電壓逐漸上升，導通電晶體 Q2 ’使彳牙電晶體Q1之基極接地而關閉電晶體QJ，使得電 源轉換控制器340使用電容C1所儲存之電力，使得電容 C1放電，·因此’藉由訊號AC—0FF之主張與否控制電源轉The control method has a very low power consumption display control method, including: explicit cross-level of the secondary side of the wheel; and: the device is stable and outputted for the display network II ☆ in order to enable the fishing bureau to further understand this DETAILED DESCRIPTION OF THE INVENTION The present invention is described with reference to the following detailed description of the invention and the accompanying drawings. [Embodiment] The second figure shows an extremely low power consumption display control circuit 300' according to an embodiment of the present invention. The AC power source 3〇2 supplies an AC voltage to the rectifier 31〇, for example, an AC voltage of 80 to 220 volts; and the rectifier 31 is rectified. Output DC voltage, 'bias circuit 320 and transformer (transf) 330, for example, i2 〇 to 375 VDC, rectifier 31 〇 is, for example, a full bridge rectifier; biased by bias circuit 320 to DC voltage signal The VDDp power supply is operated by the power conversion controller 340. The DC voltage signal VDDP is, for example, 2 〇 直 201,102,658, and the power conversion controller 340 is an analog circuit chip, and is usually packaged in eight pins. The cost is determined by the number of pins. limit. The transformer uses coil induction to convert its high-voltage DC voltage to the other secondary DC output for other circuits, such as output DC voltage signals VCC14V and VCC5V, respectively providing 14 volts and = volts DC. '14 VDC dc can supply the operation of the backlight module, such as the operation of the cold-emitting pole lamp or the backlight of the light-emitting diode. DC voltage ^ VCC5V through the regulator 35 〇, such as low dropout linear regulator (1 〇 = dn > P-_ regulator, referred to as LD 〇), the voltage regulator wheel DC voltage signal VDD3V3 and power supply to the scaling controller Operation. The scaling controller regulates the operation of the power conversion controller 34 according to the voltage condition on the voltage voltage VCC5V outputted by the voltage change 11330. For example, the DC power signal VCC5V passes through the resistance R5, R6 sensed ν (χ5ν细e The progressive controller analog scale analog converter (suCCessive approximati〇nADc, referred to as saradc) is sent to the zoom controller 360 to detect the voltage condition on the DC voltage signal VCC5V. Those skilled in the art can understand the approximation of the register analog digital digits. The converter is a low-speed analog digital converter that can be implemented at a low cost, or a sensing signal VCC5VS_ is fed into a scaling controller 360 - a comparator (not shown) and a reference voltage, for example, 4 volts, a DC voltage signal The voltage condition on the VCC5V; then, the zoom controller 360 can utilize the general-purpose input and output (Liu (4) ah (10) (10), abbreviated as GPI0). The pin is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Compensation pin C〇MP' feedback control power conversion (four) device _ open operation timing, to achieve very low power consumption (four). It should be noted that familiar with this artist 201104658 to understand that the power conversion controller 340 is an analog circuit chip, wherein the compensation pin C〇MP is supplied to the power conversion controller 34 and the current source 342, for example, 2 〇〇 micro amp (Ma) bias voltage The road plan includes resistors such as Lu milk diodes ^ = body Ql, Q2, Q3. The bias circuit 32〇 uses the resistors illusion i, Ri2, ^ to bias the high voltage DC voltage into a DC voltage signal to the power conversion controller 340 operation. The φ power conversion controller 340 utilizes the charge stored by the capacitor C1 to supply the power conversion control for a short time when the power supply is stopped. However, those skilled in the art can understand that the capacitance d is also related to When the power is turned on, it really starts to supply the time required for normal DC operation. Therefore, the capacitance port should not be too large, for example, 22 microfarads. The zoom controller 36 can use the capacitor C2 to cut off the power supply bell' to temporarily supply the operation of the zoom controller 36. Typically, the capacitor C2 is large. For example, Q microfarad ((4), should pay attention to the capacitor Q The stored power can be provided much larger than the capacitor C1. The extremely low power consumption display control circuit shown in the figure is shown, after the power is turned off, the power supply is temporarily applied to the zoom controller 360 by the capacitor C2. 350 stable output DC voltage signal VDD3V3 and 仏 package, '' 钿 控制 控制 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 360 Under the condition of working voltage of =360, the zoom controller 36〇's power consumption of $350 is extremely low, and the voltage drop between the DC voltage signal VCC5V and the DC voltage signal VDD3 v3 is extremely small. The operating voltage of the controller 36 is 33 volts, and the gradual discharge through the capacitor 201104658 C2 can make the zoom controller 360 operate as long as the DC voltage signal VCC5V exceeds (3.3 volts + LD 〇 Drop). After the power supply, the zoom controller 360 uses the GPIO. The pin sends the signal AC-OFF to zoom the voltage state of the controller 360, and reacts to the power conversion controller 34 via the resistor R4 and the optical coupling element 370 to take no current. The conversion controller 340 uses the compensation pin c〇MP to supply the current source 342 to the current via the resistor R13, the diodes D21, D22 and the transistor Q3. For example, the current coupling ratio of the optical coupling element 37 (current transfer) Mti〇n (CTR) is u, the current drawn by the two sides of the optical coupling element 370 is 1:1, and the assertion of the signal AC-〇FF is related to the level of the DC voltage signal vcc5V. When the compensation pin c〇MP senses that the voltage of the scaling controller 360 is lower than a predetermined level, the controller 340 briefly drives the signal to turn on the transistor Q4, and briefly starts the transformer 33, and the external side draws the external power source to the capacitor. C1 charges and charges the large capacitor on the secondary side of the transformer 33〇 for the operation of the zoom controller 360 during the next cycle. The second figure ☆ the direction of the arrow indicates (four) the circuit to the agency Therefore, those skilled in the art can better understand the operation of the embodiment. The electric switch 340, when the signal AC 〇FF is asserted, if the high-level optical coupling element 37G generates a rectified current, via the section, D22 and the light-converting element 370 do not take the required gas 22: the base of the transistor Q3 is expected to drop, and the conductive crystal is called; 2, D22, so that the voltage on the compensation pin C0MP drops by 1 Body Q2, making the transistor 〇; body Q1, · transistor 03罝古Γ falling and turning off the power j body Q3 has the function of current amplification, can accelerate the discharge speed of current 0 201104658 342, if the power conversion controller 34 When the current capability of the current source 342 is low, the transistor Q3 can be omitted and discharged directly by the diode D22. On the other hand, when the signal AC_〇FF is solved, for example, a low level, no induced current is generated, the transistor Q1 is energized to charge the capacitor C1, and then the voltage on the compensing pin COMP gradually rises, and the conducting transistor Q2' The base of the dentition transistor Q1 is grounded to turn off the transistor QJ, so that the power conversion controller 340 uses the power stored by the capacitor C1 to discharge the capacitor C1. Therefore, the power supply is controlled by the signal AC _FF. turn
換控制器340運作與否，以控制電容C1 &電、放電循環 運作。 & 第二圖顯示關於第二圖之極低耗電顯示控制電路％〇 ^主要波㈣，包括訊號AC—卿、錢峨VDDp、訊 唬DRV、電壓訊號VCC5V、感測訊號vcc5Vs咖〇之間 的波形關侧。配合第二圖之極低耗鶴示控制電路3〇〇 進仃說明’於此實施例中’訊號AC—〇FF拉高之後，透過 °體D21 D22與光轉合元件37〇快速地強迫電源轉換 控制器340内之電流源342放電拉低電位並關閉電晶體 Q1強迫切斷外部電源對電源轉換控制器之供電，且 電堡訊號VDDP被快相拉低，持續轉在q伏―段相奋 =時間，達到省電的目的。訊號Ac—_拉低之後； ，電晶體φ，對電容C1充電，使得電壓訊號.Dp快速 電顧’例如2Q伏，補償腳位⑺細 上升到預定位準’電源轉換控制器340短暫地主張 5|1遽響’例如由電源轉換控制請内之脈波寬度調變 P se width modulat職’簡稱pw⑷控制琴短暫地產生 201104658 高低位準寬度調變之訊號DRV’或者由脈波頻率調變 (pulse frequency modulation，簡稱 PFM )控制器產生頻率 不同之訊號DRV，短暫地導通電晶體Q4，使^變麼器33〇 之一次側短暫導通對電容C1充電以及對二次側的大電容 C2充電’例如將電壓訊號VCC：5V快速地拉升到5伏，其 可藉由與一比較器與一參考電壓比較達成，或者例如對二 次側的大電容C2充電一預定期間；只要在電壓訊號 VCC5V放電到預定電壓之前，縮放控制器36〇皆可正常運 作監控感測訊號VCC5Vsense之變化，如此持續循環運 作，舉例而言，只要確保整個過程當中電壓訊號Vcc5v 皆大於（3.3伏+電壓降LDODrop)，即可正常運作。感測 訊號VCC5Vsense則顯示對應電壓訊號vccw的充放電 变:化。應注意到，電壓訊號VDDp持續維持在〇伏一段相 當長的時間，使得訊號DRV之驅動期間相隔很遠，可以完 =隔絕外部電源之消耗，達到極低耗電之目的，經過電= 杈擬’總電力消耗約可達15〇亳瓦（mW)以下，而實際 品要支出的額外成本甚低，兼顧成本與效能兩者之考量。 本實施例中其他辅助元件之運作，例如熔絲F卜負溫係數 電阻NTC、電阻R2、電容C4等等，可以為熟知此技藝人 士所了解便不再贅述。 —第四圖顯不根據本發明之另一具體實施例之極低耗電 控制電路400 ’相較於第二圖之實施例之差異在於偏 [电路420 ’利用電ji且⑽提供偏壓控制，並省略電晶體 Q3 ’而最右端則顯示來自個人電腦的$伏訊號可以 透過一極體D6 @接於電壓訊號VCC5V，對電容C2充電； 201104658 而％放控制器360也可被廣泛整合於顯示控制器（diSpiay contiOller) ’應用於類比電視與數位電視，並不跳脫本發明 之範疇。 第五圖顯示根據本發明之另一具體實施例之極低耗電 顯示控制電路500,其主要係源自第二圖實施例之概念。 ' 類似的訊財制前面訊號之標號，有助於了解本實施例 之運作。主要差異在於電源轉換控制器54〇整合了第二圖 中，：电路320之類似元件，而顯示控制器直接偵側 • 電壓錢VDD3V3 ’節省逐步逼近暫存器類比數位轉換器 或者比較益之腳位；如前面實施例所揭示，由顯示控制器 56(|侦側屯邀5凡號VDD3V3之變化，舉例而言，確保侦側 電壓訊號WD3V3高於3.3伏。舉例而言，在電壓訊號 VDD3V3兩於3.3伏前，可由顯示控制器56()利用Gpi〇 腳位主張訊號AC_〇FF，經由光搞合元件，、補償聊位 C〇MP令電源轉換控制器540停止汲取外部電源；在電壓 汛號VDD；3V3快落到3.3伏前，由顯示控制器蝴解主張 春 Λ號AC—OFF ’电源轉換控制器54〇藉由打開内部開關（未 示出）經由高麗電源腳位HV由節點B短暫地汲取外部電 源、，使得電源轉換控制器54〇内部的受控電流源542，: &電壓訊號vDDp’對電容C1充電，短暫地驅動訊號 DRV ’啟動n’ 53G之—次側，使得變㈣別對電 ci充電以及對二次側之大電容C2充電達—敎電磨或 充電預&綱。電轉換蝴胃糾間地切斷外 迅源，可以大幅降低乾電。箭頭方向標示出幾個電路分 中的主要電流流向，使得熟知此技藝人士可以更了解本實 11 201104658 施例之運作。 根據以上諸多實施例之揭示，熟知此技藝人士可以做 出許多可能變化，仍不跳脫本發明之範疇。舉例而言，顯 示控制态560利用GPIO腳位控制訊號ac一OFF，經由電 阻R4、光耦合元件570，回授控制補償腳位c〇Mp，而控 制電源轉換控制器540是否汲取外部電源，可以有其他變 化之可能，舉例而言，可以修改光耦合元件57〇附近之電 路，使得訊谠AC—OFF之高低位準相對於電源轉換控制器 540之運作相反；或者，搭配辅助電路使得Gpi〇腳位間接 控制光耦合元件570汲取電流之運作；或者，以上諸多實 施例係由GHO腳位輸出控制訊號AC—〇FF之位準，藉由 修改光耦合元件570附近之電路，可使得Gpi〇腳位為輪 入方式運作’如第六圖所示，光耦合元件57〇經由電阻R72 耦接於顯示控制器560之GPIO腳位’經由電晶體Q8 是否導通放電，當控制訊號CTRL被主張，導通電^體 Q8 ’於訊號COMP引發電源轉換控制$ 54()類似前述^施 例之運作。 、 第七圖顯示根據本發明之具體實施例之極低耗電顯示 控制方法之流程圖。於步，驟702，感測變壓器二次側之直 流電壓位準’舉例而言，可以感測第二圖中職vcc5v 之變化，或者直接感測訊號VDD3V3之變化，舉例而士， 確保訊號VDD3V3皆高於3.3伏；於步驟7〇4，顯示控制 器藉由GPIO雜導通光耗合元件，控制電源轉換控制器 之補償腳位，而關閉電源轉換控制器之運作，舉例而言了 如第五圖所示’顯示控制器56〇可藉由Gpi〇腳位主‘訊 12 201104658 號AC—OFF增加光耦合元件57〇之耦合電流之大小，而關 閉電源轉換控制器540之運作，或者’如第六圖所示，光 耦合元件570耦接於顯示控制器56〇之Gpi〇腳位，藉由 包曰日體Q8形成放電路徑，而關閉電源轉換控制器54〇之 運作；於步驟706，當直流電壓位準下降到達一預定位準 - 時，經由GPI0腳位降低光耦合元件之耦合電流之大小， - ㈣電_換㈣11之補償職’而啟動f源轉換控制器 之運作，於步驟708，短暫導通變壓器之一次側，對第一 • 電容與第二電容短暫充電，舉例而言，如第五圖所示，藉 由脈波寬度調變或者脈波頻率調變控制電晶體Q4之閘 極，使得變壓器530對第一電容C1與二次側之第二電容 C2充電。 第八圖顯示根據本發明之-具體實施例之極低耗電電 源轉換控制器_，具有HV、VDDp、卿、cs、c〇Mp 及gnd等腳位’當應用到第五圖之實施例運作，第八圖 各腳位外部電路之運作如前述實施例所述。極低耗電電源 • 轉換，制器800包含比較器_、820、遲滞比較器請、 振盪器840、電流源δ42、電壓調節器85〇、正反哭_、 . 及閘_、872、緩衝器则、控制電路890、電阻° R80、 R82、背鈉二極體〇8〇。 第九圖顯示第八圖中極低耗電電源轉換控制器綱運 作之主要峨波形圖，v ( VDDP)、v (c〇 I (VDDp)、v (DRV)、5V 訊萝 ；、 壓訊號、COMP腳位上之電壓訊號、敗腳1^腳^電 p腳位之電流大小傭腳位之 13 201104658 號电源轉換控制器_剛啟動時，hv腳位經由電流源 842對VDDp腳位外之雷交r去-山、士& 井言至W各（未不出）充電，當電位逐漸 = ⑽較為830之正端輸入電壓高於第-遲滞參考 ^DH ’翁咖㈣之輸纽準為高，使得及間 之輸出為高’致能電壓調節器85〇輸出工作電愿於訊 唬=52供電源轉換控制器_内部之運作；而且，遲滯比 較器㈣之輪出高鮮經由糾892與反姆綱，關閉 電流源8犯，終止HV腳位從外部汲取電流，此或間卿 與反相器894控制路徑保證只要遲滞比較器83〇之輸出高 位準會關閉電流源842阻絕外部之耗電。㈣器84〇產生 :方波訊號輸出給SR正反器_之s輸入端，而sr正反 益_之11輸入端-開始為低位準，Q輸出端轉為高位準， 當勝腳位上被拉高位準，外部連接的電晶體（未示出） 會被導通，電流感測（CS)腳位也會因此跟著被拉高位準， =過=較器81〇’SR正反器860《r輸入端會轉變為高位 準’畜SR正反器860下一次接受觸發時，队正反器綱 之S輸入端料輸人端分別為低位準與高位準，觸發後， Q輸出端轉為低位準，也就是說，此電路之運作，/輸入 端與R輸入端之輸入位準於觸發時剛好都反相，以產生脈 波寬度調變訊餘DRV錄上。舉例而言，方波訊號為 細z之方波訊號，降低極低耗電電源轉換控制器_於 待機模式下的功耗，透過及閘872與緩·⑽將方波訊 號於DRV腳位上輸出。接著，VDDp腳位外之電容（未示 出）將所儲存的電力缓慢釋出，直到遲滞比較器㈣之正 端輸入電壓到達第二遲滞參考電壓VDDL，使得遲滞比較 201104658 ’使得及靜G之 ，閘872之輸出為低’腑腳位之輸出為低，關閉連接於 、上的外部電晶體（未示出）而關閉外部變 、 如第九圖所示，1 _訊號-開始：取充出電) 仏1咖职’於V ( VDDP )從電壓VDDH到電壓VDDL， I (HV)訊號（從外部電源）消耗電流驟降為仿v 〇ff。^ iVDDp)對應釋放出來的電流為加_P與I〇P，電流Iop 供應錢轉換控制器綱驅動DRV腳位上的方波訊號。 接著’外部變愿器之一次側導通過後，二次側的顯示 控制器（未示α出）方獲得電力而可以運作，可以控制V COMP)訊號。#由前述實施例揭露的cGMp腳位之控 :匕經由控制C0MP腳位上的補償訊號，可； 寬度調ί訊號的時間間隔拉長、產生的真正時間長度也縮 短，但疋仍讓電源轉換控制器_完全受監控的方式下運 作，不致於讓整個系統失控無法嗔醒。 f V(C〇MP)訊號之電錄低，強迫_振盪器840 之運作，或者’ _於V⑹)織之電位高低而調 變振盛益840之輸出頻率之高低，舉例而言，v (c〇Mp) 訊號之電位高則輪出頻率變高，v(c〇Mp)訊號之電位低 則輸出頻㈣低，或反向運作，因此V (〇)MP)訊號之 電位^可以影響電源轉換控制器800之耗電量；而且控 制比Uo將正端電麼與回授參考電壓憾^匕較後，低 位準輸出於回授控制訊號822，使得及閘請之輸出為低 位準讀电壓5周即器850之運作，關閉電源轉換控制器 8(30之内{電力供應,使得電源轉換控制器勘進入極低 201104658 耗電模式’電流I (VDDp)瞬間降低至i〇ff，較佳地電流 Ioff小於電流〇·1*ι〇ρ，或者更低，V (VDDP)電位的下降 速度變的十分緩慢，也就是y (VDDP)電位下降斜率變 小，而且藉由控制V (COMP)訊號可以大幅拉長下次開 始對外部電容充電的時間，降低整個系統之耗電；應注意 到，拉低V (COMP)訊號可以使得低位準輸出於回授控 制訊號822經由反相器896與或閘892強迫關閉電流源 842，終止HV腳位從外部汲取電流，因為此時遲滯比較器 830之輸出正處於高位準，已經關閉電流源842之運作。 也就是說，簡單的控制電路890包含或閘892以及反相器 894、896可以適時控制電流源842啟動與關閉的時機。 再回到第八圖中，當停止拉低V (COMP)訊號之動 作，也就疋當控制COMP腳位上的電壓高過回授參考電壓 I〇ff後’回授控制訊號822位準為高，電流I(VDDp)恢 復為~I〇P，外部大電容（未示出）再次恢復供應電源轉換 控制器麵之運作電力，電源轉換控制器800正常運作到 V(VDDP)電壓為VDDL，此時，遲滯比較器㈣之正端 ^入電動彳達第二遲滞參考電壓VDDL，才使得遲滞比較 益830之輸出位準由高轉低，使得及間87〇之輸出為低， 及閘872之輸出為低，DRV腳位之輸出轉為低位準。The controller 340 operates or not to control the operation of the capacitor C1 & electric and discharge cycles. & The second figure shows the extremely low power consumption display control circuit for the second figure. The main wave (4), including the signal AC-Qing, Qian 峨 VDDp, the signal DRV, the voltage signal VCC5V, the sensing signal vcc5Vs curry The waveform between the sides is off. With the extremely low-powered control circuit of the second figure, the description shows that, in this embodiment, after the signal AC-〇FF is pulled high, the power is quickly forced through the body D21 D22 and the light-converting element 37〇. The current source 342 in the conversion controller 340 discharges the low potential and turns off the transistor Q1 to force the external power supply to cut off the power supply to the power conversion controller, and the MWP signal is pulled low in the fast phase, and continues to rotate in the q volt phase. Time to achieve the purpose of saving electricity. After the signal Ac__ is pulled low, the transistor φ charges the capacitor C1, so that the voltage signal .Dp is fast, such as 2Q volts, and the compensation pin (7) is finely raised to a predetermined level. The power conversion controller 340 briefly asserts 5|1遽', for example, by the power conversion control, please adjust the pulse width modulation P se width modulat job' short for pw (4) control the piano to temporarily generate 201104658 high and low level width modulation signal DRV' or by pulse frequency modulation The pulse frequency modulation (PFM) controller generates a signal DRV with a different frequency, and briefly conducts the crystal Q4, so that the primary side of the transistor 33 is briefly turned on to charge the capacitor C1 and charge the large capacitor C2 on the secondary side. 'For example, the voltage signal VCC: 5V is quickly pulled up to 5 volts, which can be achieved by comparison with a comparator and a reference voltage, or for example, charging the secondary side of the large capacitor C2 for a predetermined period; as long as the voltage signal Before the VCC5V is discharged to the predetermined voltage, the zoom controller 36 can normally operate to monitor the change of the sensing signal VCC5Vsense, so that the cycle continues to operate, for example, as long as the entire process is ensured. When the voltage signal Vcc5v is greater than (3.3 volts + voltage drop LDODrop), it can operate normally. The sensing signal VCC5Vsense displays the charge and discharge of the corresponding voltage signal vccw. It should be noted that the voltage signal VDDp is continuously maintained at the stagnation for a relatively long period of time, so that the driving period of the signal DRV is far apart, and the end of the power supply can be isolated to achieve the extremely low power consumption, after the power = virtual 'The total power consumption is about 15 watts (mW) or less, and the extra cost of actual products is very low, taking into account both cost and performance considerations. The operation of other auxiliary components in this embodiment, such as fuse F, negative temperature coefficient resistance NTC, resistance R2, capacitance C4, etc., may be omitted from the knowledge of those skilled in the art. - The fourth diagram shows that the very low power consumption control circuit 400' according to another embodiment of the present invention differs from the embodiment of the second figure in that the bias [control circuit 420' utilizes the electric ji and (10) provides bias control. And omitting the transistor Q3 ' and the right end shows that the $ volt signal from the personal computer can be charged to the capacitor C2 through the polar body D6 @ connected to the voltage signal VCC5V; 201104658 and the % release controller 360 can also be widely integrated The display controller (diSpiay contiOller) 'applies to analog televisions and digital televisions without departing from the scope of the invention. The fifth figure shows a very low power consumption display control circuit 500 in accordance with another embodiment of the present invention, which is primarily derived from the concepts of the second embodiment. The labeling of the preceding signal of the similar financial system helps to understand the operation of this embodiment. The main difference is that the power conversion controller 54 〇 integrates the second figure, the similar components of the circuit 320, and the display controller directly detects the side of the voltage VDD3V3 'saving step by step closer to the register analog digital converter or comparing the benefits of the foot Bit; as disclosed in the previous embodiment, by the display controller 56 (|detection side change 5 VDD3V3 change, for example, to ensure that the detection side voltage signal WD3V3 is higher than 3.3 volts. For example, at the voltage signal VDD3V3 Before 3.3 volts, the display controller 56() can use the Gpi foot position claim signal AC_〇FF to engage the component via the light, and the compensation chat bit C〇MP causes the power conversion controller 540 to stop capturing the external power source; Voltage nickname VDD; 3V3 falls to 3.3 volts before, by the display controller, it is claimed that the spring AC AC-OFF 'power conversion controller 54 〇 by opening the internal switch (not shown) via the Korean power pin HV The node B briefly draws the external power source, so that the power conversion controller 54 〇 internal controlled current source 542,: & voltage signal vDDp' charges the capacitor C1, and briefly drives the signal DRV 'starts n' 53G - the secondary side Make the change (4) do not charge the electric ci and charge the large capacitance C2 on the secondary side to - 敎 electric grinder or charge pre-amp; and the electric conversion butterfly cuts off the external source, which can greatly reduce the dry electricity. The direction indicates the main current flow in several circuit segments, so that those skilled in the art can better understand the operation of the embodiment of the present invention. According to the disclosure of the above embodiments, those skilled in the art can make many possible changes, still For example, the display control state 560 uses the GPIO pin control signal ac_OFF to feedback the control compensation pin c〇Mp via the resistor R4 and the optical coupling component 570, and controls the power conversion control. Whether the device 540 captures the external power source may have other changes. For example, the circuit near the optical coupling element 57〇 may be modified such that the level of the AC-OFF signal is opposite to that of the power conversion controller 540; Alternatively, the auxiliary circuit allows the Gpi pin to indirectly control the operation of the light coupling element 570 to draw current; or, the above embodiments are controlled by the GHO pin output. The position of the signal AC-〇FF, by modifying the circuit in the vicinity of the optical coupling element 570, enables the Gpi pin to operate in a wheel-in mode. As shown in the sixth figure, the optical coupling element 57 is coupled via the resistor R72. The GPIO pin of the display controller 560 is turned on or off via the transistor Q8. When the control signal CTRL is asserted, the power-on body Q8' causes the power-conversion control $54() to be similar to the operation of the foregoing embodiment. The seventh figure shows a flow chart of a very low power consumption display control method according to a specific embodiment of the present invention. In step 702, sensing the DC voltage level of the secondary side of the transformer, for example, the second can be sensed. In the figure, the change of vcc5v, or the change of the direct sense signal VDD3V3, for example, ensures that the signal VDD3V3 is higher than 3.3 volts; in step 7〇4, the display controller controls the power supply by the GPIO hybrid light-conducting component. Converting the compensation pin of the controller and turning off the operation of the power conversion controller. For example, as shown in the fifth figure, the display controller 56 can be increased by the Gpi pin. Optical coupling element The size of the coupling current of the device is turned off, and the operation of the power conversion controller 540 is turned off, or 'as shown in the sixth figure, the optical coupling element 570 is coupled to the Gpi pin of the display controller 56, by means of packaging. The body Q8 forms a discharge path and turns off the operation of the power conversion controller 54. In step 706, when the DC voltage level drops to a predetermined level, the coupling current of the optical coupling element is reduced via the GPI0 pin. - (d) _ _ (4) 11 compensation job 'and start the operation of the f source conversion controller, in step 708, briefly turn on the primary side of the transformer, briefly charge the first capacitor and the second capacitor, for example, as the fifth As shown, the gate of the transistor Q4 is controlled by pulse width modulation or pulse frequency modulation, so that the transformer 530 charges the first capacitor C1 and the second capacitor C2 on the secondary side. The eighth figure shows a very low power consumption power conversion controller _ according to the embodiment of the present invention, having feet such as HV, VDDp, qing, cs, c 〇 Mp, and gnd' when applied to the fifth embodiment Operation, the operation of the external circuit of each pin in the eighth figure is as described in the foregoing embodiment. Very low power consumption • Conversion, the controller 800 includes comparators _, 820, hysteresis comparators, oscillator 840, current source δ42, voltage regulator 85 〇, positive and negative crying _, . and gate _, 872, The buffer is, the control circuit 890, the resistors R80, R82, and the back sodium diode 〇8〇. The ninth figure shows the main 峨 waveform diagram of the operation of the very low power consumption power conversion controller in the eighth figure, v ( VDDP), v (c 〇 I (VDDp), v (DRV), 5V signal; , COMP pin voltage signal, lose foot 1 ^ foot ^ power p pin current size commission pin 13 201104658 power conversion controller _ just started, hv pin via current source 842 to VDDp pin The thunder is going to - mountain, gentleman & well to W (not out) charging, when the potential is gradually = (10) more than 830 the positive input voltage is higher than the first - hysteresis reference ^ DH 'Wen coffee (four) lose The new standard is high, so that the output between the two is high. 'Enable voltage regulator 85 〇 output working electricity is willing to operate = 52 power supply conversion controller _ internal operation; and, hysteresis comparator (four) round high fresh Through the correction 892 and the anti-mesh, the current source 8 is turned off, and the HV pin is terminated to draw current from the outside. The control channel of the chia and the inverter 894 ensures that the current source is turned off as long as the output of the hysteresis comparator 83 is high. 842 blocks the external power consumption. (4) 84 〇 generation: square wave signal output to the SR positive and negative _ s input, and sr positive and negative _11 input terminal - start low level, Q output turns to high level, when the winning pin is pulled up, the externally connected transistor (not shown) will be turned on, current sensing (CS) pin The bit will also be pulled high, = over = comparator 81 〇 'SR positive and negative 860 "r input will be converted to high level" animal SR forward and reverse device 860 next time the trigger is triggered, the team is the counter-revolution The input end of the S input terminal is low level and high level respectively. After the trigger, the Q output end is turned to the low level. That is to say, the operation of the circuit, the input position of the input terminal and the R input terminal are triggered. Just reversed to generate the pulse width modulation DRV recording. For example, the square wave signal is a square wave signal of thin z, reducing the power consumption of the very low power consumption conversion controller _ in standby mode The square wave signal is outputted to the DRV pin through the gate 872 and the slow (10). Then, the capacitor outside the VDDp pin (not shown) slowly releases the stored power until the hysteresis comparator (4) is positive. The terminal input voltage reaches the second hysteresis reference voltage VDDL, so that the hysteresis comparison 201104658 ' makes the static G The output of the gate 872 is low. The output of the pin is low. The external transistor connected to the upper (not shown) is turned off and the external change is turned off. As shown in the ninth figure, 1_signal-start: take charge Power-off) 仏1 咖 '' at V ( VDDP ) from voltage VDDH to voltage VDDL, I (HV) signal (from external power supply) consumes a sudden drop in current to v 〇 ff. ^ iVDDp) corresponding to the released current is _P and I 〇 P, current Iop supply money conversion controller to drive the square wave signal on the DRV pin. Then, after the primary side guide of the external transducer passes, the secondary side display controller (not shown as α) can obtain power and can operate, and can control the V COMP) signal. The control of the cGMp pin disclosed in the foregoing embodiment: 匕 via the control of the compensation signal on the C0MP pin, the time interval of the width adjustment signal is elongated, and the real time length generated is also shortened, but the power is still converted. The controller _ operates in a fully monitored manner, so that the entire system is out of control and cannot be woken up. f V (C 〇 MP) signal low recording, forced _ oscillator 840 operation, or ' _ V (6)) woven potential high and low to adjust the output frequency of Zhen Sheng 840, for example, v ( c〇Mp) When the potential of the signal is high, the turn-out frequency becomes high. When the potential of the v(c〇Mp) signal is low, the output frequency (4) is low, or the reverse operation, so the potential of the V (〇) MP) signal can affect the power supply. The power consumption of the controller 800 is converted; and the control ratio is compared with the feedback voltage of the feedback terminal, and the low level is output to the feedback control signal 822, so that the output of the gate is the low-level read voltage. 5 weeks, the operation of the device 850, turn off the power conversion controller 8 (within 30 power supply, so that the power conversion controller is surveyed into the very low 201104658 power consumption mode 'current I (VDDp) is instantaneously reduced to i ff, preferably The ground current Ioff is less than the current 〇·1*ι〇ρ, or lower, and the falling speed of the V (VDDP) potential becomes very slow, that is, the y (VDDP) potential falling slope becomes smaller, and by controlling V (COMP) The signal can greatly lengthen the time to start charging the external capacitor next time, reducing the power consumption of the entire system; It is noted that pulling the V (COMP) signal low can cause the low level output to be output to the feedback control signal 822 via the inverter 896 and the OR gate 892 to force the current source 842 to be turned off, terminating the HV pin to draw current from the outside because the hysteresis is compared at this time. The output of the 830 is at a high level and the operation of the current source 842 has been turned off. That is, the simple control circuit 890 includes the OR gate 892 and the inverters 894, 896 can control the timing of the current source 842 to be turned on and off in a timely manner. Returning to the eighth figure, when the action of pulling down the V (COMP) signal is stopped, the control signal 822 is high after the voltage on the COMP pin is higher than the feedback reference voltage I 〇 ff. The current I (VDDp) is restored to ~I〇P, and the external large capacitor (not shown) resumes the operation power supplied to the power conversion controller surface, and the power conversion controller 800 operates normally until the V (VDDP) voltage is VDDL. When the positive terminal of the hysteresis comparator (4) is electrically connected to the second hysteresis reference voltage VDDL, the output level of the hysteresis comparison benefit 830 is turned from high to low, so that the output of the inter-gate is low, and the gate is low. The output of 872 is low, DRV pin Into a low level.
—然後，HV腳位經由電流源842對腳位VDDp外之電 合i未不出）短暫充電之後，V (VDDP)電位從VDDL J VDDH龟流I ( VDDp ).開始進行放電如此循環運 而CO朦腳位可以先經過增益放大器811，例如增益 _之增㈣整’此增益調整可以依照實際電路設計而調 16 201104658 整’進入比較器_之比較後，控制SR正反$ _ =端，i伏特（v)只是例示比較器⑽進行比較電壓的 辄圍’於此實施财，比較器81〇將.cs腳位電壓與C 腳位電壓與IV電塵兩個位準範圍内進行比較，熟知此 術之人士當可作出可能的電路更改變化。 ' 帛十關示根據本發明之—具體實施例之極低耗電之 • 電源轉換方法流程圖，於步驟刪，導通-電流源達第一 預定期間’例如充電到達電壓VDDH;於步驟1030，致能 :電源轉換控制器内之電壓調節器達第二預定期間，並於 弟二預定期間產生驅動訊號，例如為脈波寬度調變訊 者脈波頻率調變訊號’·於步驟1040，主張（ass⑻回授^ 制例如為第八圖中之回授控制訊號822，禁能電‘ 。周靖益’使仔電源轉換控制器進入一極低耗電模式，較佳 地，極低耗電模式下所消耗的電流低於正常運作之電流大 小之十分之-，或者更低，較佳地，主張回授控制訊號亦 1 強迫關閉電流源；於步驟1060，然後解主張回授控制訊 細電源轉換控制器恢復正常運作到達外部電容放電到電 壓VDDL，也就是運作達第三預定期間，控制外部電容從 電壓VDDL充電到電壓VDDfj。 第十員示根據本發明之一具體實施例之電源換 控制器 1100，具有 Hv，、VDDp，、DRV，、cs，、c〇Mp，及 GND等腳位’電源轉換控制器1100包含比較器1110、 =〇、遲滯比較器113G、振盪器n4G、電流源1142、電 壓調節H 1150、正反器Π6〇、及閘117〇、1172、緩衝器 !180以及反相器等等。 [S] 17 201104658 第十二圖齡軒—電源轉換控制n議運作 =要訊號波形圖’ V(VDDP，)、V(DRV，)、5v訊號分別 VDDp腳位之電廢訊號、DRV’腳位之電麗訊號、$伏 ;壓訊號。電源轉換控制器謂剛啟動時，HV,腳位唑甴 =流源U42對VDDp’腳位外之電容（未示出）充電，當 高到遲滯比較器⑽之正端輸人麵高“ :翁參考錢卿H，，練咖⑽之㈣立準為 ^使得及間1170之輸出為高，致能電壓調節器1150輪 工作電壓於訊號1152供電源機控制器議内部之運 而遲滞比較器1130之輸出高位準經由反相器 ’ Μ電流源1142 ’終止HV’腳位從外部汲取電流。 ^器1140產生一方波訊號輸出給SR正反器簡之s =端’而SR正反器1160之R輸入端-開始為低位準，- Then, the HV pin is not charged by the current source 842 to the pin VDDp.) After a brief charge, the V (VDDP) potential is discharged from the VDDL J VDDH turtle current I ( VDDp ). The CO 朦 pin can pass through the gain amplifier 811 first, for example, the gain _ is increased (four). The gain adjustment can be adjusted according to the actual circuit design. 201104658 After the comparison of the 'into comparator _, the SR is controlled by the positive and negative $ _ = ends. The i volt (v) is only a comparison of the comparison voltage of the comparator (10). In this implementation, the comparator 81 〇 compares the .cs pin voltage with the C pin voltage and the IV dust level. Persons familiar with the art can make possible changes in circuit changes.帛 关 关 关 关 关 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据Enable: the voltage regulator in the power conversion controller reaches a second predetermined period, and generates a driving signal during the predetermined period of the second generation, for example, a pulse width modulation pulse frequency modulation signal 'in step 1040, claiming (ass(8) feedback control system is for example, feedback control signal 822 in the eighth picture, disable power '. Zhou Jingyi' enables the power conversion controller to enter a very low power consumption mode, preferably, in very low power consumption mode The current consumed is less than - or less than the normal operating current. Preferably, the feedback control signal is also forced to turn off the current source. In step 1060, the feedback control signal power conversion is then claimed. The controller resumes normal operation until the external capacitor discharges to the voltage VDDL, that is, operates for a third predetermined period, and controls the external capacitor to be charged from the voltage VDDL to the voltage VDDfj. The tenth member shows according to the present invention. A power converter controller 1100 of an embodiment has Hv, VDDp, DRV, cs, c〇Mp, and GND pins. The power conversion controller 1100 includes a comparator 1110, a 〇, a hysteresis comparator. 113G, oscillator n4G, current source 1142, voltage regulation H 1150, flip-flop Π6〇, and gate 117〇, 1172, buffer! 180, inverter, etc. [S] 17 201104658 Twelfth Tuling Xuan - Power conversion control n operation = signal waveform 'V (VDDP,), V (DRV,), 5v signal VDDp pin electrical waste signal, DRV 'pin's electric signal, $ volt; pressure signal The power conversion controller says that when it is just started, the HV, the pin razor = the source U42 charges the capacitor outside the VDDp' pin (not shown), and when the high-to-hysteresis comparator (10) is at the positive side, the input side is high. : Weng reference Qian Qing H,, practice coffee (10) (4) set the standard to make the output of 1170 high, enable the voltage regulator 1150 round working voltage on the signal 1152 for the power supply controller to discuss the internal operation and delay The output high level of comparator 1130 terminates the HV' pin from the external source via the inverter 'Μ current source 1142'. ^ 1140 generates a square wave signal output to the SR flip-flop end s = Jane 'and the R input of the SR flip-flop 1160 - start at a low level,
Q輸出端轉為高位準’當DRV，腳位上被拉高位準，外部連 ^的電晶體（未示出）會被導通，電流感測⑽，）腳位也 ，因此跟著被拉高位準，經過比較器111〇，SR ^輸入端會轉變為高位準，當队正反器mo下L次接丨 j發時，正反器116〇之S輪人端與R輸人端分別為低 位準與雜準，觸發後，Q輸―轉為低位準，也就是說， 此電路之運作，S輸入端與尺輸入端之輸入位準於觸發時 J子都反相以產生脈波寬度調變訊號於腳位上。 ^例而言’方波訊號為1MHz之方波訊號，降低電源轉換 ，制器_於待機模式下的功耗，透過及閘1172與緩衝 裔mo將方波訊號於DRV，腳位上輸出。接著，伽〆腳 位外之電容（未示出）將所儲存的電力緩慢釋出，直到遲 201104658 π比权113G之正端輸人電壓到達第二遲滞參考電壓 VDDL，，使得遲滯比較器1130之輸出位準由高轉低，使得 及閘㈣之輸出為低’及閘1172之輸出為低，膽，卿位 之輸出為低’關閉連接於其上的外部電晶體（未示出）而 關閉外1:¾:壓器（未示出）之—次侧，如第十二圖所示， VDOT’從$壓VDDH，到電壓VDDL，間來回充放電震還。 或者’如第十二圖右嫩形所示，#欲產生脈波寬度調變 訊號於DRV’腳位上時，VDDp，腳位之電壓仍高於電壓 VDDL，’由於遲滞比較器⑽之正端輸人電壓尚未到達第 二遲滯參考雜VDDL，，電絲⑽保料動作，hv， 腳位不汲取㈣糕；脈波寬度調變訊號魅於娜，腳 位上後’會藉由第十三圖中變壓器133〇的副繞組⑽對 電容=1，充電’使得DRV，腳位上的電壓㈣地上升。 弟十三圖顯示根據本發明之另一具體實施例之極低耗 _控制電路1300，電源轉換控制器1340經由高壓電 轉位HV，由節點B，短暫概取外部電源，使得電源轉換 1340内部的受控電流源，經由電壓訊號VDDp，對 电合C1充電’短暫地驅動訊號DRV，，啟動變壓器B3〇 之—次側’使得變㈣咖對電容α，充電以及對二次側 大電谷C2充電達-預定電壓或者充電一預定期間。舉 例而言，可以將第十-圖之電源轉換控制器誦施用於第 :二圖中的電源轉換控制器134〇以進行運作。於此實施例 ▲顯不控制為136。可以藉由Gpi〇腳位改變在省電模式 下=【器1330之一次侧之電壓比例，以大幅降低極低耗電 顯示控制電路1300之整體耗電量。Q output turns to high level 'When DRV, the pin is pulled up, the external transistor (not shown) will be turned on, current sensing (10),) the pin is also, so it is pulled up After the comparator 111〇, the SR^ input will be converted to a high level. When the team is re-suppressed by the MO, the S-wheel terminal and the R-input terminal are respectively low. Quasi-and miscellaneous, after the trigger, Q-converted to a low level, that is, the operation of this circuit, the input of the S input and the input of the ruler is inverted at the trigger to generate the pulse width modulation. The signal is on the pin. ^ For example, the square wave signal is a 1MHz square wave signal, which reduces the power conversion, the power consumption of the controller _ in standby mode, and the gate wave signal is output on the DRV through the gate 1172 and the buffer. Then, a capacitor (not shown) outside the gamma pin slowly releases the stored power until the positive input voltage of the 201110658 π ratio 113G reaches the second hysteresis reference voltage VDDL, so that the hysteresis comparator The output level of 1130 turns from high to low, so that the output of the gate (4) is low and the output of the gate 1172 is low, and the output of the gate is low. The external transistor connected to it is turned off (not shown). And off the outer side of the 1:3⁄4: voltage regulator (not shown), as shown in the twelfth figure, VDOT' from the voltage VDDH to the voltage VDDL, back and forth between the charge and discharge. Or 'as shown in the twelfth figure on the right side, #When the pulse width modulation signal is generated on the DRV' pin, the voltage of VDDp, the pin is still higher than the voltage VDDL, 'Because of the hysteresis comparator (10) The positive input voltage has not yet reached the second hysteresis reference miscellaneous VDDL, the wire (10) protects the action, hv, the foot does not draw (four) cake; the pulse width modulation signal is enchanted in the na, the foot will be followed by the first In the thirteenth diagram, the secondary winding (10) of the transformer 133 对 has a capacitance of 1, and the charging 'such that DRV, the voltage on the pin (4) rises. Figure 13 shows a very low power consumption control circuit 1300 according to another embodiment of the present invention. The power conversion controller 1340, through the high voltage electric index HV, is briefly taken by the node B to externally supply the external power source, so that the power supply is switched inside the 1340. The controlled current source, through the voltage signal VDDp, charges the electric C1 'slowly to drive the signal DRV, and starts the transformer B3's - the secondary side' to make the (four) coffee to the capacitor α, charge and the secondary side large electric valley C2 Charging up to a predetermined voltage or charging for a predetermined period of time. For example, the power conversion controller of the tenth diagram can be applied to the power conversion controller 134 of Fig. 2 for operation. This embodiment ▲ is not controlled to 136. The voltage ratio of the primary side of the device 1330 can be changed by the Gpi pin in the power saving mode to greatly reduce the overall power consumption of the extremely low power consumption display control circuit 1300.
19 201104658 μ參考第十二圖，在正常模式下，顯示控制器136〇 藉由GPIO腳位將開關SW，關閉，顯示控制器136〇經由電 阻R1’提供正常的電壓比例，使得變塵器1330之二次侧之 輸出電摩訊號VCC5V，最高約達5伏，· sw，可以利用 電晶體開關實現；在省電模式下，顯示控制器136G降低二 次側之電壓比例，使得輸出電壓訊號VCC5V，降低至一預 疋低^ ’例如4伏、甚至為35伏，只要能確保顯示控 制器1360於省電模式下、經由低屢差線性穩㈣135〇獲得 足夠的電塵供應，舉例而言’顯禾控制器136Q藉由肥〇 腳位將開關SW，導通，使得電阻R1，與R2，並聯，亦降低了 電阻R1 ’與R2’並聯所產生的辦，可經由適當的設計電阻 R1與R2’之阻值，使得輸出電壓訊號原本vcc5v，處於約 5伏的電壓降低至預定低電壓，例如3 5伏。 ，明參考第十二圖，舉例而言，可以利用一分流調節器 Z’（shunt regUlator)於節點χ提供2 $伏的參考電壓，電 阻R1與R2可以選擇使用SK歐姆。正常模式下，將開關 SW關閉，經由電且R1,提供正常的電壓比例，使得變壓器 1330之二次側之輪出電壓訊號VCC5v，為5伏，流經電阻 R1’之電流I，為0·5毫安培（mA);進入省電模式後，將開 關SW V通’使得電阻R1，與R2，並聯使得並聯電阻值為 2.5K區人姆’即點χ所提供之2.5伏的參考電壓與電流 ^mA，使得電壓從5伏降低至，J 3.75伏，另一方面，變壓 器Π30之一-人側主要範電在於低壓差線性穩壓器出〇與 顯不控制H 1360’假設低壓差線性穩壓器135◦與顯示控 制器簡於省電模式所需要耗㈣電流㈣為Μ，可 201104658 以了解到省電模式下的功率消耗可從原先的5亳瓦（mW) (=5V*lmA)大幅降低為 3.75mW (=3.75V*lmA)。也就 疋况’電壓比例單元丨37〇耦接於變壓器133Q之二次側之 輸出以及顯示控制器136〇’電壓比例單元137G包含電阻 Rl、R2’、RX以及開關sw，，電壓比例單元137〇接收來 自分，調節器Z，於節點X提供的參考電壓，並受控於顯示 控制器1360’例如_ GPI〇腳位，使得#顯示控制器_ 進入省電模式時’可以改變電壓比例單元所提供之電19 201104658 μ Referring to the twelfth figure, in the normal mode, the display controller 136 turns off the switch SW by the GPIO pin, and the display controller 136 provides a normal voltage ratio via the resistor R1', so that the dust filter 1330 The output of the secondary side of the electric motor signal VCC5V, up to about 5 volts, · sw, can be realized by the transistor switch; in the power saving mode, the display controller 136G reduces the voltage ratio of the secondary side, so that the output voltage signal VCC5V , to reduce to a low voltage ^ 'for example 4 volts, or even 35 volts, as long as the display controller 1360 can be obtained in the power saving mode, through the low-order linear stability (four) 135 〇 to obtain sufficient dust supply, for example ' The display controller 136Q turns on the switch SW by the fat pin, so that the resistors R1 and R2 are connected in parallel, and the resistors R1' and R2' are also connected in parallel, and the appropriate design resistors R1 and R2 can be used. The resistance value is such that the output voltage signal is originally vcc5v, and the voltage at about 5 volts is lowered to a predetermined low voltage, for example, 35 volts. Referring to the twelfth figure, for example, a shunt regulator Z' (shunt regUlator) can be used to provide a reference voltage of 2 volts at the node ,, and resistors R1 and R2 can optionally use SK ohms. In the normal mode, the switch SW is turned off, and the normal voltage ratio is supplied via the electric and R1, so that the voltage VCC5v of the secondary side of the transformer 1330 is 5 volts, and the current I flowing through the resistor R1' is 0. 5 milliamperes (mA); after entering the power-saving mode, the switch SW V is turned on 'so that the resistors R1, R2 are connected in parallel so that the parallel resistance value is 2.5K, which is the reference voltage of 2.5 volts provided by the point χ With the current ^mA, the voltage is reduced from 5 volts to J 3.75 volts. On the other hand, one of the transformers Π30 - the main side of the human body lies in the low-dropout linear regulator and the uncontrolled H 1360' hypothesis of low dropout The linear regulator 135◦ and the display controller are simpler than the power-saving mode (4) current (four) is Μ, can be 201104658 to understand that the power consumption in the power-saving mode can be from the original 5 watts (mW) (= 5V * The lmA) is significantly reduced to 3.75mW (=3.75V*lmA). In other words, the voltage proportional unit 丨37〇 is coupled to the output of the secondary side of the transformer 133Q and the display controller 136〇 The voltage proportional unit 137G includes the resistors R1, R2', RX and the switch sw, and the voltage proportional unit 137 〇 Receives the reference voltage supplied from the sub-controller Z at the node X and is controlled by the display controller 1360', for example, the _GPI pin, so that the #display controller_ can enter the power saving mode. Electricity provided
£比例進而降低整體之耗電量。箭頭方向標示出幾個 路分析巾社要電錢向，使得熟知此技φ人何以 解本實施例之運作。 第十四®!歸㈣本發私具體實關 號VCC5V’的信赛、、古报同Λ Α Λ 干M W / 合參考f十三圖之運作，鶴 開關SW，，經由電阻R]，样1字0的輸出拉低，關閉 隸VCC5V，不」 常的電壓比例，使得電塵 入^為5伏位準。當顯示控制器1360進 =电核式’將gPI0的輸出拉高，將開關撕 付电阻R1與R2,並聯，以降低 電 VCC5V，於省電槿式夕认， 從仲电域讯唬The ratio of £ further reduces the overall power consumption. The direction of the arrow indicates that several road analysis companies have to pay for money, making it familiar with the operation of this embodiment. The fourteenth!! (4) the private specific real number VCC5V' of the letter of the game, the ancient newspaper with the same Λ Λ dry MW / with reference to the operation of the f th map, crane switch SW, through the resistor R], The output of 1 word 0 is pulled low, and the VCC5V is turned off. The voltage ratio is not constant, so that the electric dust is at the 5 volt level. When the display controller 1360 enters the electric cell type to pull the output of gPI0 high, the switch tears the resistors R1 and R2 in parallel to reduce the electric VCC5V, and recognizes the power saving mode.
、 輪出降低為3,75伏位準，去趣-制器1360預計要回到正當 田頦不L 關閉開關SW’，經的輸出拉低’ 電壓訊號VCC5V，正常_巾提供正彳的電觀例，使得 1360進人正常模式。^此技^伏位準，並令顯示控制器 所揭露之電路，可,士相了解適當地修改 得更低，㈣X維_㈣彳^訊號VCC5V，之輸出降 A 丁&制态1360之運作。 201104658 -第十五圖顯不根據本發明之具體實施例之極低乾電顯 不控制方法之流程圖，於步驟1520，顯示控制器進入 電模式’啟動極低耗電之機制;於步驟153〇，顯示控制吳 2由GPI〇腳位改變電壓比例，以降低變壓器之“ 輪出電麼位準，舉例而言，可以降低為35伏；於步驟 1540，將二次側之輸出電壓經由低壓差線性穩壓器穩壓以 輸出供顯示控制器之運作。當顯示控制器離開 切拉式時，即經由GPI0聊位回復電壓比例以及 伏電壓位準。 紅上所述’本發明揭示一種極低耗電顯示控制電路， G括具有-次側以及二次侧之變壓器、祕至變麗哭之二 ，側之電容，穩壓器、顯示控制器以及電壓比例單:^ k用以於-次側接收高壓直流電墨以轉換成直流電壓於 --人側，電容用以穩定直流電遷；穩壓器福接至電容，用 直流電壓並產生直流穩壓輪出；顯示控制器_至 〜堅时用以接收直流穩塵輸出而運作；電壓 ==器以及變壓器之二次側，用以接收參考電Ϊ n、s包堅比例於一次側，使得顯示控制器可於省電模 式猎由通用型輸人輸出腳位改變電壓比例。 、 ^發明更揭示—種極低耗電晏員示控制方法 =進=電模式;顯示控制器改變電壓比例以心 叮輪出電壓位準；以及將二次側之該輸出 以產生穩壓輪出供顯示控制器於省電 綜上所述’雖然本發明已以較佳實施例揭露如上，然 22 201104658 其並非用以限定本發明。任何熟習此技藝者，在不脫離本 發明之精神和範圍内，當可作各種更動與潤飾，本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 本案得藉由下μ圖式及說明，俾得更深人之了解. 第-圖顯示習知技藝之顯示器⑽賴示電路方塊圖。·, the round reduction is reduced to 3,75 volts level, and the fun-control device 1360 is expected to return to the correct Tian Hao not L to close the switch SW', the output is pulled low 'voltage signal VCC5V, normal _ towel provides positive electricity The example makes the 1360 enter the normal mode. ^ This technology ^ volt level, and the circuit revealed by the display controller, can be properly modified to be lower, (four) X-dimensional _ (four) 彳 ^ signal VCC5V, the output is reduced A D & 1360 Operation. 201104658 - The fifteenth diagram shows a flow chart of a very low dry power display control method according to a specific embodiment of the present invention. In step 1520, the display controller enters an electrical mode to initiate a mechanism for extremely low power consumption; 〇, the display control Wu 2 changes the voltage ratio by the GPI pin to reduce the “round-out” level of the transformer, for example, can be reduced to 35 volts; in step 1540, the secondary side output voltage is passed through the low voltage. The differential linear regulator is regulated to output for the operation of the display controller. When the display controller leaves the Cheer-type, the voltage ratio and the voltage level are restored via the GPI0 chat. Low power consumption display control circuit, G includes transformers with - secondary side and secondary side, secret to the second, the side of the capacitor, voltage regulator, display controller and voltage ratio single: ^ k used in - The secondary side receives the high-voltage direct current ink to be converted into a DC voltage on the human side, the capacitor is used to stabilize the DC current; the voltage regulator is connected to the capacitor, and the DC voltage is generated by the DC voltage; the display controller _ to ~ Jian Used to pick up The DC stabilizes the dust output and operates; the voltage== device and the secondary side of the transformer are used to receive the reference Ϊn, s package is proportioned to the primary side, so that the display controller can be hunted by the general-purpose input in the power-saving mode. The pin changes the voltage ratio. The invention reveals that the control method of the extremely low power consumption is as follows: the input mode is changed; the display controller changes the voltage ratio to the heart voltage level; and the secondary side The output is used to generate a voltage regulator for the display controller to save power. Although the invention has been disclosed in the preferred embodiment as above, it is not intended to limit the invention to any of the above. Anyone skilled in the art, Within the spirit and scope of the present invention, the scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. And the description, the deeper understanding. The first-figure shows the display of the conventional technology display (10).
第，圖齡减树_體實施狀極健鶴示控制電 第二圖顯示相關於第二圖實施例之主要波形圖。 電顯示控 第四圖騎减本發㈣—具體實闕之極低耗 制電路。 第五圖顯示根據本發明另―具體實關之極低耗 制電路。 不控 第六圖顯錄據本發㈣—具體實關之極低 制電路。 电員不控 第七圖顯稀據本發明之具體實施狀極 方法之流程圖。 μ不控制 具體實施例之極低耗電電源轉 第八圖顯示根據本發明之— 換控制器。 第九圖顯示第八圖中極低耗電電源轉換控制器運作 訊號波形圖。 <主要 第十圖顯雜據本發明之―具财施狀極低 轉換方法流程圖。 屯源 23 201104658 ^。目‘知根據本發明之_具體實關之電轉換控制 第十二圖顯 波形圖。 示第十一圖中電源轉換控制器運作之主要訊號 第十二圖顯示根據本發明之另— 示控制電路。 具體實施例之極低粍電顯 第十四圖顯示第十三 形圖。 圖中輸出電壓訊號VCC5V，的信號波 ίι =圖·，根據本發明之具體實施例之極低耗電顯示控 制方法之流裎圖。 仏 【主要元件符號說明】 本案圖式中所包含之各元件列示如下： 100顯示電路方塊圖 110電源電路 120縮放控制器300、400、500、1300 112 交流電源 114、116電壓訊號 130 背光模組 顯示控制電路 302交流電源 310 整流器 320、420偏壓電路 330、530、1330變壓器340、540、800、11〇〇、1340電源轉換控制器 342、542、842、1M2 電流源 350穩壓器 360 縮放控制器 370、570光耦合元件 560、1360顯示控制器 550、1350低壓差線性穩壓器 24 201104658 810、820、1110、1120 比較器 812、822、852、1152 訊號 830、1130遲滯比較器. 1332 副繞組 811 增益放大器 840、1140振盪器 850、1150電壓調節器 860、1160正反器 870、872、1170、1172 及閘 880、1180 緩衝器 890 控制電路 892 或閘 894、896、1190 反相器 1370 電壓比例單元 F1 熔絲 A、B、B，、X 節點 NTC 電阻 SW’開關 VDDP、VDDP，、VCC14V、VCC14V，、VDD3V3、VDD3V3， 訊號 COMP、COMP，、HV、HV’、VCC5Vsense、AC—OFF 訊號 DRV、DRV，、VCC5V、VCC5V’ 訊號 Rll、R12、R13、R2、R4、R5、R6、R72、R80、R82、 R1’、R2’、R18、RX 電阻 D1、D21、D22、D3、D4、D5、D6、D80 二極體 (3卜（32、（33、（34、（28電晶體 cn、C2、C3、C4、Cl，、C2，電容 z’分流調節器First, the age of the tree is reduced. The second figure shows the main waveform diagram related to the embodiment of the second figure. Electric display control The fourth picture of riding and reducing the hair (4) - the extremely low-cost circuit. The fifth figure shows an extremely low-cost circuit in accordance with the present invention. Not controlled The sixth picture is recorded according to the hair (4) - the extremely low-level circuit. The electrician does not control. The seventh figure shows a flow chart of a specific embodiment of the present invention. μ does not control the extremely low power consumption of the specific embodiment. The eighth diagram shows the controller according to the present invention. The ninth figure shows the waveform of the operation signal of the extremely low power consumption conversion controller in the eighth figure. < Mainly the tenth figure shows a flow chart of the extremely low conversion method according to the present invention. Wuyuan 23 201104658 ^.目 知 知 知 知 知 知 知 知 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见The main signal showing the operation of the power conversion controller in Fig. 11 shows a control circuit according to the present invention. The extremely low power display of the specific embodiment shows the thirteenth figure. In the figure, the signal voltage of the output voltage signal VCC5V, ίι = Fig., is a flow chart of the extremely low power consumption display control method according to the embodiment of the present invention.仏 [Main component symbol description] The components included in the diagram of the present invention are listed as follows: 100 display circuit block diagram 110 power supply circuit 120 scaling controller 300, 400, 500, 1300 112 AC power supply 114, 116 voltage signal 130 backlight mode Group display control circuit 302 AC power supply 310 rectifier 320, 420 bias circuit 330, 530, 1330 transformer 340, 540, 800, 11 〇〇, 1340 power conversion controller 342, 542, 842, 1M2 current source 350 regulator 360 scaling controller 370, 570 optical coupling element 560, 1360 display controller 550, 1350 low dropout linear regulator 24 201104658 810, 820, 1110, 1120 comparator 812, 822, 852, 1152 signal 830, 1130 hysteresis comparator 1332 secondary winding 811 gain amplifier 840, 1140 oscillator 850, 1150 voltage regulator 860, 1160 flip-flop 870, 872, 1170, 1172 and gate 880, 1180 buffer 890 control circuit 892 or gate 894, 896, 1190 reverse Phase 1370 voltage proportional unit F1 fuse A, B, B, X node NTC resistor SW' switch VDDP, VDDP, VCC14V, VCC14V, VDD3V3, VDD3V3, signal COMP, COMP, HV, HV', VCC5Vsense, AC-OFF signal DRV, DRV, VCC5V, VCC5V' signal R11, R12, R13, R2, R4, R5, R6, R72, R80, R82, R1', R2', R18, RX Resistors D1, D21, D22, D3, D4, D5, D6, D80 diodes (3, (32, (33, (34, (28 transistor cn, C2, C3, C4, Cl, C2, capacitor z) 'Shunt regulator