TW201103110A - Under land routing - Google Patents

Under land routing Download PDF

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Publication number
TW201103110A
TW201103110A TW098124713A TW98124713A TW201103110A TW 201103110 A TW201103110 A TW 201103110A TW 098124713 A TW098124713 A TW 098124713A TW 98124713 A TW98124713 A TW 98124713A TW 201103110 A TW201103110 A TW 201103110A
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TW
Taiwan
Prior art keywords
layer
channel
component
track
insulating
Prior art date
Application number
TW098124713A
Other languages
Chinese (zh)
Other versions
TWI487078B (en
Inventor
Zaid Aboush
Original Assignee
Cambridge Silicon Radio Ltd
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Publication date
Application filed by Cambridge Silicon Radio Ltd filed Critical Cambridge Silicon Radio Ltd
Priority to US12/829,745 priority Critical patent/US8368224B2/en
Publication of TW201103110A publication Critical patent/TW201103110A/en
Application granted granted Critical
Publication of TWI487078B publication Critical patent/TWI487078B/en

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An electronic component comprising an integrated device and a plurality of packaging layers in which routing between locations on the device and lands on the surface of the component is provided by a redistribution layer. The redistribution layer may be routed below the extent of a contact pad on the surface by providing a channel through the via and redistribution layers underneath that land.

Description

201103110 六、發明說明： 【發明所屬之技彳軒領域】 發明領域 本發明係有關整合的裝置之封裝技術，且尤係有關使 用一晶圓級晶片尺度封裝體(WLCSP)之重分布層（RDL)在 連接區下方的導路安排技術。 C先前技術j U 發明背景 WLCSP是一種封裝技術，其中供作外部接點的焊接凸 體或知球會被形成其上，並在該晶圓或面板分割之前電連 接於一整合的裝置，例如一積體電路(IC)，整合式被動裝置 ： _)，微機電系統_MS)裝Ϊ，顯示裝置，或影像感測 ' 裝置。 WLCSP裝置包含一球體下金屬化(UBM)層在該裝置的 表面上以供焊球台區的形成，而以絕緣聚合物層分隔於該 Q 整合裝置。一中間的金屬RDL會被提供以界定軌路來將該 整合裝置上的接墊接合於該UBM層中的焊球台區。穿過該 聚合物層的通道會提供該整合裝置連接點與該RDL軌路之 間，和該RDL軌路與該UBM焊球台區之間的連接。 第1圖示出一典型的WLCSP裝置之平面圖和載面圖。 1C層102係形成於該晶圓中，且一下聚合物103係沈積在該 晶圓上。一通道104會被形成穿過該第一聚合物層103以使 該1C上之一接墊105與該WLCSP RDL 106接觸。一上聚合物 層107係沈積在該RDL 106上。一通道108會被形成穿過該上 3 201103110 聚合物層107以使該RDL 106與一形 〜成於該UBM層中的二 區101接觸。該UBM台區101係用來仳小θ丄 σ 球或凸體的附接。 該RDL 106和UBM台區1〇1之間的、3,., 间的通遏108可被界定成 比該焊球台區101和相關的RDL區域更小或較大些，俾使1 各層鎖定於該聚合物中，以將該等金屬層機械_固於該/ 聚合物進並及於該1C。 若該等整合裝置的複雜性增加則所需的外部接點數目 亦會增加，故會導致該rdi^〇UBm層中的導路安排複雜性 增加。 導路安排問題可藉增加層數來解決（例如使用兩個 RDLS)，但增加層數在此特定用途中是不受歡迎的，因為添 加層數亦需要添加的聚合物層。該等聚合物層的沈積會利 用一熱製程，其必須相對於該整合裝置的熱預算來被考 量俾提问可賴度考量。添加層數亦會增加製程步驟因 而增加每一裝置的成本。 因此有需要-種技術以容許整合裝置的接塾和該UBM 層中的焊球台區之間能有改良的信號導路安排。201103110 VI. Description of the Invention: [Technical Fields of the Invention] Field of the Invention The present invention relates to packaging techniques for integrated devices, and more particularly to a redistribution layer (RDL) using a wafer level wafer scale package (WLCSP) ) Route routing technology below the connection zone. C prior art j U BACKGROUND OF THE INVENTION WLCSP is a packaging technique in which solder bumps or balls for external contacts are formed thereon and electrically connected to an integrated device before the wafer or panel is divided, for example An integrated circuit (IC), integrated passive device: _), MEMS _MS) mounting, display device, or image sensing 'device. The WLCSP device includes a sub-spherical metallization (UBM) layer on the surface of the device for the formation of solder ball pads and is separated from the Q integrated device by an insulating polymer layer. An intermediate metal RDL will be provided to define the track to bond the pads on the integrated device to the pad stage in the UBM layer. A passage through the polymer layer provides a connection between the integrated device connection point and the RDL rail and between the RDL rail and the UBM solder ball station. Figure 1 shows a plan view and a carrier view of a typical WLCSP device. A 1C layer 102 is formed in the wafer, and a lower polymer 103 is deposited on the wafer. A channel 104 is formed through the first polymer layer 103 to contact one of the pads 105 on the 1C with the WLCSP RDL 106. An upper polymer layer 107 is deposited on the RDL 106. A channel 108 is formed through the upper 3 201103110 polymer layer 107 to bring the RDL 106 into contact with the second region 101 formed in the UBM layer. The UBM stage 101 is used to reduce the attachment of a small θ 丄 σ ball or a convex body. The passivation 108 between the RDL 106 and the UBM mesa 1〇1 can be defined to be smaller or larger than the solder ball table area 101 and the associated RDL area, so that the 1 layers are locked In the polymer, the metal layers are mechanically fixed to the polymer and further to the 1C. If the complexity of the integrated devices increases, the number of external contacts required will also increase, which will result in increased routing complexity in the rdi^〇UBm layer. Routing problems can be solved by increasing the number of layers (for example, using two RDLS), but increasing the number of layers is undesirable in this particular application because the number of layers added also requires the addition of a polymer layer. The deposition of such polymer layers utilizes a thermal process that must be considered relative to the thermal budget of the integrated device. Adding the number of layers also increases the cost of each device by increasing the number of process steps. There is therefore a need for techniques to allow for improved signal routing arrangements between the interface of the integrated device and the solder ball stage in the UBM layer.

【明内J 發明概要 本概要說明係被提供來以一簡化的形式介紹一種概念 的L擇I會被進一步描述於後的詳細說明中。此概要說 明並非要明定所請求主題内容的關鍵特徵或主要特徵，亦 非要被用作決定所請求主題内容的範圍之_輔助。 -種電子構件包含—整合的裝置及多數的封裝層，該 201103110 等封裝層包含該等封裝層之一金屬層在該構件的表面上 含有一台區，該等封裝層之一金屬重分布層在該表面下方 而含有一第一軌路用以將信號由該台區導送至該構件中的 其它位置，該等封裝層之一上絕緣體緣層介於該金屬表面 層和該金屬重分布層之間，一通道穿過該上絕緣層而將該 台區連接於該重分布層中的軌路，及一第二軌路在該重分 布層中，其係被排設穿過該第一軌路和該台區範圍底下的 通道中之一間隙，而使該第二執路不會與該台區、通道或 δ亥台區範圍内的第一執路形成電接觸。 該通道可被形成於至少兩個各個的部件中，並有一絕 緣槽道介於至少二該等部件之間，其中該絕緣槽道會形成 用以排設第二軌路的間隙。 該構件可包含多數的台區、通道和齡，其巾多數條軌 路會被排設穿過其錄灿通射之錄㈣應的間隙。 於此亦提供-種構件的晶圓或面板，其含有至少一如 上所述的構件。 於此亦提供一種在—含有一整合裝置與多數封裝層之 電子構件中界定信號導路的方法，該方法包含以下步驟： 在該等封裝層之-表面金屬層中界定—台區，界定一通道 將該台區連接於該等封裝層之-重分布層中之-第一軌 路，其㈣表面金屬層係m缘層來傾重分布層分 開，在該通道與該台區範圍内的第—軌路中界定—間隙， 及在該重分布區中界I第二執路，其中該第二軌路會被 排設穿過關隙。錢其不會與該台區、通道、或該台區 5 201103110 範圍内的第一軌路形成電接觸。 在該台區與第一軌路之間的通道可被界定於至少二各 別的部件之間，並有一絕緣槽道在至少二該等部件之間而 形成用以排設該第二軌路的間隙。 該絕緣槽道可為筆直的或可為非筆直的。 該電子構件可為一晶圓級晶片尺度封裝裝置，該表面 層可為一球體下金屬化(UBM)層，該連接點可為一焊球台 區，而該整合裝置可為一積體電路，該構件可更包含一下 絕緣層用以隔絕該重分布層與該積體電路，並有至少一通 道穿過該下絕緣層而將該重分布層中之一軌路連接於該積 體電路上之一接墊。 於此亦提供一種製造一電子構件晶圓或面板的方法， 乃包令—如上所述的方法。 該晶圓或面板可包含至少一如上所述的構件。 所提供的特徵可依需要來被組合，乃為專業人士所顯 而易知，且能與本發明的任何態樣結合。 圖式簡單說明 本發明的實施例將會參照以下圖式藉由舉例來被描 述，其中： 第1圖示出一習知技術的WLCSP裝置之透視圖和截面 圖， 第2圖示出使用一球體下金屬化層來形成一重分布層 中的軌路之間的連結物； 第3圖示出界定於一球體下金屬化層中之台區底下執 2〇11〇311〇 路的排設；及 第4圖不出一被示於第3圖中的台區之平面圖和截面圖。 C實施方式】 較佳實施例之詳細說明 I發明的實施例係僅藉舉例說明如下。該等例子代表 申叫人目剛所知之將本發明付諸實施的最佳方式，雖它們 、、非月b被達ί丨的僅有方式。此說明陳述該例子的功效及用 ο μ構建和操作該例子的步驟順序。但是，相喊同等的功 效和順序亦可IX不同的例子來達成。 第2圖示出—RDL和UBM層排路系統的立體圖，其可容 許軌路通過而不需要添加層。因此軌路的密度能夠增加而 無需太大的添加費用。 通道200 ’ 201係被界定於該RDL和UBM層之間，且一 轨路202會被界定於該UBM層中來連接該等通道2〇〇、2〇1。 相對於傳統的布局部該UBM層係被利用當作一排路層，故 0 容許軌路通過而無需添加層。 第3圖示出一WLCSP裝置的立體圖，更包含一種將rdl 中的信號由該1C導送至該UBM層中之焊球台區的方法。第4 圖不出一焊球台區300附近區域的平面圖和截面圖。在一焊 球台區300的第一例中，該RDL 310、311和通道302、303 會被圖案化成兩半，並有一槽道304介於該兩半之間。該 RDL的第一半310和該通道的第一半302會以傳統方式運作 而將信號由該RDL軌路305傳導至該焊球台區3〇〇。該通道 的第二半303和RDL的第二半311會提供該焊球台區3〇〇的 7 201103110 機械支撐，及該等金屬層對該聚合物和1(：的鎖固。 該槽道304會被利用來排設該咖中的另一信號轨路 306，俾可容許軌路通過而無需一添加層。 如在第3圖中有關UBM台區307所示，穿過該通道和 RDL的槽道308並不-定是筆直的，而可採取—肢形狀以 容該RDL中的轨路之有效率排設。該槽道的路徑亦會助益 於該UBM台區的機械性質，當選擇該UBM台區底下的排路 時此應要被考慮。在習知技術的系統中該軌路3〇9必須傍沿 著台區307來被排設，故會增加同等連接性所需的面積。 第3圖的排路系可具有超過第2圖所示者的優點，因為 第2圖的系統會在該UBM層中留下暴露的軌路，此可能會減 低可彳§賴度或增加焊料短接電路的可能性。相對地，第3圖 的系統不會增加該UBM中的軌路數目。且，第2圖的系統需 要增多的通道位置數目以容許軌路通過，而第3圖的系統不 需要任何添加的通道位置，因執路的通過發生在既有的通 道位置。 在該UBM焊球台區底下的槽道和執路具有影響該 UBM台區之機械和電性質的潛力。但是，—典型的UBM焊 球台區相較於10〜25μιη之典型軌路寬度會有一24〇μηι的直 徑。因此該槽道相較於該焊球台區係很小，故而對該台區 的性質不可能會有任何實質的影響。 傳統的設計和製造技術可被用來設計和製造利用所述 排路系統的裝置。 在s玄UBM台區，通道和RDL區域’及運行穿過該通道 201103110 與RDL中之槽道的軌路之間玎能會有電性交互作用，其在 使用傳統技術的設計過程中被納入考量。該交互作用可 被用來提供該等信號路徑之間的寄生電容或電感的已知 值。例如用以達到電供應去耦，或可提供不同的信號路徑 間之一所需的交互作用或耦合。 該等圖式已示出單一的重分布層，但多個重分布層亦 可被利用，而仍然適用於此所述之本發明的原理。 若台區被描述為焊球台區，則應請瞭解其概括係指在 該WLCSP之表面上的台區，而非唯獨僅用於焊球的台區； 例如印刷焊接凸體或銅柱亦可取代燁球來被使用。焊球可 被預先形成。 以上描述主要係以WLOSP技術的内容來提供，但該等 技術同樣可應用來封裝其它的整合裝置以及半導體ICs。例 如’該等技術亦可被應用於整合的被動裝置(IPDs)，微機電 系統(MEMS)裝置，光學微機電系統(0MEMS)裝置，顯示 裝置’及影像感測裝置等。除了晶圓以外，該技術亦可被 用於電性面板，或電子構件。同樣地，材料系統譬如陶曼 和玻璃亦可被使用。 若有疊覆或在上方等詞語被使用於本文件中，除非另 有不同的揭示’它們並非要表示該部件或層當在該晶圓或 面板的平面圖視之會具有相同的範圍或是位於相同或重疊 的區域，而是指該部件或層當在戴面圖視之大致位於上方 一其係較接近於該裝置的表面’而更遠離該IC。同樣地， 在底下和於下方等字語係用來表示該部件或層當在截面圖 9 201103110 現之係大餘於下方-其絲⑽㈣近該κ。 聚合物係被提供作為-用以隔絕該等金屬層的介電声 之—例，但如所瞭解其它的材料亦可_用 或破璃亦可適用，乃視被使—材料系統而定。 在以上描述中一形成於 ‘。η料道之例已被提 2该通道亦可被形成於兩個以上的部件中，且在該多個[Bright J. Summary of the Invention This Summary is provided to introduce a concept in a simplified form and will be further described in the following detailed description. This summary does not necessarily identify key features or key features of the claimed subject matter, and is intended to be used as an aid in determining the scope of the claimed subject matter. - an electronic component comprising - an integrated device and a plurality of encapsulation layers, wherein the encapsulation layer such as 201103110 comprises a metal layer of the encapsulation layer comprising a region on a surface of the component, and one of the encapsulation layers is a metal redistribution layer Below the surface, a first track is included for directing signals from the land to other locations in the component, and an insulator edge layer on one of the encapsulation layers is interposed between the metal surface layer and the metal redistribution Between the layers, a channel passes through the upper insulating layer to connect the land to the track in the redistribution layer, and a second track is disposed in the redistribution layer A gap between a track and a channel under the zone, such that the second leg does not make electrical contact with the first leg in the zone, channel or delta zone. The channel can be formed in at least two of the various components and has an insulating channel between at least two of the components, wherein the insulating channel forms a gap for arranging the second track. The member may include a plurality of sections, passages, and ages, and a plurality of tracks of the towel may be arranged to pass through the gaps in which the recordings are recorded. Also provided herein is a wafer or panel of components having at least one member as described above. There is also provided a method of defining a signal path in an electronic component comprising an integrated device and a plurality of encapsulation layers, the method comprising the steps of: defining a region in the surface metal layer of the encapsulation layer, defining a The channel is connected to the first track in the redistribution layer of the encapsulation layer, and the (iv) surface metal layer is a m-edge layer separated by a dumping distribution layer, and the channel is within the range of the channel region In the first-track, a gap is defined, and in the redistribution region, a second way is established, wherein the second track is arranged to pass through the gap. Qian Qi does not make electrical contact with the station, the passage, or the first track within the area of the district 5 201103110. A passage between the land and the first rail may be defined between at least two separate components, and an insulating channel is formed between at least two of the components for arranging the second rail Clearance. The insulating channel can be straight or non-straight. The electronic component can be a wafer level wafer scale package device, and the surface layer can be a sub-sphere metallization (UBM) layer, the connection point can be a solder ball stage area, and the integrated device can be an integrated circuit. The member may further include a lower insulating layer for isolating the redistribution layer from the integrated circuit, and having at least one channel passing through the lower insulating layer to connect one of the redistribution layers to the integrated circuit One of the pads. There is also provided a method of making an electronic component wafer or panel, as described above. The wafer or panel may comprise at least one component as described above. The features provided can be combined as desired, are readily apparent to the skilled person, and can be combined with any aspect of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the present invention will be described by way of example with reference to the following drawings in which: FIG. 1 shows a perspective view and a cross-sectional view of a prior art WLCSP device, and FIG. 2 shows the use of a The underlying metallization layer forms a joint between the rails in a redistribution layer; FIG. 3 shows the arrangement of 2〇11〇311〇 roads under the platform defined in a metallization layer under a sphere; And Fig. 4 shows a plan view and a cross-sectional view of the land shown in Fig. 3. C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention are described by way of example only. These examples represent the best way for the applicant to be aware of the best way to put the invention into practice, although they are the only way in which the month b is reached. This description states the power of the example and the sequence of steps for constructing and manipulating the example with ο μ. However, the same effect and order can be achieved by different examples. Figure 2 shows a perspective view of the RDL and UBM layer routing system, which allows the passage of the track without the need to add layers. Therefore, the density of the track can be increased without much additional cost. Channels 200' are defined between the RDL and UBM layers, and a track 202 is defined in the UBM layer to connect the channels 2, 2, 1. The UBM layer is utilized as a row layer relative to the conventional layout portion, so 0 allows the rail to pass without adding layers. Figure 3 shows a perspective view of a WLCSP device, further including a method of routing signals from rdl from the 1C to the solder ball pads in the UBM layer. The fourth drawing shows a plan view and a cross-sectional view of a region near the solder ball stage area 300. In the first example of a solder ball stage 300, the RDL 310, 311 and the channels 302, 303 are patterned into two halves, and a channel 304 is interposed between the two halves. The first half 310 of the RDL and the first half 302 of the channel operate in a conventional manner to conduct signals from the RDL track 305 to the solder ball stage 3A. The second half 303 of the channel and the second half 311 of the RDL will provide the 7 201103110 mechanical support of the solder ball stage 3〇〇, and the metal layer to the polymer and 1 (: the locking. The channel 304 It will be utilized to arrange another signal track 306 in the coffee, which allows the track to pass without the need for an additional layer. As shown in Figure 3 for the UBM stage 307, the channel and the RDL are passed through. The channel 308 is not necessarily straight, but may take the shape of the limb to accommodate the efficient placement of the track in the RDL. The path of the channel may also contribute to the mechanical properties of the UBM zone. This should be considered when selecting the route underneath the UBM zone. In prior art systems, the track 3〇9 must be routed along the zone 307, thus increasing the equivalent connectivity required. Area. The routing of Figure 3 may have advantages over those shown in Figure 2, as the system of Figure 2 leaves an exposed track in the UBM layer, which may reduce the reliance or Increasing the likelihood of a solder short circuit. In contrast, the system of Figure 3 does not increase the number of tracks in the UBM. Moreover, the system of Figure 2 requires The number of channel locations to be increased to allow the rail to pass, and the system of Figure 3 does not require any added channel locations, since the passage of the road occurs at the existing channel location. The channel under the UBM soldering station area and The road has the potential to affect the mechanical and electrical properties of the UBM station. However, a typical UBM ball table area will have a diameter of 24 〇μηι compared to a typical track width of 10 to 25 μm. The solder ball stage is small, so there is no real impact on the nature of the station. Traditional design and manufacturing techniques can be used to design and manufacture devices that utilize the routing system. The UBM zone, the channel and the RDL zone', and the track that runs through the channel 201103110 and the channel in the RDL can have electrical interactions that are taken into account in the design process using conventional techniques. Interactions can be used to provide known values of parasitic capacitance or inductance between the signal paths, for example to achieve electrical supply decoupling, or to provide the required interaction between one of the different signal paths or Coupling. The figures have shown a single redistribution layer, but multiple redistribution layers can also be utilized while still being applicable to the principles of the invention described herein. If the zone is described as a solder ball zone, then It should be understood that the summary refers to the area on the surface of the WLCSP, not the only area used for solder balls; for example, printed solder bumps or copper posts can also be used instead of the ball. Pre-formed. The above description is mainly provided by the content of WLOSP technology, but these technologies can also be applied to package other integrated devices and semiconductor ICs. For example, 'the technologies can also be applied to integrated passive devices (IPDs) , microelectromechanical systems (MEMS) devices, optical microelectromechanical systems (0MEMS) devices, display devices' and image sensing devices. In addition to wafers, this technology can also be used for electrical panels, or electronic components. Similarly, material systems such as Tauman and glass can be used. Words such as overlay or on top are used in this document unless otherwise disclosed. 'They are not intended to indicate that the component or layer will have the same extent or be located in the plan view of the wafer or panel. The same or overlapping regions, but rather the component or layer is further away from the IC when it is substantially above the surface of the device as it is closer to the surface of the device. Similarly, the words "under" and "below" are used to indicate that the component or layer is in the cross-section of Figure 9 201103110, which is more than below - its wire (10) (four) is near the κ. The polymer is provided as an example of the dielectric sound used to insulate the metal layers, but other materials as known may also be used or may be applied depending on the material system. In the above description, one is formed in ‘. An example of a η channel has been proposed 2 that the channel can also be formed in more than two components, and in the plurality

°(Μ牛之間可有一個以上的絕緣槽道。+ ; A 9道—或更多的執路可被 辦5 又穿過該一個以上的絕緣槽道。 申請人於此乃分別_露每—所述的個別特徵及二戍 更夕該等舰的任何組合，達财基於—熟習簡術之人 4的一般普通常離據本說明書之整使料特徵或 、'且合能夠被實現的程度，㈣該等特徵或特徵的組合是否 解決任何所揭的問題，且沒有限制所請求的範圍。申請人 不出本發明的態樣可由任何該等個別的特徵或特徵的^ 來構成。參見以上描述將可賴習該技術者證明各種修正 亦可在本發明的範圍内被完成。 任何於此所提供的範圍或裝置值係可被延展或改變而 不喪失所求的效果，此乃為專業人士顯而易知。 “ 2請瞭解上述的效益和優點等可能有__實施例或 若干貫施例。該等實施例並不限於它們會解決任何或全部 的所述問題，或它們具有任何或全部的所述效益和優點。 任何述及“一 ’’物品係指一或更多個該等物品。該“包 3之同語係在此用來意指包括該等方法的方塊或明示的 元件但8亥等方塊或元件並不包含任何排它的列表，且一 201103110 方法或裝置可含有添加的方塊或元件。 於此所述方法的步驟係可以任何適當的次序來被完 成，或者需要亦可同時地進行。 應請瞭解於上一較佳實施例的描述係僅藉舉例來說 明，而各種修正亦可被專業人士作成。 雖各種不同實施例已被以一定詳細程度，或參照一或 更多個別的實施例來描述於上，但精習於該技術者應能對 該等所揭實施例作成許多改變而不超出本發明的精神或範 圍。 【圖式簡單說明3 第1圖示出一習知技術的WLCSP裝置之透視圖和截面 圖， 第2圖示出使用一球體下金屬化層來形成一重分布層 中的軌路之間的連結物； 第3圖示出界定於一球體下金屬化層中之台區底下軌 路的排設；及 第4圖示出一被示於第3圖中的台區之平面圖和截面圖。 【主要元件符號說明】 101，307...UBM台區 102…1C層 103.. .下聚合物層 104，108，200，201，302，303··.通道 105.. .接墊 106.. .重分布層(RDL) 11 201103110 107.. .上聚合物層 202，309…麟 300.. .焊球台區 304，308…槽道 305.. .RDL 軌路 306".信號執路 310，311...重分布層(RDL)° (There may be more than one insulated channel between the yak. + ; A 9 - or more roads can be handled 5 and passed through the one or more insulated channels. Applicants here are _ Each of the above-mentioned individual characteristics and any combination of these ships, the wealth is based on the general knowledge of the person who is familiar with the simple technique, usually based on the characteristics of the whole material or the combination of the instructions can be realized The extent to which the combination of features or features solves any of the disclosed problems and does not limit the scope of the invention. The Applicant's aspects of the invention may be constructed by any such individual feature or feature. The above description will be apparent to those skilled in the art that various modifications can be made within the scope of the invention. Any range or device value provided herein can be extended or changed without losing the desired effect. It is obvious to the professional. "2 Please understand that the above benefits and advantages, etc. may have __ embodiments or several embodiments. The embodiments are not limited to they solve any or all of the problems, or they Have any or all of the stated Any reference to "a" item refers to one or more of the items. The phrase "same of the package 3" is used herein to mean the element or the element that includes the method, but A block or element does not contain any exclusive list, and a 201103110 method or apparatus may contain additional blocks or elements. The steps of the methods described herein may be performed in any suitable order, or may be performed simultaneously. It should be noted that the description of the preferred embodiment has been described by way of example only, and various modifications may be made by the skilled person. Although various embodiments have been described in detail, or reference to one or more individual The embodiments are described above, but those skilled in the art should be able to make many changes to the disclosed embodiments without departing from the spirit or scope of the invention. [FIG. 1 shows a conventional example. Perspective and cross-sectional views of a technical WLCSP device, Figure 2 shows the use of a sub-metallization layer to form a bond between the tracks in a redistribution layer; Figure 3 shows the metallization defined under a sphere The arrangement of the lower rails of the Zhongzhitai District; and the fourth figure shows a plan view and a cross-sectional view of the platform shown in Fig. 3. [Key element symbol description] 101, 307... UBM station area 102 ... 1 C layer 103.. . Lower polymer layer 104, 108, 200, 201, 302, 303 · · Channel 105.. Pad 106.. Redistribution layer (RDL) 11 201103110 107.. Object layer 202, 309... Lin 300.. . solder ball table area 304, 308 ... channel 305.. . . . RDL track 306 " signal path 310, 311 ... redistribution layer (RDL)

Claims (1)

201103110 七、申請專利範圍： 1. 一種電子構件，包含一整合的裝置和多數的封裝層，該 等封裝層包含： 一該等封裝層之金屬層在該構件的表面上包含有 一台區；201103110 VII. Patent application scope: 1. An electronic component comprising an integrated device and a plurality of encapsulation layers, the encapsulation layer comprising: a metal layer of the encapsulation layer comprising a region on a surface of the component; 一該等封裝層之金屬重分布層在該表面下包含有 一第一軌路用以將信號由該台區導送至該構件中的其 它位置； 一該等封裝層之上絕緣層介於該金屬表面層與該 金屬重分布層之間； 一通道穿過該上絕緣層而將該台區連接於該重分 布層中的執路；及 一第二軌路在該重分布層中，其係被排設穿過一在 該第一軌路與該台區範圍下方之通道中的間隙，而使該 第二軌路不會與該台區、通道或該台區範圍内的第一執 路形成電接觸。 2. 如申請專利範圍第1項之構件，其中該通道係形成於至 少二各別的部件中，並有一絕緣槽道介於至少二該等部 件之間，其中該絕緣槽道會形成用以排設該第二軌路的 間隙。 3. 如申請專利範圍第1或2項之構件，包含多數的台區、通 道和軌路，其中有多數的執路被排設穿過在其它軌路和 通道中之多數個對應的間隙。 4. 如申請專利範圍第2項之構件，其中該絕緣槽道是筆直的。 13 201103110 申請專利I請第2項之構件，其中該絕緣槽道不 直的。 6.如以上中請專利範圍任—項之構件其中該構件係為一 =圓級晶収朗«置，絲面層是下金屬化 二’ 區是一焊球台區’而該整合的裝置是一積體電 路’ §亥構件更包含： 一該等封裝層之下絕緣層心隔絕該重分布層與 該積體電路，且至少古 n 、 ^ 至少有一通遏穿過該下絕緣層而將一在 «分布層中的軌路連接於該積體電路上之一接塾。 構件的晶圓或面板，包含有至少—如中請專利範圍 第1至6項之任一項所請求的構件。 8. 種在3有一整合的裝置和多數封裝層之電子構件 信號導路的方法，該方法包含以下步驟： 在該等封裝層之—表面金屬層中界定—台區； ^定―通道將該台區連接於—在該等封裝層之— 刀層中的—第—軌路，其中該表面金屬層係以一上 絕緣層來與該重分布層分開； ^通道與該台區範圍内的第—軌路中界定一間 I承，及· #、二::分布層中界定一第二軌路，其中該第二執路 穿過該_’而使其不會與該⑼、通道或該 D區乾圍_第—軌路形成電接觸。 9·如申請專利範_8項之方法，其中介於該台區與第— 軌路之間的通道係、被界定在至少二各別的部件中，並有 14 201103110 一絕緣槽道在至少二該等部件之間而形成用以排設該 第二軌路的間隙。 10. 如申請專利範圍第9項之方法，其中該絕緣槽道是筆直的。 11. 如申請專利範圍第9項之方法，其中該絕緣槽道不是筆 直的。 12. 如申請專利範圍第8至11項之任一項的方法，其中該電 子構件是一晶圓級晶片尺度封裝裝置，該表面層是一球 體下金屬化(UBM)層，該連接點是一焊球台區，而該整 合的裝置是一積體電路；該構件更包含： 一下絕緣層用以隔絕該重分布層與該積體電路，並 有至少一通道穿過該下絕緣層而將一在該重分布層中 的軌路連接於該積體電路上之一接墊。 13. —種製造電子構件之晶圓或面板的方法，乃包含一如申 請專利範圍第8至12項之任一項所請求的方法。 14. 一種製造電子構件之晶圓或面板的方法，其中該晶圓或 面板包含至少一如申請專利範圍第1至6項之任一項所 請求的構件。 15a metal redistribution layer of the encapsulation layer includes a first track under the surface for directing signals from the mesa to other locations in the component; an insulating layer over the encapsulation layer Between the metal surface layer and the metal redistribution layer; a passage through the upper insulation layer to connect the land to the redistribution layer; and a second track in the redistribution layer Is arranged to pass through a gap in the passage between the first rail and the sub-area, so that the second rail does not with the station, the channel or the first in the range of the station The road forms an electrical contact. 2. The component of claim 1, wherein the channel is formed in at least two separate components, and an insulating channel is interposed between at least two of the components, wherein the insulating channel is formed for The gap of the second rail is arranged. 3. If the component of claim 1 or 2 of the patent application contains a majority of stations, passages and tracks, a majority of the roads are routed through a corresponding number of gaps in the other tracks and channels. 4. The component of claim 2, wherein the insulating channel is straight. 13 201103110 Patent application I, please refer to item 2, where the insulation channel is not straight. 6. As in the above, please refer to the patent scope of the component, wherein the component is a = round-level crystal collection, the silk layer is the lower metallization, the second zone is a solder ball zone, and the integrated device is An integrated circuit ' § hai component further comprises: an insulating layer under the encapsulation layer isolating the redistribution layer from the integrated circuit, and at least one of n, ^ at least one passivation passes through the lower insulating layer A rail in the «distribution layer is connected to one of the contacts on the integrated circuit. The wafer or panel of the component comprises at least the components as claimed in any one of claims 1 to 6. 8. A method for signal routing of an electronic component having an integrated device and a plurality of encapsulation layers, the method comprising the steps of: defining a region in a surface metal layer of the encapsulation layer; The mesa is connected to the -th track in the layer of the encapsulation layer, wherein the surface metal layer is separated from the redistribution layer by an upper insulating layer; ^ the channel and the area within the mesa Defining an I bearing in the first-track, and · #, two:: a second track is defined in the distribution layer, wherein the second road passes through the _' so that it does not interact with the (9), the channel or The D-area _first-track forms electrical contact. 9. The method of applying the patent _8, wherein the channel between the station and the first track is defined in at least two separate components, and has 14 201103110 an insulating channel at least A gap is formed between the components to dispose the second rail. 10. The method of claim 9, wherein the insulating channel is straight. 11. The method of claim 9, wherein the insulating channel is not straight. 12. The method of any one of clauses 8 to 11, wherein the electronic component is a wafer level wafer scale package device, the surface layer being a sub-spherical metallization (UBM) layer, the connection point being a solder ball stage, and the integrated device is an integrated circuit; the component further comprises: a lower insulating layer for isolating the redistribution layer from the integrated circuit, and having at least one channel passing through the lower insulating layer A track in the redistribution layer is connected to one of the pads on the integrated circuit. 13. A method of fabricating a wafer or panel of an electronic component, comprising the method as claimed in any one of claims 8 to 12. 14. A method of making a wafer or panel of an electronic component, wherein the wafer or panel comprises at least one component as claimed in any one of claims 1 to 6. 15
TW098124713A 2009-07-07 2009-07-22 Under land routing TWI487078B (en)

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US7122458B2 (en) * 2004-07-22 2006-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating pad redistribution layer
US7262121B2 (en) * 2004-07-29 2007-08-28 Micron Technology, Inc. Integrated circuit and methods of redistributing bondpad locations
US7646087B2 (en) * 2005-04-18 2010-01-12 Mediatek Inc. Multiple-dies semiconductor device with redistributed layer pads
US7622309B2 (en) * 2005-06-28 2009-11-24 Freescale Semiconductor, Inc. Mechanical integrity evaluation of low-k devices with bump shear
US7531903B2 (en) * 2005-09-02 2009-05-12 United Microelectronics Corp. Interconnection structure used in a pad region of a semiconductor substrate
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
US20080083980A1 (en) * 2006-10-06 2008-04-10 Advanced Chip Engineering Technology Inc. Cmos image sensor chip scale package with die receiving through-hole and method of the same
US20080157303A1 (en) * 2006-12-28 2008-07-03 Advanced Chip Engineering Technology Inc. Structure of super thin chip scale package and method of the same

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