TW201101731A - Methods and apparatus for data transmission based on signal priority and channel reliability - Google Patents
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201101731 、發明說明： 【發明所屬之技術領域】 相關於一種資料傳輸’係關於一種於多重通道 (multi-channel)通訊系統中的資料傳輸之資料處理。 【先前技術】 多重通道通訊系統係能夠在傳送端以及接收端之 間傳送資訊（像是音訊和資料等）的無線通訊系統’其 中傳送端以及接收端各可具有至少一根傳送端天線以 及一根接收端天線。例如，多重通道通訊系統可包括 一多重輪入多重輸出（multiple-input multiple-output ’ 簡稱ΜΙΜΟ)通訊系統，一正交分頻多工（Orthogonal Frequency Division Multiplexing ’ 簡稱 OFDM)系統及/ 或一基於正交分頻多工的多重輸入多重輸出系統。一 多重輸入多重輸出系統使用複數個傳送端天線以及複 數個接收端天線以利用空間分集（spatial diversity)方 式形成複數個空間子通遒(subchannel)，其中使用每一 個子通道可用以傳送資料。而一正交分頻多工系統則 將一操作頻帶分成複數個頻率子通道，每一頻率子通 道即為可傳送調變資料的各子載波。因此，多重通道 通訊系統可支援複數個傳輸通道，而各傳輸通道可對 應到多重輸入多重輸出系統中的一空間子通道、正交 分頻多工系統中的一頻率子通道、或是使用正交分頻 201101731 多工機制的多重輸入多重輸出系統中之頻率子通道的 空間子通道。 於多重通道通訊系統中，傳輸通道會因為不同的 衰減以及多路徑效應而形成了不同的通道情況，故形 成了 不同的訊號對干擾加雜訊比 (signal-to-interference-plus-noise ratio 5 簡稱 SINR)。 因此，傳輸通道所能提供的傳輸容量（像是資訊位元速 _ 率（information bit rates))因不同通道而有所不同。此 〇 外，通道狀況常會隨時間/頻率而改變。因此，傳輸通 道所能提供的位元速率亦隨著變化的通道情況以及可 靠度而改變。就此而言，一經歷了較差的通訊通道的 單一通道通常會限制多重通道的總體傳輸速率。而對 操縱有關通訊資料之應用而言則會造成傳輸速率變 慢，並且使用者亦會感受到傳輸速度變慢。 Q 【發明内容】 在此所描述的示範方法以及示範裝置係根據訊號 先權值以及訊號/通道可靠度來提供資料的傳輸。揭露 之部分實施例可能指出複數個通道中的哪一通道具有 較高的可靠度，並且根據通道可靠度來分配較重要的 資料位元至資料串流中的位元位置。除此之外，揭露 之部分實施例並可能選擇性地分配較重要的資料位元 至已調變資料符元中的較高訊號先權值的位置以提升 相關訊息成功傳輸的機率。 5 201101731 根據部分實施例，可首先，將被傳送的訊息位元 編碼以產生系統位元以及同位位元。這裡所適用的， 系統位元係為描述被輸入至編碼器的資訊位元之資料 的編碼位元，並且在成功的通訊中其地位係比較重要 的。同位位元則為編碼的錯誤更正或錯誤確認位元， 並且在成功的通訊中是比較不重要的。一實施例分配 系統位元以及同位位元至對應多重通道系統中的複數 個通道的資料串流中以增加通訊呑吐率以及整體可靠 度。 在此描述了許多實施例，提供一種根據訊號先權 值和通道可靠度之資料傳輸的方法範例。所示範的方 法包括將複數個位元編碼為具有複數個系統位元以及 其各自對應的複數個同位位元的編碼位元，為了透過 一多重通道通訊系統的複數個通道來傳輸資料故將上 述位元編碼，其中上述多重通道通訊系統包括了一較 高可靠度通道以及一較低可靠度通道。所示範的方法 更包括分配上述系統位元以及上述同位位元至對應於 上述較高可靠度通道之一第一串流的各位元位置中， 或對應於上述較低可靠度通道之一第二串流的各位元 位置中。配置上述系統位元以及上述同位位元之步驟 可包括分配至少若干的上述系統位元至上述第一串流 的位元位置、分配至少若干所剩下的上述系統位元至 上述第二串流中具有一較高訊號先權值的位元位置、 以及分配至少若干的上述同位位元至第上述二串流中 201101731 所剩下的可用位元位置。 另一實施例係為根據訊號先權值和通道可靠度之 資料傳輸的一種裝置。根據有些實施例，上述裝置更 包括一編碼器以及一位元對應器。上述編碼器，用以 將複數個位元編碼為具有系統位元以及各對應的同位 位元之編碼位元，由於透過一多重通道通訊系統的複 數個通道來傳輸資料故將上述位元編碼，其中上述多 重通道通訊系統包括了一較高可靠度通道以及一較低 可靠度通道。上述位元對應器，用以分配上述系統位 元以及上述同位位元至對應於上述較高可靠度通道之 一第一串流的各位元位置中，或對應於上述較低可靠 度通道之一第二串流的各位元位置中。配置上述系統 位元以及上述同位位元之步驟包括分配至少若干的上 述系統位元至上述第一串流的位元位置、分配至少若 干的上述系統位元至上述第一串流的位元位置包括分 配至少若干的上述系統位元至上述第一串流具有較高 訊號先權值的位元位置中。上述位元對應器更用以分 配至少若干位於上述第一串流中的上述系統位元有關 的上述同位位元至上述第二串流中的位元位置中。 另一實施例係為根據訊號先權值和通道可靠度之 貢料傳輸的·—種電腦程式產品。上述電腦程式產品包 括至少一具有内存複數個可執行計算機可讀取程式碼 指令的一計算機可讀取儲存媒體，上述計算機可讀取 儲存媒體的計算機可讀取程式碼指令用以產生一裝置 201101731 來執行將複數個位元編碼為具有複數個系統位元以及 其各自對應的複數個同位位元的編碼位元，為了透過 一多重通道通訊系統的複數個通道傳輸資料故將上述 位元編碼，其中上述多重通道通訊系統包括了 一較高 可靠度通道以及一較低可靠度通道。計算機可讀取程 式碼指令以可產生一裝置用來分配上述系統位元以及 上述同位位元至對應於上述較高可靠度通道之一第一 串流的各位元位置中，或對應於上述較低可靠度通道 之一第二串流的各位元位置中。配置上述系統位元以 及上述同位位元之步驟包括分配至少若干的上述系統 位元至上述第一串流的位元位置、分配至少若干的上 述系統位元至上述第一串流的位元位置包括分配至少 若干的上述系統位元至上述第一串流具有較高訊號先 權值的位元位置中。上述計算機可讀取程式碼指令更 可產生一裝置用來執行分配至少若干位於上述第一串 流中的上述系統位元有關的上述同位位元至上述第二 串流中的位元位置中。 【實施方式】 揭露的實施例係伴隨著圖示說明，但有些情況 下，可能的實施例並未表示於圖示中。在可能情況下， 圖示中相同之元件編號係代表相同或類似之部分。在 此所使用有關於「資料」、「内容」、「資訊」以及 相似的詞語可交互使用以表示可根據所揭露實施例而 201101731 被傳送、接收及/或儲存之資料。 如上述所提及的，-多重輸入多重輸出(MIM0) 技術係應用在傳送端和接收端的複數個天線上以達到 同步傳送複數個個獨立資料串流(data streams)來增加 傳輸速率。根據上述原則的技術被採用在與已詳細制 定於1EEE 802.16e標準的多重輸入多重輸出模式所結 合的第四代無線通訊標準中。不論此特定技術，多重 0 輸入多重輸出傳輸的架構係基於一單碼字（single codeword，簡稱SCW)結構或一多碼字（multiple codeword，簡稱 MCW)結構。 針對單碼字結構，此架構包括單一組調變階層 (modulation order)以及編碼速率（coding rate)的一調變 及編碼機制（modulation and coding scheme，簡稱 MCS) 於傳送端使用。換句話說，多碼字結構則使用複數組 的調變及編碼機制（例如，兩組）。根據上述兩者技術 Q 之一者，適用在傳送端的有些參數，例如調變階層和 編碼速率，將被用以改善傳輸效能。由於多碼字（MCW) 具有更多能有效修改的參數，故多碼字比單碼字傳輸 架構能提供更多的效能增益（performance gain)。然 而，此一架構可能會需要額外的回授訊號量（feedback overhead)，這樣的情況則會導致降低總頻寬效益 (spectral efficiency) ° 第1圖係顯示在具有預編碼(precoding)使用下， 基於單碼字傳輸架構的空間多工多重輸入多重輸出 9 201101731 (SCW-based spatial multiplexing ΜΙΜΟ)的傳送端方塊 圖。傳送端包括一編碼器（encoder)126，一通道交錯器 (channel interleaver) 128 ，一速率匹配器（rate matcher) 130，一符元對應器（symbol mapper) 132，一碼 字對串流對應器（codeword(CW)-to-stream mapper)134，與複數個天線埠（antenna port)連結的一 預編碼器（precoder) 136 ，以及一控制器 (controller)138。編碼器126接收位元串流中含有資訊 位元124的碼字區塊(code block)。接著，編碼器126 根據一編碼機制來編碼所接收的資訊位元124，例 如’利用具有結尾位元新增(tail bit addition)的1/3碼 率渦輪碼（1/3-rate turbo code, TC)。 涡輪碼（TC)或迴旋渴輪碼（convolutional turbo code，簡稱CTC)使用一雙倍二進位環狀遞迴系統迴旋 碼（double binary circular recursive systematic convolutional code ’ 簡稱 double binary CRSC code)， 如第2圖中所表示的。第2圖係描述更具體化的編碼 器126之圖示。首先’透過迴旋渦輪碼將複數個輸入 資訊位元(A，B)編碼為複數個系統位元(a，b)以及複數 個同位位元(Y1，Y2,Wl，W2)。每一系統位元與至少對 應若干同位位元。同位位元係用於其對應的系統位元 之錯誤偵測或修正。同位位元Υ1和W1係透過組成 編碼器（constituent encoder) 102所產生的，而同位位元 Y2和W2則係透過迴旋渴輪碼交錯琴（ctc 10 201101731 interleaver) 100以及組成編碼器104所產生的。 經編碼後，透過通道交錯器將編碼位元的複數個 子區塊交錯放置以避免在特別通道上叢集種類的通訊 錯誤發生。關於第3圖，複數個位元的每個子區塊， 例如，A子區塊108、B子區塊110、Y1子區塊112、 Y2子區塊114、W1子區塊116、W2子區塊118，透 過子區塊交錯器120重新排列（route)位元順序以產生 ^ 一交錯碼序列122。 於交錯處理之後，包括了系統位元部份以及同位 位元部份的交錯碼序列122會經過剔除(puncture)的動 作以符合速率匹配器130所希望的編碼速率。經過剔 除的動作後，符元對應器132將編碼位元調變為複數 符元(complex-valued symbol)，其中複數符元即為具有 實部以及虛部的符元。透過碼字對串流對應器134對 調變符元由一單一序列轉換為多重傳輸串流。例如， 〇 使用一基於資料循環放置方式的碼字對串流對應器 (circulation-based CW-to-stream mapper)。接著，在預 編碼器13 6中根據一預先設計的(pre-designed)預編碼 矩陣將串流進行預編碼，並且由複數個個天線傳送出 去。圖4a、4b以及4c係顯示碼字對串流對應器134 將一單一編碼、調變的符元序列各轉換為2、3以及4 個串流之圖示。上述編瑪速率、調變階層、傳輸資料 串流的數量以及預編碼矩陣皆由控制器138所調整， 用以修正上述組合的傳輸。 201101731 第5a圖係顯示基於單碼字的空間多工多重輸入 多重輸出的資料處理之範例，其中資訊位元的數量L 為48 ’並採用Ιό正交振幅調變（16_qam)，碼率 2/3’以及攀流的數量上為2。於此例中，首先利用U3 碼率的迴㈣輪碼將資訊位元_，接著，經過位元 交錯以及剔除的程序以符合2/3的碼率。因此，編碼 位το序列中包括了 48 _系統位元以及經過剔除的動 作之後所剩的24個當作同位位元的編碼位元。在編碼 位7L序列中同位位元接續在純位元之後。經過剔除 程序之後，透過符元對應器132將編碼位元對應至符 兀中。由於是利用16正交振幅調變機制，故每四個編 碼位元被分成一群對應至一個複數調變符元中。 每符元具有關聯係的位元位置，其中有些位元位 置具有較高訊號先權值的位元位置（例如：符號位元 (sign bit))，有些位元位置具有較低訊號先權值的位元 位置（例如：非符號位元(non-sign bit))。第5a圖中有底 線的位元即表示一個複數調變符元的符號位元，而複 數调變符元的符號位元係用來表示一複數調變符元的 實數(real value)和虛數(image value)。由於符元的結 構’符號位元比非符號位元具有更高的訊號先權值。 一般而言，一複數調變符元係由多數個編碼位元所構 成的。例如’兩個位元構成一正交相位鍵移（QPSK)符 元、四個位元構成一 16正交振幅調變（i6_QAM；)符元 以及六個位元構成一 64正交振幅調變（64-QAM)符 12 201101731 兀。任意符元中的其中兩個位元用以表示一正交振幅 調變(QAM)符元的實數(例如，同相）部分以及虛數(例 如’正交)部分’亦即符號位元。f 5b以及&圖係顧 示16正交振幅調變的編碼之星座圖，其中第一位元和 第三位元分別代表實部以及虛部的符號。如第5b 5c圖所顯示的’改變第一位元和第三位元即分別代表 星座圖中某不同半部，（亦即，第-位元為i時的符 〇 力皆發生在星座®中的左半部，第-位it為G時的符 元皆發生在星座圖中的右半部；以及第三位元 的符元皆發生在星座圖中的上半部，第三位元為i時 的符元則皆發生在星座圖中的下半部）。在符元傳輸 的期間，傳送位元通常會位於解調變區域的相同半部 或象限中。由此可知，相較於並非定義一半部或一象 限的位元來說，決定一半部或象限之位元具有相對低 #錯誤率。因此’這些位元具有較高的訊號先權值， U ^在傳輸中係為更重要的位元。基於這種特性，因 可靠度的考量’較為重要的編碼位元(例如系統位元） 將分配至-複數調變符元中的符號位元的位置。 再二人使用與第5a圖相同的範例，將全部的個 編碼位元對應至18個16正交振幅調變（16_QAM)符 Ά據範例所顯示的，可了解有些系統位元被分配 至，數調變符元的非符號位元。最後，碼字對串流對 應器134將上述18個正交振幅調變符元平均地分配至 兩個傳輸串流中，並且經由兩個實際的通道傳送。如 201101731 第5a圖之箭頭方向，將系統位元以及對應的同位位元 分配至相同的通道中。基於上述的討論，假設其中一 通道比另一個通道具有較好且更可靠的傳輸品質。然 而，根據此範例圖示來說，通道將對位元配置呈現相 同處理。在這例子中，由於碼率i?為2/3的關係，有 些系統位元將配置於較不可靠的通道中。 第6圖係顯示在具有預編碼(precoding)架構下， 基於多碼字的空間多工多重輸入多重輸出 (MCW-based spatial multiplexing ΜΙΜΟ)之傳送端的 方塊圖。傳送端包括一切割器（splitter) 140，一編瑪器 142 ’ 一通道交錯器144，一速率匹配器146，一調變 器148，一碼字對串流對應器150，與複數個天線埠連 結的一預編碼器152 ’以及一控制器154。針對基於多 碼字結構，控制器154根據通道情形來調整複數個調 變及編碼機制。與上面所描述的單碼字結構相比，由 於通道的變化須調整更多的參數以提供改善鏈路效能 (link performance)。然而，可更改參數之數量增加會 造成回授訊號量的需求增加。因此，基本上多碼字結 構的資料處理方式類似於單碼字結構，唯多碼字結構 係基於複數個碼字同時進行處理。第7a以及7b圖係 顯示碼字對串流對應器150與預編碼器 152如何操作 之示思圖。就這點而言，第7a以及7b圖說明碼字對 串流對應器150如何將兩個編碼調變符元序列各轉換 為3個或4個串流的情況。 14 201101731201101731, invention description: [Technical field to which the invention pertains] relates to data processing of a data transmission in a multi-channel communication system. [Prior Art] A multi-channel communication system is a wireless communication system capable of transmitting information (such as audio and data) between a transmitting end and a receiving end, wherein each of the transmitting end and the receiving end may have at least one transmitting end antenna and one Root receiver antenna. For example, the multi-channel communication system may include a multiple-input multiple-output (referred to as ΜΙΜΟ) communication system, an Orthogonal Frequency Division Multiplexing (OFDM) system and/or a Multiple input multiple output system based on orthogonal frequency division multiplexing. A multiple input multiple output system uses a plurality of transmit antennas and a plurality of receive antennas to form a plurality of spatial subchannels using spatial diversity, wherein each subchannel is used to transmit data. An orthogonal frequency division multiplexing system divides an operating frequency band into a plurality of frequency sub-channels, and each frequency sub-channel is a sub-carrier capable of transmitting modulated data. Therefore, the multi-channel communication system can support a plurality of transmission channels, and each transmission channel can correspond to a spatial sub-channel in a multiple input multiple output system, a frequency sub-channel in an orthogonal frequency division multiplexing system, or use positive Cross-frequency 201101731 The spatial sub-channel of the frequency sub-channel in the multiple input multiple output system of the multiplex mechanism. In the multi-channel communication system, the transmission channel will form different channel conditions due to different attenuation and multipath effects, thus forming different signal-to-interference-plus-noise ratio 5 (signal-to-interference-plus-noise ratio 5 Referred to as SINR). Therefore, the transmission capacity (such as information bit rates) that the transmission channel can provide varies from channel to channel. In addition to this, channel conditions often change with time/frequency. Therefore, the bit rate that the transmission channel can provide also varies with varying channel conditions and reliability. In this regard, a single channel that has experienced a poor communication channel typically limits the overall transmission rate of multiple channels. For applications that manipulate communication data, the transmission rate will be slower and the user will experience slower transmission speeds. Q [Disclosed Summary] The exemplary methods and exemplary devices described herein provide for the transmission of data based on signal pre-weights and signal/channel reliability. Some of the disclosed embodiments may indicate which of the plurality of channels has higher reliability and assign more important data bits to the bit positions in the data stream based on channel reliability. In addition, some embodiments of the disclosure may selectively allocate more significant data bits to higher signal pre-weighted locations in the modulated data symbols to increase the probability of successful transmission of related information. 5 201101731 According to some embodiments, the transmitted message bits may first be encoded to generate system bits and parity bits. As used herein, a system bit is a coded bit that describes the data of the information bits that are input to the encoder, and its status is important in successful communications. The parity bit is the coded error correction or error acknowledgement bit and is less important in successful communication. An embodiment allocates system bits and parity bits to a data stream of a plurality of channels in a corresponding multi-channel system to increase communication throughput and overall reliability. Many embodiments are described herein that provide an example of a method of data transmission based on signal pre-weight and channel reliability. The exemplary method includes encoding a plurality of bits into coded bits having a plurality of system bits and their respective corresponding plurality of parity bits, in order to transmit data through a plurality of channels of a multi-channel communication system. The above bit coding, wherein the multi-channel communication system comprises a higher reliability channel and a lower reliability channel. The exemplary method further includes allocating the system bit and the co-located bit to a bit position corresponding to the first stream of one of the higher reliability channels, or corresponding to one of the lower reliability channels. The stream is in the meta-location. The step of configuring the system bit and the co-located bit may include allocating at least a plurality of the system bits to a bit position of the first stream, and allocating at least a plurality of remaining system bits to the second stream a bit position having a higher signal first weight, and assigning at least some of the above-mentioned parity bits to the remaining bit positions remaining in 201101731 of the second stream. Another embodiment is a device for transmitting data based on signal pre-weight and channel reliability. According to some embodiments, the apparatus further includes an encoder and a one-bit counterpart. The encoder is configured to encode a plurality of bits into coded bits having system bits and corresponding co-located bits. The bits are encoded by transmitting data through a plurality of channels of a multi-channel communication system. The multi-channel communication system includes a higher reliability channel and a lower reliability channel. The bit corresponding device is configured to allocate the system bit and the co-located bit to a bit position corresponding to the first stream of one of the higher reliability channels, or to one of the lower reliability channels In the position of each element of the second stream. The step of configuring the system bit and the co-located bit includes assigning at least a plurality of the system bits to a bit position of the first stream, and allocating at least a plurality of the system bits to a bit position of the first stream The method includes allocating at least a plurality of the system bits to a bit position of the first stream having a higher signal pre-weight. The bit correlator is further configured to allocate at least a plurality of the parity bits associated with the system bit located in the first stream to a bit position in the second stream. Another embodiment is a computer program product that is transmitted based on the weight of the signal and the reliability of the channel. The computer program product comprises at least one computer readable storage medium having a plurality of executable computer readable code instructions, wherein the computer readable storage computer readable program code instructions are used to generate a device 201101731 Encoding a plurality of bits into coded bits having a plurality of system bits and respective corresponding plurality of parity bits, wherein the bits are encoded in order to transmit data through a plurality of channels of a multi-channel communication system The multi-channel communication system includes a higher reliability channel and a lower reliability channel. The computer readable program code instructions to generate a means for assigning the system bit and the co-located bit to a bit position corresponding to the first stream of one of the higher reliability channels, or corresponding to the comparison One of the low reliability channels is in the position of each of the second streams. The step of configuring the system bit and the co-located bit includes assigning at least a plurality of the system bits to a bit position of the first stream, and allocating at least a plurality of the system bits to a bit position of the first stream The method includes allocating at least a plurality of the system bits to a bit position of the first stream having a higher signal pre-weight. The computer readable code instructions further generate means for performing the allocation of at least a plurality of the parity bits associated with the system bits in the first stream to the bit locations in the second stream. [Embodiment] The disclosed embodiments are accompanied by the illustrations, but in some cases, possible embodiments are not shown in the drawings. Wherever possible, the same element numbers in the figures represent the same or similar parts. As used herein, the terms "data," "content," "information," and similar terms may be used interchangeably to refer to information that can be transmitted, received, and/or stored in accordance with the disclosed embodiments. As mentioned above, the Multiple Input Multiple Output (MIM0) technique is applied to a plurality of antennas at the transmitting and receiving ends to simultaneously transmit a plurality of independent data streams to increase the transmission rate. The technique according to the above principles is adopted in the fourth generation wireless communication standard combined with the multiple input multiple output mode which has been specifically defined in the 1EEE 802.16e standard. Regardless of this particular technique, the architecture of multiple 0-input multiple-output transmissions is based on a single codeword (SCW) structure or a multiple codeword (MCW) structure. For a single codeword structure, this architecture includes a single set of modulation orders and a modulation rate coding and coding scheme (MCS) for use at the transmitting end. In other words, multi-codeword structures use complex array modulation and encoding mechanisms (for example, two groups). According to one of the above two techniques Q, some parameters applied to the transmitting end, such as the modulation level and the coding rate, will be used to improve the transmission performance. Since multi-codewords (MCW) have more parameters that can be effectively modified, multi-codewords provide more performance gain than single-wordword transmission architectures. However, this architecture may require additional feedback overhead, which leads to a reduction in the overall spectrum efficiency. Figure 1 shows the use of precoding. Space multiplex multiple input multiple output based on single code word transmission architecture 9 201101731 (SCW-based spatial multiplexing ΜΙΜΟ) transmission terminal block diagram. The transmitting end includes an encoder 126, a channel interleaver 128, a rate matcher 130, a symbol mapper 132, and a codeword pair stream counterpart. (codeword (CW)-to-stream mapper) 134, a precoder 136 coupled to a plurality of antenna ports, and a controller 138. Encoder 126 receives a code block containing information bits 124 in the bit stream. Encoder 126 then encodes the received information bits 124 according to an encoding mechanism, such as 'using a 1/3 rate turbo code with tail bit addition (1/3-rate turbo code, TC). Turbo code (TC) or convolutional turbo code (CTC) uses a double binary circular recursive systematic convolutional code (referred to as double binary CRSC code), such as 2 is shown in the figure. Figure 2 is a diagram depicting a more specific encoder 126. First, a plurality of input information bits (A, B) are encoded into a plurality of system bits (a, b) and a plurality of parity bits (Y1, Y2, W1, W2) through the swirling turbo code. Each system bit corresponds to at least a number of co-located bits. The parity bit is used for error detection or correction of its corresponding system bit. The parity bits 和1 and W1 are generated by a constituent encoder 102, and the parity bits Y2 and W2 are generated by the cyclotron code interlace (ctc 10 201101731 interleaver) 100 and the encoder 104. of. After encoding, the plurality of sub-blocks of the coded bits are interleaved by the channel interleaver to avoid communication errors of the cluster type on the special channel. Regarding FIG. 3, each sub-block of a plurality of bits, for example, A sub-block 108, B sub-block 110, Y1 sub-block 112, Y2 sub-block 114, W1 sub-block 116, W2 sub-area Block 118, routing the bit order through sub-block interleaver 120 to generate an interleaved code sequence 122. After the interleaving process, the interleaved code sequence 122 including the systematic bit portion and the parity portion is subjected to a puncture to conform to the encoding rate desired by the rate matcher 130. After the culled action, the symbol counterpart 132 converts the encoded bit into a complex-valued symbol, where the complex symbol is a symbol having a real part and an imaginary part. The modulated symbols are converted from a single sequence to a multiple transmitted stream by a codeword pair stream counterpart 134. For example, 〇 use a data-based loop-based CW-to-stream mapper. Next, the stream is precoded in a pre-encoder 13 6 according to a pre-designed precoding matrix and transmitted by a plurality of antennas. Figures 4a, 4b, and 4c show graphical representations of the stream-to-stream counterpart 134 converting a single encoded, modulated symbol sequence into 2, 3, and 4 streams, respectively. The above-mentioned marsh rate, modulation level, number of transmission data streams, and precoding matrix are all adjusted by the controller 138 to correct the transmission of the above combination. 201101731 Figure 5a shows an example of data processing based on single codeword spatial multiplex multiple input multiple output, where the number L of information bits is 48 ' and uses Ιό quadrature amplitude modulation (16_qam), code rate 2/ 3' and the number of climbs is 2. In this example, the information bit _ is first used by the back (four) round code of the U3 code rate, and then the bit interleaving and culling procedure is performed to meet the code rate of 2/3. Therefore, the coded bit το sequence includes 48 _ system bits and 24 remaining coded bits that are quaternary bits after the culled action. The co-bits in the sequence of coded bits 7L are followed by a pure bit. After the culling procedure, the symbol bit is mapped to the symbol by the symbol counterpart 132. Since the 16-quadrature amplitude modulation mechanism is utilized, every four coded bits are divided into a group corresponding to a complex modulation symbol. Each symbol has a connected bit position, some of which have a higher signal first bit position (eg, a sign bit), and some bit positions have a lower signal first value Bit position (for example: non-sign bit). The bit line with the bottom line in Fig. 5a represents the sign bit of a complex modulating symbol, and the sign bit of the complex modulating symbol is used to represent the real value and imaginary number of a complex modulating symbol. (image value). Since the symbol's structure' sign bit has a higher signal pre-weight than the non-symbol bit. In general, a complex modulator is composed of a plurality of coded bits. For example, 'two bits form a quadrature phase key shift (QPSK) symbol, four bits form a 16 orthogonal amplitude modulation (i6_QAM;) symbol and six bits form a 64 quadrature amplitude modulation (64-QAM) symbol 12 201101731 兀. Two of the bits in any symbol are used to represent a real (e.g., in-phase) portion of a quadrature amplitude modulation (QAM) symbol and an imaginary (e.g., 'orthogonal) portion', i.e., a sign bit. The f 5b and & graphs represent a 16 constellation of orthogonal amplitude modulation codes in which the first and third bits represent the real and imaginary symbols, respectively. As shown in Figure 5b 5c, 'changing the first and third bits represents a different half of the constellation, respectively (that is, the sign of the first bit is i in the constellation®) In the left half of the middle, the symbols when the first-bit it is G occur in the right half of the constellation; and the symbols of the third-bit all occur in the upper half of the constellation, the third bit The symbols for i are all in the lower half of the constellation. During a symbol transfer, the transfer bit is typically located in the same half or quadrant of the demodulation region. It can be seen that the bit that determines half or quadrant has a relatively low # error rate compared to a bit that does not define a half or a quadrant. Therefore, these bits have higher signal-first weights, and U^ is a more important bit in transmission. Based on this characteristic, the more important coding bits (e.g., system bits) due to reliability considerations will be assigned to the locations of the sign bits in the - complex modulation symbols. The second person uses the same example as in Figure 5a to map all the coding bits to 18 16-quadrature amplitude modulation (16_QAM) symbols. As shown in the example, some system bits are allocated to A non-symbol bit of a numbered argument. Finally, the codeword pair stream responder 134 evenly distributes the 18 orthogonal amplitude modulation symbols described above into two transport streams and transmits them via two actual channels. For example, in the direction of the arrow in Fig. 5a of 201101731, the system bits and the corresponding parity bits are assigned to the same channel. Based on the above discussion, it is assumed that one of the channels has better and more reliable transmission quality than the other channel. However, according to this example illustration, the channel will present the same processing for the bit configuration. In this example, because the code rate i? is 2/3, some system bits will be placed in less reliable channels. Figure 6 is a block diagram showing the transmission side of a multi-codeword based spatial multiplex multiple input multiple output (MCW-based spatial multiplexing) with a precoding architecture. The transmitting end includes a splitter 140, a coder 142', a channel interleaver 144, a rate matcher 146, a modulator 148, a codeword pair stream counterpart 150, and a plurality of antennas. A precoder 152' and a controller 154 are connected. For a multi-code based structure, the controller 154 adjusts a plurality of modulation and coding mechanisms depending on the channel conditions. Compared to the single codeword structure described above, more parameters have to be adjusted due to channel variations to provide improved link performance. However, an increase in the number of changeable parameters will result in an increase in the demand for feedback signals. Therefore, basically the data processing of the multi-codeword structure is similar to the single-codeword structure, and the multi-codeword structure is processed simultaneously based on a plurality of codewords. Figures 7a and 7b show a representation of how the codeword pairs the stream counterpart 150 and the precoder 152 operate. In this regard, Figures 7a and 7b illustrate the case where the codeword pair stream counterpart 150 converts each of the two coded symbol sequences into three or four streams. 14 201101731
G 第8圖係顯示根據一實施例所述之單碼字結構。 第8圖之結構顯示了基於訊號先權值以及可靠度進行 資料分配以改善傳輸品質所使用的範例方法及/或範 例裝置之系統方塊圖。當第8圖描述出有關單碼字解 釋的同時，熟悉此技藝人士可相同地了解應用多碼字 結構之實施例。編碼器126，通道交錯器128，速率匹 配器156，碼字對串流對應器158，符元對應器160， 預編碼器136以及控制器162可以硬體或軟體方式實 現的至少一硬體裝置（例如：積體電路）。 關於第8圖，編碼器ι26、通道交錯器ι28以及 預編崎器136如上面所描述的方法進行操作。然而， 根據有些貫施例，在交錯程序之後，編碼位元將藉由 ^率匹配S 156基於期望的編碼率及訊號先權值進行 率】^速率匹配。就此而言，根據不同的實施例，速 ^ ^ ^(PUnCtUrin§ rati〇> 或剔除 162 T剔除有些同位位元，其中控制器 剔除規則Si靠度及/或位元配置來決㈣除率或 串流之系統位于1比率係指-與位於較高可靠度通道中的 通道中的串=兀有關的同位位元對與位於較低可靠度 據不同的二之系統位元有關的同位位元之比率。根 流之系統位二關位於較低可靠度通道中的串 較高可靠度的、、1的同位位兀在數量上須要比與位於 元較多的^通道中的串流之系統位元有關的同位位 、進行剔除比率設計。例如，1:2的剔除 15 201101731 比率係指，相較於較高可靠度通道中的系統位元有關 的同位位元，比相較於較低可靠度通道中的系統位元 有關的同位位元具有其兩倍數量的同位位元。 可視為一位元對應器的碼字對串流對應器158以 及符元對應器160,可根據通道的可靠度來分配系統 位元以及同位位元至不同串流中。就這點而言，經過 交錯程序之後的編碼位元首先係根據訊號可靠度來進 行剔除程序以及對應至串流中，接著，符元對應器160 再根據訊號先權值和可靠度將每個串流中的複數個位 元對應為調變符元。因此，與碼字對串流對應器134 相比，碼字對串流對應器158是以位元方式執行串流 對應，而不是以符元方式來執行。 根據不同的實施例，可基於調變符元的先權值來 執行符元對應以更改善傳輸連結品質。此外，根據不 同的實施例，可進行基於先權值的符元對應（Symbol Mapping based Priority，簡稱SMP)。根據先權值的符 元對應（SMP)，系統位元（例如：編碼序列中重要的部分) 被分配至一複數調變符元中具有高訊號先權值的位元 位置（例如：符號位元）。另外，根據不同的實施例，基 於來自接收端或其他網路實體的回傳資訊來分配系統 位元至較高可靠度通道的串流中。相較於同位位元， 因為系統位元係即為所傳送的資訊位元，系統位元在 編碼位元序列中較為重要。當在傳送端可獲得每個通 道中的訊號傳送可靠度時，分配系統位元到較可靠的 16 201101731 通道可提供一改善的傳輸鏈路品質。因此，根據不同 的實施例，盡量地配置大部分的系統位元至較高可靠 度的通道中。然而基於碼率，系統位元也有可能被配 置到較低可靠度通道中。 透過迴授信號給控制器162,使用來指示何者通 道較為可靠的資訊可能會導致增加迴授信號量。然 而，根據其他實施例，迴授信號量可被限縮至只需要 0 具體描述具有最好可靠度的通道之位元數目。根據其 他實施例，1到3個位元的迴授信號量即已足夠。在 有些實施例中，例如分別對應到各自通道的兩個資料 串流的多重輸入多重輸出系統，需要迴授1個位元信 號量（a one-bit overhead)給在一開放迴圈（open-loop)之 多重輸入多重輸出系統中的一傳送端以指出通道的品 質。若在使用凡個傳輸串流的情況下，則需l〇g2A^ 之數量的位元用已進行通道可靠度之通報中。在有些 ❹ 封閉迴圈（closed loop)系統中，在傳送端已可有效獲得 通道可靠度的資訊，故並不需要額外的迴授信號。因 此，根據結合通道可靠度以及訊號先權值來分配位元 位置可因此被用以發展一套聯合位置分配（joint allocation)來改善鏈路可靠度以及增加整體的頻譜·效 率。 根據上面所描述的，第9、11、13以及15圖係顯 示數個實施例的位元位置分配結果。值得注意的是， 雖然第9、11、13以及15圖皆有關於兩個有效的通道 17 201101731 之糸統，但上述所顯示的技術以及實施例可應、用於使 用任何通道數量的系統中。第9圖係顯示利用結合美 於訊號先權值的符元對應規則與基於訊號/通$ 度的碼字對串流對應規則來決定位元位置。 ^乐9圖 所述的，訊號資料的數量為48個，使用碼率為2/3的 16正交振幅調變，以及在每一傳輸的通道上產生兩組 資料串流。透過例如控制器162所接收的迴授传號， 來決定此二通道之可靠度程度。 & 如第9圖所述的，在編碼、交錯以及剔除裎序後， 產生編碼的系統位元和同位位元的序列。這此所產生 的編碼位元接著透過基於訊號可靠度的碼字對串流^ 應器來配置其位元放置位置。如此，系驗元可對應 到更加可靠通道中的串流，其他剩下的系統位元則放 置到較低可靠度的通道中，並輯有的同位位元都安 排至較低可靠度之通道㈣流巾。接著，根據先權值 ^符元對應(SMP)法則來執行符元對應。位於較低可 靠度通道中的串流之系統位元被分配到較低可靠度之 通道的^流中的複數符元(eGmplex_valued 裡 面的車乂同訊號先權值的位元位置中，亦即符號位元的 位置。同位位元則配置到在較低可靠度通道的串流中 較低的訊號先權值的位元位置，亦即非符號位元的位 置上。因此’這樣的操作產生了在較高可靠度通道中 裡面的，—串流皆為系統位元，以及在較低可靠度通 逼中的第二串流中較高訊號先權值位元位置皆為系統 18 201101731 位元，而在較低可靠度通道中 下的較高訊號先權值位元位 弟二串流中任何所剩 位元位置皆為同位位元。 '及在較低訊號先權值 第10圖係顯示要完成第 法的流程圖。第H)圖之 配置之示範方 通訊系統的複數個通道 2 =括透過-多重通道 中位元編竭為具有 要傳輸的位元編碼編碼，其G Figure 8 shows a single codeword structure in accordance with an embodiment. The structure of Fig. 8 shows a system block diagram of an exemplary method and/or exemplary apparatus used for data distribution based on signal prior weight and reliability for improved transmission quality. While FIG. 8 depicts an explanation of a single codeword, an embodiment of the application of a multi-codeword structure can be equally understood by those skilled in the art. The encoder 126, the channel interleaver 128, the rate matcher 156, the codeword pair stream counterpart 158, the symbol counterpart 160, the precoder 136, and the controller 162 can be implemented in hardware or software by at least one hardware device. (Example: integrated circuit). With respect to Fig. 8, encoder ι26, channel interleaver ι28, and pre-blocking 136 are operated as described above. However, according to some embodiments, after the interleaving procedure, the coding bits will be matched by the rate matching S 156 based on the desired coding rate and the signal prior weight. In this regard, according to different embodiments, the speed ^ ^ ^ (PUnCtUrin§ rati〇> or 162 T removes some of the parity bits, wherein the controller rejects the rule Si and/or the bit configuration to determine the (four) removal rate. Or the system of the stream is located at the ratio 1 - the parity of the pair of bits associated with the string located in the channel of the higher reliability channel and the parity of the system bits of the second system of the lower reliability The ratio of the element. The system of the root flow is the higher reliability of the string in the lower reliability channel, and the parity of 1 is required in comparison with the stream in the channel with more elements. The system bit is related to the parity and the rejection ratio is designed. For example, the 1:2 rejection 15 201101731 ratio refers to the parity of the system bits in the higher reliability channel. The system bit associated with the low reliability channel has twice the number of parity bits. The codeword pair stream counterpart 158 and the symbol counterpart 160, which can be regarded as a one-bit counterpart, can be based on the channel. Reliability to assign system bits and the same The bit bit is in a different stream. In this regard, the coded bit after the interleaving process first performs the culling process according to the signal reliability and corresponds to the stream, and then the symbol counterpart 160 is further based on the signal. The first weight and the reliability correspond to the plurality of bits in each stream as the modulation symbols. Therefore, the codeword pair stream counterpart 158 is a bit compared to the codeword pair stream counterpart 134. The manner of performing the stream correspondence is not performed in a symbol manner. According to different embodiments, the symbol correspondence may be performed based on the first weight of the modulation symbol to further improve the transmission link quality. Further, according to different embodiments A symbol mapping based priority (SMP) can be performed. According to the symbol-based correspondence (SMP) of the first weight, system bits (for example, important parts in the coding sequence) are assigned to one. A bit position (eg, a sign bit) having a high signal prior weight in the complex tone symbol. Additionally, according to various embodiments, system bits are allocated based on backhaul information from the receiving end or other network entity. In the stream to the higher reliability channel, compared to the parity bit, because the system bit is the transmitted information bit, the system bit is more important in the coded bit sequence. When obtaining the signal transmission reliability in each channel, assigning system bits to the more reliable 16 201101731 channel can provide an improved transmission link quality. Therefore, according to different embodiments, most of the system bits are configured as much as possible. In the higher reliability channel, however, based on the code rate, the system bit may also be configured into the lower reliability channel. By using the feedback signal to the controller 162, the information used to indicate which channel is more reliable may result in The feedback semaphore is increased. However, according to other embodiments, the feedback semaphore can be limited to only 0, specifying the number of bits of the channel with the best reliability. According to other embodiments, a feedback signal amount of 1 to 3 bits is sufficient. In some embodiments, for example, a multiple input multiple output system corresponding to two data streams of respective channels, a one-bit overhead is required to be given to an open loop (open- Loop) A transmitter in a multiple input multiple output system to indicate the quality of the channel. If any of the transport streams are used, then the number of bits of l〇g2A^ needs to be reported in the channel reliability. In some closed loop systems, channel reliability information is available on the transmit side, so no additional feedback signals are required. Therefore, assigning bit locations based on combined channel reliability and signal prior weights can therefore be used to develop a joint set of joint allocations to improve link reliability and increase overall spectrum efficiency. According to the above description, the 9, 9, 13, and 15 diagrams show the bit position assignment results of several embodiments. It is worth noting that although the figures 9, 11, 13 and 15 are all about the two effective channels 17 201101731, the techniques and embodiments shown above can be used in systems using any number of channels. . Figure 9 shows the location of the bit by using the symbol correspondence rule combined with the signal-first weight and the code-to-signal-to-stream correspondence rule based on the signal/passage. As shown in Fig. 9, the number of signal data is 48, using 16 orthogonal amplitude modulation with a bit rate of 2/3, and two sets of data streams are generated on each transmitted channel. The degree of reliability of the two channels is determined by, for example, a feedback mark received by the controller 162. & As described in Figure 9, after encoding, interleaving, and culling, a sequence of encoded system bits and parity bits is generated. The resulting coded bits then configure their bit placement by the stream-based signal-to-string processor. In this way, the system can correspond to the stream in the more reliable channel, and the other remaining system bits are placed in the channel with lower reliability, and the set of the same bits are arranged to the channel with lower reliability. (4) Flowing towels. Next, the symbol correspondence is performed according to the precedence value (SMP) rule. The system bits of the stream located in the lower reliability channel are assigned to the complex symbols in the stream of the lower reliability channel (the position of the ruling in the eGmplex_valued is the same as the first weight of the signal, ie The position of the sign bit. The co-located bit is allocated to the bit position of the lower signal first weight in the stream of the lower reliability channel, that is, the position of the non-symbol bit. Therefore, such an operation is generated. In the higher reliability channel, the -stream is the system bit, and in the second stream in the lower reliability pass, the higher signal first bit position is the system 18 201101731 bit Yuan, and any remaining bit positions in the higher signal first weight bit in the lower reliability channel are all parity bits. 'And in the lower signal first weight value 10th figure A flow chart showing the completion of the method. The plurality of channels 2 of the exemplary communication system of the configuration of the H) are included in the trans-multiple channel, and the bit coding is encoded to have the bit coding code to be transmitted.
(在步驟4〇〇中I'、、元以及同位位元的編碼位元 括-個較具有較言c通訊系統的複數個通道包 靠度的通道。在二：广的通道以及-個具有較低可 若干個系統位元配置到法包括將至少 流裡的位元位置。根可靠度的通道中的第-串 所有位元位置皆為分::二實施例;在第-串流中的 銘古土勹刀配糸統位兀。在步驟420中，示 可靠度所剩下的系統™^ 二串施例，某些或甚至是全部的第 "，L 、較鬲訊號先權值的位元位置都被分配认夸 +七入μ 驟43〇中，示範方法亦包括分配至少若 二二ί同ί位元至第二串流中所剩下可用的位元 位元勺括了些實施例中’分配至少若干或全部的同位 的St 些與位於第一串流中的系統位元有關 的同“立兀分配至第二串流中的位元位置。 阶罢^1圖係顯示根據―實施例所述之另—種位元 θυ置之^万法'。错1 1 弟11圖係使用結合剔除程序和基於訊號 19 201101731 /通道可靠度的碼字對串流對應規則以及基於訊號先 權值的符號對應規則來決定的位元配置。在第11圖中 所描述的範例，訊號資料的數量為48個，使用碼率為 2/3的16正交振幅調變，以及在每個各傳輸的通道上 各產生一組資料串流。且判斷其中哪一個通道比起另 一個通道具有較佳的可靠度。 如第11圖所述的，在編碼以及交錯程序之後，產 生編碼的系統位元以及同位位元之序列。這些所產生 的編碼位元接著透過碼字對串流對應器根據訊號可靠 度來對應其位置。如此，系統位元可對應到較高可靠 度通道的串流中。任何所剩下的系統位元則放置到較 低可靠度通道中，並且所有的同位位元都安排至較低 可靠度通道的串流中。 根據剔除比率剔除編碼序列些不需要的位元。如 此，在系統位元填滿了較高可靠度通道的位元位置之 後，決定哪些系統位元依舊被分配到較低可靠度通道 中。剔除比率之決定，係希望在剔除程序之後，與配 置在較低可靠度通道中系統位元有關的同位位元能比 與較高可靠度通道中系統位元有關的同位位元的數目 來的多。如第11圖所述，剔除比為1:2，在有些實施 例中，在剔除程序之後再根據可靠度來執行碼字對串 流對應。 依照基於先權值的符元對應（SMP)法則來執行符 元對應。如此，位於較低可靠度通道之串流中的系統 20 201101731 位元將被分配到符元裡面的較高訊號先權值的位元位 置上，亦即符號位元位置上，以及同位位元則配置到 較低可靠度通道之串流中符元裡面的較低的訊號先權 值位元位置上，亦即非符號位元位置上。因此，這樣 的操作會導致較高可靠度通道中的第一串流皆為系統 位元以及在較低可靠度通道中的第二串流具有在高訊 號先權值位元位置亦為系統位元。同位位元則被分配 0 到第二串流中具有配置系統位元之符元中較低訊號先 權值的位元位置，而所剩下的同位位元將被分配到第 二串流中任何剩下的可用位元位置中。 第12圖係顯示為了完成第11圖所述的位元配置 之示範方法的流程圖。第12圖之示範方法包括透過一 多重通道通訊系統的複數個通道將要傳輸的位元編碼 為編碼位元，其中編碼位元具有糸統位元以及同位位 元(在步驟500中）。多重通道通訊系統的複數個通道 〇 包括具有一個較高可靠度的通道以及一個較低可靠度 的通道。在步驟510中，根據剔除比率剔除不需要的 編碼位元。上述剔除比率之決定，係希望留下較多與 配置在第二串流中的系統位元有關的同位位元。根據 有些實施例，在配置位元位置之前，先進行剔除程序。 在步驟520中，示範方法包括分配至少若干個系統位 元至對應於較高可靠度通道的第一串流中的位元位置 上。根據其他實施例，在第一串流中的所有位元位置 皆配置為系統位元。在步驟530中，示範方法包括分 21 201101731 配至少若干個所剩下的系統位元至對應於較低可靠度 的通道的第二串流中具有較高訊號先權值的位元位ΐ f。在步驟540中，示範方法亦包括將與位於第二串 2位元位置的系統位元有關的至少若干已經過剔除 _序所剩下的同位位元，以及與位於第—串流中的位 =立置之系統位元有_至少轩已經過剔除程序的 :立位凡，分配至第二串流中所剩下的較低訊號 值位元位置中。 ▲。第3以及15圖係顯示使用結合剔除程序和基於 道可#度之碼字料流對應㈣以及基於訊 ft權值和可靠度兩者的符元對應規則來決定位元的 料二在第13和15圖所描述的範例中，訊號資 =的數置為48個’使用碼率為2/3的16正交振幅調 ’以及在每-傳輸的通道上各產生—組資料串流， 哪-個通道比起另—個通道更具有較佳的可靠 =纟元的位置分配與訊號先權值以及訊 可#度兩者皆有關。 第圖係顯示已編碼的系統位元以及同位位元 :序列。此序列包括了48個系統位元以及以個同位 设預先定義的剔除比為1:2,並使用如上所描 掛庙 >。弟13圖的位元配置係顯示根據字碼對串流 +應以及符tl對應規則來執行—連串的操作。 較言ίΪΓ、圖中的第—個操作，首先分配系統位元到 门0罪又通道中的位元位置，並且分配剩下的系統 22 201101731 位元至較低可靠度通遒中的較高訊號先權值位元位 置。在第二操作步驟中，使用剔除比率來決定與配置 在較低可罪度通道中的系統位元有關的同位位元之數 量，隨後配置這些對應的同位位元至較低可靠度通道 中所剩下的較向訊號先權值位元位置中。在第三操作 步驟中，與配置在較低可靠度通道中的系統位元有關 的所任何剩下的同位位元則被分配到與較低可靠度通 ❹ 道中系統位元被分配至較高訊號先權值位元位置的符 元内較低訊號先權值位元位置。在第四操作步驟中， 與位於較向可靠度通道中系統位元有關的同位位元則 被分配到較低可罪度通道所剩下的較低訊號先權值位 置上。 第14圖係顯示為了完成第13圖所述的位元配置 之不範方法的流程圖。第13圖之示範方法包括透過一 多重通逗通訊系統的複數個通道將要傳輸的編碼位元 編碼上述編碼位元具有系統位元以及同位位元（在 步驟=00中）。多重通道通訊系統的複數個通道包括一 個較间可罪度的通道以及一個較低可靠度的通道。在 步驟610中，根據剔除比率將編碼位元執行剔除程 士：上，除比率之決定’係希望留下較多與配置在 第一串流中的系統位元有關的同位位元。根據有些實 施例在配置位元位置之前，先進行剔除程序。在步 驟㈣中’示範方法包括分配至少若干個系統位元至 於較希可靠度的通道中的第—串流中的位元位置。在 23 201101731 步驟630中，示範方法包括分配至少若干所剩下的系 統位το至於較低可靠度通道中的第二串流裡具有較高 訊號先權值的位元位置。在步驟64〇中，示範方法亦 包括將與位於第：串流中的位元位置的系統位元有關 的至少若干經過剔除程序的同位位元分配至第二串流 中所剩下之具有較咼訊號先權值的位元位置。在步驟 650中，示範方法包括將與位於第二串流中的位元位 置的系統位元有關的至少若干所剩下的同位位元分配 至較低可靠度通道中系統位元被分配至較高訊號先權 值位元位置的符元内之較低訊號先權值位元位置。如 此’同位位元可分配到較低訊號先權值位置中使得至 少有些同位位元被配置到與其有關的系統位元相同符 元中。在步驟660中，示範方法包括將與位於第一串 流中的位元位置的系統位元有關的至少若干個同位位 元分配至第二串流中所剩下具有較低訊號先權值位元 位置上。 第丨5圖係顯示編碼系統位元以及同位位元所組 成的另一個序列。與第13以及14圖所描述的實施例 不同之處在於第15和16圖中實施例的剔除比率並非 為預先定義的，而係利用下面所描述的公式來決定 的。在第15圖所描述的範例，剔除比決定為1:3。第 15圖的位元配置係顯示透過字碼對串流對應以及符 元對應規則來執行一連串的操作。 在第15圖中的第一個操作，分配系統位元到較高 24 201101731 可靠度通道中的位元位置，並且分配剩下的系統位元 至較低可靠度通道中的較高訊號先權值位元位置。在 第二操作步驟中，將與配置在較低可靠度通道中的 統位7L有關的同位位元配置到較低可靠度通道中的所 剩下之較高訊號先權值位元位置中。在第三操作步驟 中，與配置在較低可靠度通道中的系統位元有關的所 有任何剩下的同位位元分配到較低可靠度通道中系統 0 位元被分配至較高訊號先權值位元位置的符元内之較 低訊號先權值位元位置。在第四操作步驟中，與位於 較南可靠度通道中系統位元有關的同位位元則被分配 到較低可靠度通道中所剩下之較低訊號先權值位置 上。 如上面所提到的，根據與調變階層μΐ、編碼速率 及以及資料串流數目μ有關的公式之計算來決定剔除 比率。其關係如下所定義： Ο Nc：=:^ = Ns+Np ⑴(In step 4, the coded bits of I', , and the same bit are included in the channel with a plurality of channel dependencies of the c communication system. In the second: wide channel and - have The lower number of system bit configurations to the method includes at least the bit position in the stream. The first-string all bit positions in the channel of the root reliability are all points:: two embodiments; in the first-stream The Minggu soil trowel is equipped with the 兀 兀 兀. In step 420, the system remaining in the reliability TM^ two sequences, some or even all of the first ", L, the first signal The bit position of the value is assigned to the value of 夸 七 七 七 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In some embodiments, 'allocation of at least some or all of the co-located St is related to the system bit located in the first stream, and the position of the bit in the second stream is assigned to the second stream. The system displays the ^0000 method according to the other embodiment described in the embodiment. The error 1 1 brother 11 uses a combined culling program and is based on Signal 19 201101731 / channel reliability code word pair stream correspondence rule and bit configuration based on signal precedence value symbol correspondence rule. In the example described in Fig. 11, the number of signal data is 48, A 16-quadrature amplitude modulation with a code rate of 2/3 is used, and a set of data streams is generated on each of the transmitted channels, and it is judged which one of the channels has better reliability than the other channel. As described in Figure 11, after encoding and interleaving, a sequence of coded system bits and parity bits is generated. These generated code bits are then mapped to the stream counterparts by codewords according to signal reliability. In this way, the system bits can correspond to the stream of higher reliability channels. Any remaining system bits are placed in the lower reliability channel, and all the parity bits are arranged lower. In the stream of reliability channels, the undesired bits of the coding sequence are eliminated according to the rejection ratio. Thus, after the system bits fill the bit positions of the higher reliability channels, which ones are determined The continuation bit is still assigned to the lower reliability channel. The rejection ratio decision is expected to be comparable to the higher reliability of the system bits associated with the system bits in the lower reliability channel after the culling procedure. The number of parity bits associated with system bits in the channel is much higher. As described in Figure 11, the rejection ratio is 1:2, and in some embodiments, the codeword pair is performed based on reliability after the culling procedure. Correspondence. The symbol correspondence is performed according to the SMP rule based on the first weight. Thus, the system 20 201101731 bit located in the stream of the lower reliability channel will be assigned to the higher of the symbol. At the bit position of the signal first weight, that is, at the symbol bit position, and the parity bit is configured to the lower signal precedence bit position in the symbol in the stream of the lower reliability channel, That is, the position of the non-symbol bit. Therefore, such an operation results in that the first stream in the higher reliability channel is the system bit and the second stream in the lower reliability channel has the system bit in the high signal first bit position. yuan. The co-located bit is assigned 0 to the bit position of the second stream having the lower signal first weight in the symbol of the configured system bit, and the remaining co-located bits are assigned to the second stream. Any remaining available bit locations. Figure 12 is a flow chart showing an exemplary method for completing the bit configuration described in Figure 11. The exemplary method of Figure 12 includes encoding the bit to be transmitted as a coded bit through a plurality of channels of a multi-channel communication system, wherein the coded bit has a system bit and a parity bit (in step 500). Multiple channels of a multi-channel communication system 包括 include a channel with a higher reliability and a channel with lower reliability. In step 510, the undesired coding bits are rejected based on the rejection ratio. The above rejection ratio decision is intended to leave more of the parity bits associated with the system bits configured in the second stream. According to some embodiments, the culling procedure is performed prior to configuring the bit position. In step 520, the exemplary method includes allocating at least a number of system bits to a bit position in a first stream corresponding to a higher reliability channel. According to other embodiments, all bit locations in the first stream are configured as system bits. In step 530, the exemplary method includes dividing 21 201101731 with at least a number of remaining system bits to a bit position having a higher signal precedence value in the second stream corresponding to the channel of lower reliability ΐ f . In step 540, the exemplary method also includes at least a number of co-located bits remaining in the cull_detail associated with system bits located at the second string of 2-bit locations, and bits in the first-stream = The system bit of the stand has _ at least Xuan has already eliminated the program: the position is assigned to the lower signal value bit position remaining in the second stream. ▲. Figures 3 and 15 show the use of a combined culling procedure and a code-based stream corresponding to the trajectory (4) and a symbol correspondence rule based on both the ft weight and the reliability to determine the bit of the second in the 13th In the example described in Figure 15, the number of signal = is set to 48 '16 orthogonal amplitude modulations using a code rate of 2/3' and a data stream is generated on each channel of the transmission, which - One channel is more reliable than the other channel = the position allocation of the unit is related to both the signal weight and the signal # degree. The figure shows the encoded system bits and the parity bits: sequence. This sequence consists of 48 system bits and a pre-defined rejection ratio of 1:2 with a parity setting, using the Temple > as described above. The bit configuration of the 13th figure shows that the series of operations are performed according to the string-to-stream + and the corresponding rules of the t1. In contrast, the first operation in the figure first allocates the system bit to the bit position in the channel and the channel, and allocates the remaining system 22 201101731 bit to the higher of the lower reliability wanted. The signal first weight position. In a second operational step, the culling ratio is used to determine the number of collocated bits associated with system bits configured in the lower sinus channel, and then the corresponding collocated bits are configured into the lower reliability channel The remaining relative signal is in the first weight position. In a third operational step, any remaining co-located bits associated with system bits configured in the lower reliability channel are assigned to higher-level system bits in the lower reliability channel. The lower signal first weight position in the symbol of the signal first bit position. In a fourth operational step, the parity bits associated with the system bits located in the more reliable channel are assigned to the lower signal prior weight positions remaining in the lower sinus channel. Fig. 14 is a flow chart showing an exemplary method for completing the bit configuration described in Fig. 13. The exemplary method of Figure 13 includes encoding the coded bits to be transmitted through a plurality of channels of a multiple-communication communication system. The coded bits have system bits and parity bits (in step = 00). The multiple channels of the multi-channel communication system include a relatively sinister channel and a lower reliability channel. In step 610, the puncturing process is performed on the coded bits based on the culling ratio: the upper, the ratio decision determines to leave more of the parity bits associated with the system bits configured in the first stream. According to some embodiments, the culling procedure is performed before the bit position is configured. In step (4), the exemplary method includes allocating at least a number of system bits to a bit position in the first stream in the channel of the higher reliability. In 23 201101731 step 630, the exemplary method includes allocating at least a number of remaining system bits το to a bit position having a higher signal prior weight in the second stream of the lower reliability channel. In step 64, the exemplary method also includes allocating at least a plurality of cull-releasing co-located bits associated with system bits located in the bit position of the first stream to the second stream having the remaining The bit position of the first weight of the signal. In step 650, the exemplary method includes assigning at least a number of remaining co-located bits associated with system bits located in a bit position in the second stream to a lower reliability channel in which system bits are assigned The lower signal precedence bit position in the symbol of the high signal first weight bit position. Thus, the 'colocated bit' can be assigned to a lower signal pre-weighted position such that at least some of the co-located bits are configured into the same symbol as the system bit associated with it. In step 660, the exemplary method includes allocating at least a number of co-located bits associated with system bits located at a bit location in the first stream to a lower signal prior weight bit remaining in the second stream Meta location. Figure 5 shows another sequence of coding system bits and co-located bits. The difference from the embodiment described in Figs. 13 and 14 is that the rejection ratio of the embodiments in Figs. 15 and 16 is not pre-defined, but is determined by the formula described below. In the example depicted in Figure 15, the rejection ratio is determined to be 1:3. The bit configuration of Fig. 15 shows that a series of operations are performed by word-to-stream correspondence and symbol correspondence rules. In the first operation in Figure 15, the system bits are allocated to the bit position in the higher 24 201101731 reliability channel, and the remaining system bits are allocated to the higher signal precedence in the lower reliability channel. Value bit position. In a second operational step, the parity bits associated with the location 7L configured in the lower reliability channel are configured into the remaining higher signal prior weight location in the lower reliability channel. In a third operational step, all remaining co-located bits associated with system bits configured in the lower reliability channel are assigned to the lower reliability channel. System 0 bits are assigned to higher signal precedence. The lower signal precedence bit position within the symbol of the value bit position. In the fourth operational step, the parity bits associated with the system bits located in the souther reliability channel are assigned to the lower signal prior weight positions remaining in the lower reliability channel. As mentioned above, the rejection ratio is determined based on the calculation of the formula relating to the modulation level μΐ, the coding rate, and the number of data streams μ. The relationship is defined as follows: Ο Nc:=:^ = Ns+Np (1)
R 其中iVc表示經編碼、交錯以及剔除程序之後編碼 位元之總數，馬表示系統位元的數目（亦即資訊位元的 數目）’以及馬》表示同位位元的數目。 較低可靠度通道中的串流之位元配置之關係如下 所定義： '=~~ = NS+NP (2) 其中丸為位於較低可靠度通道中的編碼位元數 25 201101731 量，元為位於較低可靠度通道中的系統位元數量以及 為位於較低可靠度通道中的同位位元數量。在較低 可靠度通道中的複數符元之較高的訊號先權值位元 (亦即符號位元）之數目定義為：R where iVc represents the total number of coded bits after encoding, interleaving, and culling, and the horse indicates the number of system bits (i.e., the number of information bits) and the horse indicates the number of parity bits. The relationship of the bit configuration of the stream in the lower reliability channel is defined as follows: '=~~ = NS+NP (2) where the pill is the number of coded bits in the lower reliability channel 25 201101731 quantity, element The number of system bits in the lower reliability channel and the number of parity bits in the lower reliability channel. The number of higher signal precedence bits (i.e., sign bits) of the complex symbols in the lower reliability channel is defined as:
设CSet C
Ns^：=\^~2 ⑶ 此外 NS=NC-{NC-NS) (4) 而 NP := N(P + N^} =NC-NS (5) 其中係為與分配在較低可靠度通道的系統位 元有關的同位位元之數量，以及句係為與分配在較高 可靠度通道的系統位元有關的同位位元之數量。死。〕以 及及?>可計算如下：Ns^:=\^~2 (3) In addition NS=NC-{NC-NS) (4) and NP := N(P + N^} =NC-NS (5) where the system is assigned with lower reliability The number of parity bits associated with the system bits of the channel, and the number of parity bits associated with the system bits allocated to the higher reliability channel. Dead.] and and ?> can be calculated as follows:
以及 Ν{^ =ΝΡ- Ν{°] A -2 R A Μ ⑹ ^-R\A\M-\A\ + 2 r\a\mAnd Ν{^ =ΝΡ- Ν{°] A -2 R A Μ (6) ^-R\A\M-\A\ + 2 r\a\m
Ns ⑺ 從公式（6)和公式（7)，可決定剔除比率為： ⑻Ns (7) From equation (6) and equation (7), the rejection ratio can be determined as: (8)
7 I M-2 J 其中 26 201101731 Ο Ο 第16圖係顯示為了完成第15圖所述的位元配置 之示範方法的流程圖。第16圖之示範方法包括透過一 多重通道通訊系統的複數個通道將要傳輸的一組訊號 編碼為具有糸統位元以及同位位元的編碼位元（在步 驟700中）。多重通道通訊系統的複數個通道包括一個 較高可靠度的通道以及一個較低可靠度的通道。在步 驟710中’示範方法包括分配至少若干系統位元至較 南可靠度通道的第一串流中的位元位置。在步驟720 中，示範方法包括分配至少若干剩下的系統位元至較 低可靠度通道中的第二串流裡具有較高訊號先權值的 位元位置中。在步驟730中，示範方法办包括將位於 第二串流中的位元位置的系統位元有關的至少若干同 位位元分配至第二串流中所剩下的具有較高訊號先權 值的位元位置上。在步驟740中，示範方法包括將與 位於第二串流中的位元位置之系統位元有關的任何所 剩下的同位位元分配至較低可靠度通道中系統位元被 分配至較高訊號先權值位元位置的符元内的較低訊號 先權值位元位置。在步驟75〇中，示範方法亦包括將 位於第一串流中的位元位置之系統位多有關的至少若 干個同位位元分配至第二串流中所剩卞的具有較低訊 號先權值之位元位置上。在步驟76〇中，示範方法包 括根據公式（8)以及(9)決定剔除比率，妒上所述。 上面所提供的描述以及在此所顯系的基於訊號先 27 201101731 權值和通道可靠度的資料傳輸示範方法，示範裝置和 示範電知程式產品。第17圖係顯示以積體電路/晶片 2〇〇或用以執行在此所述的各種功能的通訊裝置2〇1 之形式的所示範的裝置實施例。積體電路/晶片2〇〇或 通afl裝置201可包括及/或用以執行在此所描述的功 月匕尤其疋第8-16圖中所述的功能。例如，積體電路 /晶片200可包括或用以執行編碼器126、通道交錯器 128、一速率匹配器16〇、一碼字對串流對應器 一付元對應器160、預編碼器136以及控制器丨62的 功能。 關於第17圖’在有些實施例中，裝置2〇1實現或 包括有線或無線通訊功能的通訊裝置之構成元件。例 如不移動終端（stationary terminal)，裝置201可為存取 點（例如，基地台、無線路由器等）、電腦、一伺服器、 支挺網路通訊的裝置等之一部分。例如行動终端 (mobile terminal)，裝置201可為行動電腦、行動電話、 可攜式數位助理（portable digital assistant，簡稱 PDA)、一攜帶型傳呼器（pager)、一行動電視、一遊戲 機、一膝上型行動電腦（laptop computer)、一照相機、 一影音錄放影機、一音訊/影音播放器、一無線電、及 /或全球定位系統(global positioning system ’ 簡稱 GPS) 裝置’或上述任何的結合等等，不論通訊裝置為何種 形式，裝置201亦包括計算能力。 示範裝置201包括其他用於通訊的積體電路/晶片 28 201101731 205、一記憶體裝置210、一通訊介面電路215、一接 收器271、傳送器272、天線273、使用者介面電路220、 顯示器261、鍵盤262以及揚聲器263。積體電路/晶 片205透過執行各種功能的裝置來具體實現，例如一 微處理器、一協同處理器（coprocessor)、一控制器、一 特定目的積體電路（例如專用積體電路（application specific integrated circuit，簡稱 ASIC)、元件可程式邏 ❹ 輯閘陣列（field programmable gate array，簡稱 FPGA)、硬體力口速器（hardware accelerator)、處理電路 等）。在有些實施例中，積體電路/晶片205用以執行 儲存於記憶體裝置210中的指令或進入積體電路/晶片 205的指令。如此’儲存於記憶體裝置21〇中的指令 即為有關第8-16圖的敘述中所執行功能之指令。 不論是利用硬體或透過儲存於計算機可讀取儲存 媒體（computer-readable storage medium)的指令，或者 〇 是上述兩者之結合，積體電路/晶片205可為根據上述 所對應的實施例來執行操作的實體。因此，在積體電 路/晶片205可透過專用積體電路、元件可程式邏輯閑 陣列等或其部分來實現的實施例中，積體電路/晶片 2〇5可特定麟管理在此所述操作的硬體。而在 ，路/晶片205係可具體實料财後計算機可讀取儲 存媒體的指令之執行者的其他實施例中，上述指令^ ί別用於裝配積體電路/晶片205以執行在此所述的= 异法或操作。另外’在有些可根據積體電路/晶片地 29 201101731 的配置透過執行在此所述的演算法、方法以及操作的 執行指令的實施例中，積體電路/晶片205 $用以執行 實施例之特定裝置的處理器（例如，行動終端）。 〇 記憶禮裝置210為至少一個包括揮發性及/或非揮 發性的計算機可讀取f特媒體。有些實施财，記憶 體裝置210包含具有動態隨機存取記㈣（办軸^ RAM)及/或靜態隨機存取記憶體(static RAM)、嵌入式 (on-chip)或可抽取式（0ff_chip)快取記憶體及/或等等 的隨機存取§己‘fe體（Random Access Memory，簡稱 RAM)。此外，記憶體裝置210可包括嵌入式及/或可 抽取式非揮發性記憶體，且可包括唯讀記憶體、快閃 記憶體、磁存貯裝置（例如硬碟、軟碟裝置、磁帶等）、 光碟機及/或媒體、非揮發性隨機存取記憶體 (non-volatile random access memory，簡稱 NVRAM)7 I M-2 J where 26 201101731 Ο Ο Figure 16 is a flow chart showing an exemplary method for completing the bit configuration described in Figure 15. The exemplary method of Figure 16 includes encoding a set of signals to be transmitted into a coded bit having a system bit and a parity bit through a plurality of channels of a multi-channel communication system (in step 700). The multiple channels of the multi-channel communication system include a higher reliability channel and a lower reliability channel. In step 710, the exemplary method includes allocating at least a number of system bits to a bit position in a first stream of a souther reliability channel. In step 720, the exemplary method includes allocating at least a number of remaining system bits to a bit position having a higher signal prior weight in the second stream of the lower reliability channel. In step 730, the exemplary method includes allocating at least a plurality of co-located bits associated with system bits located at a bit position in the second stream to the remaining higher priority values in the second stream Bit position. In step 740, the exemplary method includes assigning any remaining co-bits associated with system bits located in the bit locations in the second stream to lower reliability channels in which system bits are assigned higher The lower signal precedence bit position within the symbol of the signal first bit position. In step 75, the exemplary method also includes allocating at least a plurality of co-located bits associated with a system bit located at a bit position in the first stream to a lower signal precedence remaining in the second stream The value of the bit position. In step 76, the exemplary method includes determining the rejection ratio according to equations (8) and (9), as described above. The description provided above and the data transmission demonstration method based on the signal 27 201101731 weight and channel reliability, the demonstration device and the demonstration electronic program product. Figure 17 shows an exemplary device embodiment in the form of an integrated circuit/wafer 2 or a communication device 2〇1 for performing the various functions described herein. Integrated circuit/wafer 2 or pass afl device 201 may include and/or be used to perform the functions described herein, particularly in Figures 8-16. For example, the integrated circuit/wafer 200 can include or be used to execute an encoder 126, a channel interleaver 128, a rate matcher 16A, a codeword pair stream counterpart to a pay element counterpart 160, a precoder 136, and The function of the controller 丨62. Regarding Fig. 17' In some embodiments, the device 2〇1 implements or constitutes a constituent element of a communication device of a wired or wireless communication function. For example, without a stationary terminal, the device 201 can be part of an access point (e.g., a base station, a wireless router, etc.), a computer, a server, a device for communicating with a network, and the like. For example, a mobile terminal, the device 201 can be a mobile computer, a mobile phone, a portable digital assistant (PDA), a portable pager, a mobile TV, a game machine, and a mobile terminal. Laptop computer, a camera, a video recorder, an audio/video player, a radio, and/or a global positioning system (GPS) device or any combination of the above Etc., regardless of the form of the communication device, device 201 also includes computing power. The exemplary device 201 includes other integrated circuits/wafers 28 for communication, 201101731 205, a memory device 210, a communication interface circuit 215, a receiver 271, a transmitter 272, an antenna 273, a user interface circuit 220, and a display 261. , a keyboard 262 and a speaker 263. The integrated circuit/wafer 205 is embodied by a device that performs various functions, such as a microprocessor, a coprocessor, a controller, and a specific purpose integrated circuit (eg, application specific integrated Circuit (referred to as ASIC), component programmable logic array (field programmable gate array (FPGA), hardware speed (hardware accelerator), processing circuit, etc.). In some embodiments, the integrated circuit/wafer 205 is used to execute instructions stored in the memory device 210 or instructions to enter the integrated circuit/wafer 205. Thus, the instructions stored in the memory device 21 are instructions for the functions performed in the description of Figs. 8-16. Whether integrated with hardware or by instructions stored in a computer-readable storage medium, or a combination of the two, the integrated circuit/wafer 205 may be in accordance with the corresponding embodiments described above. The entity that performed the operation. Therefore, in embodiments in which the integrated circuit/wafer 205 can be implemented by a dedicated integrated circuit, a component programmable logic array, or the like, the integrated circuit/wafer 2 can be managed by the specific subsystem. Hardware. In other embodiments, where the way/wafer 205 is an executor of instructions for the computer readable storage medium, the instructions are used to assemble the integrated circuit/wafer 205 for execution herein. Said = different method or operation. In addition, in some embodiments in which the execution instructions of the algorithms, methods, and operations described herein are performed in accordance with the configuration of the integrated circuit/wafer field 29 201101731, the integrated circuit/wafer 205$ is used to execute the embodiment. A processor of a particular device (eg, a mobile terminal).记忆 Memory device 210 is at least one computer readable f-media including volatile and/or non-volatile. In some implementations, the memory device 210 includes a dynamic random access memory (four) (running axis RAM) and/or static random access memory (static RAM), embedded (on-chip) or removable (0ff_chip). Cache memory and/or the like of random access § 'Random Access Memory (RAM). In addition, the memory device 210 may include embedded and/or removable non-volatile memory, and may include read only memory, flash memory, magnetic storage devices (eg, hard disk, floppy device, tape, etc.) ), optical drive and/or media, non-volatile random access memory (NVRAM)
及/或等等。記憶體裝置210可包括資料臨時儲存的快 取緩衝區。就這點而言，有些或所有的記憶體裝置210 可被包括於積體電路/晶片205裡面。 通訊介面電路215可為實現於硬體、電腦程式產 品’或者是硬體和電腦程式產品的結合之一者的任何 裝置或工具，其中硬體和電腦程式產品的結合可用於 接收及/或傳送資料從/到網路225及/或可為透過接收 器271、傳送器272以及天線273與範例裝置2〇1通 訊的任何其他裝置或模組。積體電路/晶片205亦可例 如藉著通訊介面電路215中的控制硬體透過通訊介面 30 201101731 電路以促使交換資料。此外，偕同接收器27i、傳送 器272、和天線273的積體電路/晶片2〇5以及通訊介 面電路215用以支援不論何種的無線通訊，包括與多 重輸入多重輸itj(MIMQ)的環境以及執行正交分頻多 工（OFDM)訊號的環境之通訊。And/or so on. The memory device 210 can include a cache buffer for temporary storage of data. In this regard, some or all of the memory device 210 can be included in the integrated circuit/wafer 205. The communication interface circuit 215 can be any device or tool implemented on a hardware, a computer program product, or a combination of a hardware and a computer program product, wherein a combination of a hardware and a computer program product can be used for receiving and/or transmitting. Data from/to the network 225 and/or any other device or module that communicates with the example device 2〇1 via the receiver 271, the transmitter 272, and the antenna 273. The integrated circuit/wafer 205 can also facilitate the exchange of data by, for example, controlling the hardware in the communication interface circuit 215 through the communication interface 30 201101731. In addition, the integrated circuit 27i, the transmitter 272, and the integrated circuit 273 of the antenna 273 and the communication interface circuit 215 are used to support any wireless communication, including an environment with multiple input multiple input (ITQQ). And communication of an environment that performs orthogonal frequency division multiplexing (OFDM) signals.
使用者介面電路220係為與積體電路/晶片2〇5溝 通以透過顯示器26卜鍵盤262以及揚聲器加來接 收使用者輸人紐供❹者輸出。根據有些實施例， =如裝置201為-基地台的實_，則排除了使用者 ^面，路260、顯示器261、鍵盤城以及揚聲器加。 轉5本》/1: 14以及16圖係根據-實施例所述系 、洗、或電腦程式產品的流程圖。藉由這些圖 :择::::程圖的每一操作或方塊’及/或流程圖中 的操作或方塊之結合可透過許多裝冷 程圖的操作或方塊之裝置’流程圖中 = 結合或其他在此所敘述的實施彳 '、5 另B之功能可包括硬體， 或〇括具有計算機可讀取儲存 品’其中上料算機可讀取儲存體 程式碼指令、電腦指令或儲存其内至少一電腦 可讀取程式碼指令。就此討論 了執灯的計具機 記憶體裝置，例如範例裝置(例如t指令可儲存於 體裝置21〇中，以及透過第8圖=置201)的記憶 處理器(例如積體電路/晶片 ：述的几件或某種 人士已知，任何像是程式碼指4,:。熟悉此技藝 7了攸計算機可讀取儲 201101731 存媒體載入到一電腦或其他程控裝置（例如：積體電路 /晶片205、記憶體裝置210等等）以產生一特定的設備 使能成為執行流程圖所說明方法或操作之功能的裝 置。這些程式碼指令亦可儲存於一計算機可讀取儲存 媒體以管理一電腦、一處理器或其他程控裝置以運行 在一特定方法中進而形成一特定設備或特定的製造商 品。儲存於計算機可讀取儲存媒體的指令可產生執行 流程圖所說明的方法或操作的功能之裝置的製造商 品。程式碼指令可於計算機可讀取儲存媒體中重新獲 得並且載入一電腦、處理器或其他程控裝置以安排透 過上述電腦、處理器或其他程控裝置來執行操作，或 於上述電腦、處理器或其他程控裝置上來執行。上述 程式碼指令的重新取回、載入以及執行可一連串地執 行，因此在一時間中可重新取回、載入以及執行一指 令。在有些實施例中，程式碼指令的重新取回、載入 以及執行可利用平行的方式來執行，因此可一起重新 取回、載入以及執行程式碼指令。程式碼指令的執行 會產生一計算機執行程序，因此上述電腦、處理器或 其他程控裝置所執行的指令提供執行說明於流程圖中 的方法或操作之功能的工作。 因此，處理器所執行的與流程圖的方塊或操作有 關的指令，或與計算機可讀取儲存媒體中流程圖的方 塊或操作有關的儲存，支援執行這些特定功能操作的 結合。可了解的是流程圖中至少一方塊或操作或是上 32 201101731 述方塊或操作之組合，可利用特定目的以硬體為基礎 可執行特定功能或特定目的硬體以及程式碼指令的結 合的電腦系統及/或處理器予以實現。 所提出之變型與潤飾以及其他實施例將可以使熟 習此項技藝者充分瞭解到本發明具有以上說明以及相 關圖示所教示的特點與優點。因此，可以了解的是本 發明並未只限縮為上述已揭露之特定實施例，任何其 變型與潤飾及實施例係亦屬本申請專利範圍之保護範 圍内。此外，雖然上述的詳細說明以及相關所附圖式 以基本要素及/或功能方式闡述的特定實施例之結合 的内容來描述實施例，但可了解的是任何基於以其基 本要素及/或功能方式闡述的各種不同之結合亦可藉 由其他替代之未背離本申請專利保護範圍的實施例所 提供。就其而論，例如，任何以基本要素及/或功能方 式闡述的各種不同之結合而非上述明確說明亦可被視 為本申請專利範圍中所提出之保護範圍。雖然這裡使 用一些特定術語來描述本發明，但此特定術語係以一 般或描述性的方式來使用，並非用以限制本發明。 33 201101731 【圖式簡單說明】 第1圖係顯示具有預編碼之基於單碼字的空間多 工多重輸人多重輸出（Scw_based spatial mu脚lexing ΜΙΜΟ)之傳送端的方塊圖。 第2圖係更具體描述的編碼器126之圖示。 第3圖係顯示通道交錯以及剔除程序的概要方塊 圖。 第4a-4c圖係顯示在基於單碼字傳輸下具有不同 的串流數目的碼字對串流對應之方塊圖。 弟5 a圖係顯示基於單碼字位元位置的資料處理。 第5b以及5c圖係顯示16正交振幅調變 (Quadrature Amplitude Modulation，QAM)星座圖所指 出的位元可靠度。 第6圖係顯示在多重輸入多重輸出系統中基於多 碼字的傳送端之方塊圖。 第7a以及7b圖係顯示在基於多碼字傳輸下具有 不同的串流數目的碼字對串流對應之方塊圖。 第8圖係顯示根據實施例所述之在多重輸入多 重輸出系統中基於單碼字的傳送端之方塊圖。 第9、11、13以及15圖係顯示根據一實施例所述 之根據訊號先權值和通道可靠度的位元配置方法。 第10、12、14以及16圖係顯示根據一實施例所 述之根據訊號先權值和通道可靠度來執行位元配置方 法之流程圖。 34 201101731 第17圖係顯示根據一實施例所述之基於訊號先 權值和通道可靠度來執行位元配置方法之裝置。 【主要元件符號說明】 124〜資訊位元； 126、142〜編碼器； 128、144〜通道交錯器； 130、146、156〜速率匹配器； 132、160〜符元對應器； 134、150、158〜碼字對串流對應器； 136、152〜預編碼器； 138、154、162〜控制器； 102、104、106〜組成編碼器； 100〜迴旋渦輪碼交錯器； 10 8〜A子區塊， 110〜B子區塊； 112〜Y1子區塊； 114〜Y2子區塊； 116〜W1子區塊； 118〜W2子區塊； 120〜子區塊交錯器； 122〜交錯碼序列； 140〜切割器； 35 201101731 148〜調變器； 201〜通訊裝置； 225〜網路； 271〜接收器； 272〜傳送器； 273〜天線； 215〜通訊介面電路； 205〜積體電路/晶片， 210〜記憶體裝置； 220〜使用者介面電路； 261〜顯示器； 262〜鍵盤； 263〜揚聲器。 36The user interface circuit 220 communicates with the integrated circuit/chip 2〇5 to receive the user input and output through the display 26 and the speaker 262. According to some embodiments, = if the device 201 is a real base of the base station, the user's face, the way 260, the display 261, the keyboard city, and the speaker are excluded. Transfer 5/1: 14 and 16 are flowcharts of the system, wash, or computer program product according to the embodiment. By means of these figures: the operation of each operation or block of the :::: diagram and/or the operation of the block or the combination of the blocks can be carried out through a number of operations or block devices that are equipped with a cold map. Or other implementations described herein, the functions of the other B may include hardware, or include computer readable storage, where the input processor can read the stored code instructions, computer instructions or storage. At least one computer can read the code instructions. In this connection, the meter memory device of the lamp is discussed, for example, a memory device (such as an integrated circuit/wafer: the example device (for example, the t command can be stored in the body device 21, and the image is transmitted through the figure 8). Some of the pieces mentioned or somebody knows that any code like 4 means:: Familiar with this skill 7 攸 Computer readable storage 201101731 Storage media loaded into a computer or other program control device (eg: integrated circuit /chip 205, memory device 210, etc.) to generate a particular device enable device to perform the functions or operations described in the flowcharts. The code instructions can also be stored in a computer readable storage medium for management A computer, a processor or other programmed device for operating in a particular method to form a particular device or a particular article of manufacture. The instructions stored on the computer readable storage medium can produce the method or operation illustrated by the flowchart. The manufacture of a functional device. The code instructions can be retrieved from a computer readable storage medium and loaded into a computer, processor or other programming device. Arranging to perform operations through the above computer, processor or other program control device, or executing on the above computer, processor or other program control device. The retrieving, loading and execution of the above code instructions can be performed in series, thus An instruction can be retrieved, loaded, and executed in time. In some embodiments, the retrieving, loading, and execution of the code instructions can be performed in a parallel manner, so that they can be retrieved, loaded, and loaded together. Executing code instructions. The execution of the code instructions produces a computer executed program, such that the instructions executed by the computer, processor or other programmed device provide the functionality to perform the functions or operations described in the flowcharts. The instructions executed by the device relating to the blocks or operations of the flowchart, or the storage associated with the blocks or operations of the flowcharts in the computer readable storage medium, support a combination of these specific functional operations. It is understood that in the flowchart At least one block or operation or a combination of 32 201101731 blocks or operations, A computer system and/or processor that performs a specific function or a combination of specific purpose hardware and program code instructions on a hardware-specific basis may be implemented. The proposed variations and retouchings and other embodiments will make this familiar. The skilled artisan is well aware of the features and advantages of the present invention as described in the foregoing description and the accompanying drawings. It is understood that the invention is not limited to the specific embodiments disclosed above, any variations and modifications thereto. The embodiments are also intended to be within the scope of the invention, and the embodiments are described in the context of the description of the specific embodiments and the It is understood that any combination of the various elements that are described in terms of their basic elements and/or functions may be provided by other alternatives without departing from the scope of the invention. In this regard, for example, any combination of the various elements set forth in the basic elements and/or functional aspects, rather than the above-described explicit description, may also be considered as the scope of protection set forth in the scope of the claims. Although specific terms are used herein to describe the invention, the specific terms are used in a generic or descriptive manner and are not intended to limit the invention. 33 201101731 [Simple description of the diagram] Figure 1 shows a block diagram of the transmission end of a spatially multiplexed multiple input multiple output (Scw_based spatial mu lexing ΜΙΜΟ) with precoding based on a single codeword. Figure 2 is an illustration of an encoder 126, which is described in more detail. Figure 3 is a block diagram showing the channel interleaving and culling procedures. Figures 4a-4c show block diagrams of codeword pair streams having different numbers of streams based on single codeword transmission. The brother 5 a shows the data processing based on the position of the single code word bit. Figures 5b and 5c show the bit reliability indicated by the 16 Quadrature Amplitude Modulation (QAM) constellation. Fig. 6 is a block diagram showing a multi-code word-based transmission end in a multiple input multiple output system. Figures 7a and 7b show block diagrams of codeword pair streams having different numbers of streams based on multi-codeword transmission. Figure 8 is a block diagram showing a single codeword-based transmitting end in a multiple input multiple output system according to an embodiment. Figures 9, 11, 13, and 15 show bit configuration methods based on signal pre-weight and channel reliability, in accordance with an embodiment. Figures 10, 12, 14 and 16 show a flow chart for performing a bit allocation method based on signal pre-weight and channel reliability, in accordance with an embodiment. 34 201101731 FIG. 17 is a diagram showing an apparatus for performing a bit configuration method based on signal preemption values and channel reliability according to an embodiment. [Main component symbol description] 124~ information bit; 126, 142~encoder; 128, 144~channel interleaver; 130, 146, 156~ rate matcher; 132, 160~ symbol counterpart; 134, 150, 158~ codeword pair stream counterpart; 136, 152~ precoder; 138, 154, 162~ controller; 102, 104, 106~ composition encoder; 100~ cyclotron turbo code interleaver; 10 8~A sub Block, 110~B sub-block; 112~Y1 sub-block; 114~Y2 sub-block; 116~W1 sub-block; 118~W2 sub-block; 120~sub-block interleaver; 122~interlace code Sequence; 140~Cutter; 35 201101731 148~ modulator; 201~communication device; 225~network; 271~receiver; 272~transmitter; 273~antenna; 215~communication interface circuit; 205~integrated circuit / wafer, 210 ~ memory device; 220 ~ user interface circuit; 261 ~ display; 262 ~ keyboard; 263 ~ speaker. 36
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| US12/536,032 US20100027704A1 (en) | 2007-09-10 | 2009-08-05 | Method and Apparatus for Data Transmission Based on Signal Priority and Channel Reliability |
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