TW201101399A - Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die - Google Patents

Abstract

A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to the UMB layer to align the die relative to the conductive pillar. An encapsulant is deposited over the die and around the conductive pillar. The UBM layer prevents shifting of the semiconductor die while depositing the encapsulant. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electricaaly connected through the conductive pillar. The first or second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device and a fixed bump that is relatively fixed to an interconnect structure based on alignment of the semiconductor die. A method of lowering a metallization (UMB) layer. [Prior Art] Semiconductor components are commonly found in modern electronic products. Semiconductor components vary in the number and density of electrical components. Discrete semiconductor components are generally a type of electrical component 'e.g., a light emitting diode (led), a small signal = body = device, a capacitor, an inductor, and a power MOS semiconductor field MOSFET (MOSFET). The whole person's main road threat _ children's 11 type + conductor element typically contains thousands of four electrical components. The whole person _. σ-type + conductor element examples include microcontrollers, microprocessors, charge 铋 射 射 咖 咖 咖 咖 咖 咖 : : : : : 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能 太阳能High-speed computing, transmission and 11% LD h, control of electronic components, conversion of light into electricity and the production of television display y power conversion, _ body components for entertainment, communications, seen in military applications and consumer products . Semiconductor components are also found in soap applications, aerospace, semiconductor component utilization control, and office equipment. ® ^ M ^ _ + Electrical properties of the conductor material. The semiconductor material is controlled by its structure. The technique of rubbing impurities to the electric field or the conductivity of the body element through the replacement process. The semiconductor element is manipulated to control the semiconductor. 201101399 A semiconductor component includes active and passive electrical structures. Active structures containing diodes and field effect transistors control current flow. By changing the doping level and applying an electric or base current, the transistor does not increase or limit the current flow. Passive structures containing resistors, capacitors, and inductors have a relationship between the voltage and current required to perform various electrical functions. The passive and active structures are electrically connected to perform high speed calculations and other useful functions. Semiconductor components are typically fabricated using a two-composite process, known as a front-end process and a back-end process, each of which can involve hundreds of steps. The end process involves forming a plurality of crystal grains on the surface of a semiconductor wafer. Each die typically has exactly the same circuitry and contains circuitry formed by electrically connected active and passive components. The back end process involves singulating individual dies from the finished wafer and constructing the dies to provide structural support and environmental = separation. The components of the semiconductor are typically efficiently fabricated, which can be formed by modifying the crystalline material of the moving member to form within the formed structure to help target one of the processes to make smaller semiconductor components. It also consumes less power, has higher execution efficiency, and is more versatile. In addition, smaller semiconductor components have a smaller footprint to provide smaller end products... smaller die sizes can be used in front-end processes to produce smaller, higher density active and ready-to-use processes. The electrical connection and the mounting of the semiconductor component having a smaller space are improved. These pages are often required for wafer level wafer size (WLcsp). p and the bottom interconnect structure. The top and bottom interconnect structures are wafer-level wafer size mounted on the U-Board and other printed circuit boards (PCBs) or substrates. Through the interconnection structures on the top and bottom surfaces of the β-frame, a plurality of wafer-level wafer size packages can be placed to form a stacked package to provide complex or conductive penetration in a small package volume. The via hole (ΤΗν) ι forms a via hole or a conductive via hole. A via hole is etched. The mussel penetrates the semiconductor material or a peripheral region of the semiconductor die. The vias are then filled with a conductive material, for example by copper deposition in an electromine process. However, the semiconductor die is difficult to align during die bonding and the right gas r #foot system < u gate flat will shift during the process of the sealant, which leads to component failure and lower manufacturing yield. . SUMMARY OF THE INVENTION There is a need for semiconductor die mounting and alignment between vertical interconnect structures without displacing the die. In view of the above, in one embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of providing a temporary carrier, forming an H-electrode layer on the temporary carrier, and forming a bump under the temporary carrier Metallized layer. The under bump metallization layer is fixed at a relative position of the first conductive layer. The method further includes the steps of forming a conductive pillar on the first conductive layer, mounting a semiconductor die to the under bump metallization layer to align the semiconductor die to the conductive pillar and at the semiconductor A glue is deposited on the die and around the conductive pillar. The under bump metallization layer prevents the semiconductor grain from shifting during deposition of the sealant. The method further includes the steps of: removing the temporary carrier to form a first interconnect structure on the first surface of the encapsulant and forming a second surface on the sealing agent opposite the first interconnecting junction 201101399 The second interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillars.另一 Ο In another embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of providing a temporary carrier, forming a first conductive layer on the temporary carrier, and forming a bump on the temporary carrier Lower metallization layer. The under bump metallization layer is fixed at a relative position of the first conductive layer. The method further includes the steps of forming a conductive pillar on the first conductive layer, mounting a semiconductor die to the under bump metallization layer to align the semiconductor die to the remainder, and (4) semiconductor die Depositing a sealant around the upper and lower electrodes, removing the temporary carrier, forming a first interconnect structure on the first surface of the sealant and a second surface of the sealant opposite the first interconnect structure Forming a second interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillars. The invention is characterized in that the conductive pillar is electrically connected and is irradiated, and the invention is a method for manufacturing a conductor component, which comprises a step shape comprising a wettable contact pad # fixed to the relative positions of the contact pads. a first interconnect structure of the under bump metallization layer, a pillar formed on the wettable contact tab of the interconnect structure, and a first semiconductor component mounted to the under bump metallization layer to Aligning the semiconductor component to the conductive pillar, depositing a sealant on the semiconductor member and around the conductive pillar, and forming a second interconnect structure on the second surface of the sealant opposite to the first interconnect structure . The first and second interconnects. In another embodiment, the present invention is a semiconductor device comprising a first conductive layer and a bump underlying layer 7 201101399. A conductive pillar is formed on the first -^^5^ Λ isoelectric layer. A semiconductor component to the conductive column. A semiconductor structure touches the women's clothing to the under-metallization layer of the bump to match the +-conductor grain to the main track and the electric field. A glue is deposited on the "Xuan semiconductor daily granule and around the conductive column. _ An interconnect structure is formed on the first surface of the sealant. A second stone n is further formed on the second surface of the sealant opposite to the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillars. DETAILED DESCRIPTION OF THE INVENTION [Embodiment] The present invention is described in the following description, or in more embodiments, wherein like numerals represent the same or similar components. While the present invention has been described in its preferred embodiments, the embodiments of the invention are intended to Alternatives, modifications, and equivalents are included in the spirit and scope of the invention. Semiconductor components are generally fabricated using a two-composite process, a front end process, and a back end process. The front end process involves forming a plurality of grains on a surface of a semiconductor wafer. Each of the dies on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. For example, an active electrical component of a transistor has the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers create the relationship between voltage and current required to perform electrical circuit functions. The passive and active components are formed on the surface of the semiconductor wafer through a series of processes including doping, deposition, lithography, etching, and planarization. Doping techniques are introduced into the semiconductor material via, for example, ion implantation or bombardment. The technique of the impurity process = the technique of the bulk material to convert the conductivity of the impurity material to convert the internal semiconductor of the semiconductor device or to dynamically change the conductivity of the semiconductor material and the current of the conductor. The transistor contains an electric field or base region as needed to cause the transistor to flow according to the electric field or 2 = type and extent. - Earth π electric 'melon to enhance or limit the active and passive components for different composition. The layers of material may be formed by various types of conditional techniques determined by the type of material to be formed by the layer of material. For example, all kinds of, redundant borrowing mvm from Tian Wei "children's technology can include chemical gas phase; the second deposition is called electric ore and no electricity. Each process is formed by patterning to form active components, passive components (4) The electrical connection portion. The A4 structure layer can be patterned using lithography imaging technology, which includes, for example, a salt-resisting sleeve ##β 'ubiquitous material of a photoresist. ❹2 is used to transfer a pattern from a mask to the photoresist by light. The portion of the photoresist pattern that encounters λ is removed using _solvent to expose the underlying layer to be patterned. The remainder of the photoresist is removed leaving a patterned layer. Alternatively, some material types are previously deposited/synchronized process domains using direct deposition materials such as electroless ore-type technology. Or patterning in the pores. Forming a thin film material on a ready-made pattern expands the underlying pattern, 'generating a non-uniform flat surface. A uniform flat surface is needed to produce a smaller and denser package Active and passive The planarization technique can be used to remove material from the surface of the wafer and produce a uniform flat surface. The flattening technique involves polishing the surface of the wafer with a polishing pad. - Abrasive material and rot Sex chemicals are added to the surface of the wafer during polishing. The mechanical action of the gentleman's grinding and the corrosive action of the chemical remove any irregular topography and produce a uniform flat surface. The back end process refers to cutting or Singulating the completed wafer into the individual dies and then structuring the dies to provide structural support and environmental isolation. To singulate the dies, the wafer is scribed along a so-called cut saw or scribe line The non-functional area of the wafer is marked and cut. The wafer is cut into grains using a laser cutting tool or a saw blade. After singulation, individual dies are mounted to include pins or contact pads to be integrated with other systems. The component is connected to the substrate, and the contact pad formed on the semiconductor die is then connected to the component: the contact pad. The electrical connection can be matched with the solder ball bump, the short post bump, the conductive wire Come [...] a sealant or other encapsulant material is deposited on the structure for physical support and electrical isolation. The completed package is then inserted with an electrical amp and the semiconductor (4) function is a slice carrier for other system components. The electronic component of the substrate or printed circuit board 52 is electrically mounted. It may have a certain semiconductor package type or a plurality of semiconductor package types, and the power is fixed: in the description (4), the different semiconductor package types are shown in FIG. The component 50 can be a sub-component of the electronic component 5G-type system instead of using the semi-electrical functions. For example, the electricity can be - can be inserted into an electric moon: 10 201101399 Card, drag, grazing, μ J-channel interface card or other signal processing card. The semiconductor structure can be 微处理器 3 microprocessor, memory, special-purpose integrated circuit (ASIC), logic circuit class ratio circuit, RF circuit , discrete components or other semiconductor dies or electrical components. In Fig. 1, 'the main substrate is provided for the semiconductor package U-support and electrical interconnection' printed circuit board 52 mounted on the printed circuit board. The conductive trace lines 54 are formed on one surface or multiple layers of the printed circuit board 52 using an evaporation process, an electroplating process, an electroless plating process, a screen printing process, or other suitable metal deposition process. Signal trace 54 provides electrical and trajectory 54 for each of the semiconductor components, mounting members, and other external system components to provide electrical and ground connections to each of the semiconductor components. In some embodiments, a semiconductor component has a two-construction stage. The first stage of construction is a technique for mechanically and electrically bonding the semiconductor die to an intermediate carrier. The second level of construction involves mechanically and electrically bonding the carrier to the printed circuit board. In other embodiments, a semiconductor component can have only the first level of construction, wherein the die is mounted directly to the printed circuit board via mechanical and electrical means. Some first stage construction types including wire bond assembly 56 and flip chip assembly 58 are shown on printed circuit board 52 for illustrative purposes. In addition, a solder ball array (BGA) package 60, a bump wafer carrier (BCC) 62, a dual array package (DIP), a planar array (LGA) package 66, and a multi-chip module (Mcm) package 68 are included. The four-stage flat-type, lead-free (QFN) 7-pin and four-sided flat-mounted packages are mounted on the printed circuit board 52. According to the requirements of the 11 201101399 system, the first and second Any combination of the staged mounting patterns and any combination of semiconductor components constructed by other electronic components can be coupled to the printed circuit board 52. In some embodiments, the electronic components 5A comprise a single bonded semiconductor package, while other implementations For example, multiple connection configurations are required. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electronic components and systems. Because these semiconductor packages contain complex functions, they can be used less expensive. Components and a modern process to manufacture electronic components. The components produced are less likely to fail, and the manufacturing costs are lower for the consumer and the components produced are cheaper. _ za_zc is not a bit of a smock The semiconductor die 74 includes an active region containing an analog or digital circuit, and the circuitry is configured to be formed in the die and in accordance with any of the features of the dual-array package 64. The electrical design of the die is electrically connected to the active component, the passive component, the conductive layer and the dielectric layer. For example, the circuit may comprise one or more transistors 'diodes, inductors, capacitors Γ resistors and formed in The contact pad 76 in the active region of the semiconductor die 74 is, for example, one of the first (A1), copper (CU), tin (four), brocade (10), u 〆 silver (Ag) or more conductive material layers, and Electrically connected to the circuit component of the semiconductor die 74 to be in the period of time H. In the combined double row structure 64 8 + conductor grain 74 is a metal ruthenium alloy layer, such as I $ lipid paste Good #卡6 / σ gold layer or, for example, hot epoxy tree pure material, the text is attached to an intermediary carrier 78, such as polymer or ceramics, which contains 7. Insulation material for the class The wire 80 and the sustaining electrode k are electrically interconnected between the semiconductor die 74 and the brush circuit board 52. The sealing agent 84 is deposited on the structure. The sealant, gas and particles enter the structure, and provide environmental protection by dyeing the grain 74 or the wire 82. Figure 2b illustrates the embossing u 1 仓, Cangbei, which is mounted on the printed circuit board 52. Further details of the wafer carrier 62. The semiconductor die 88 is mounted on the carrier 90 using a bottom-fill or grease bond material 92. The wire 94 provides a first-level package that contacts between 3% and 98. An interconnecting compound or encapsulant is deposited on the semiconductor die 88 and the wiring 94 to provide physical support and electrical isolation of the component. The contact die 102 is formed using a suitable metal deposition process such as electrowinning or electroless plating. It is formed on the surface of the printed circuit board to prevent oxidation. The contact pad 102 is electrically connected to the conductive signal track 54 of the printed circuit board. The solder bump is deposited on the bump wafer carrier to contact the contact pad of the printed circuit board 52. 〇 2 And being reflowed to form bumps 104 that form a mechanical and electrical connection between the bump wafer carrier 62 and the printed circuit board 52. In Figure 2c, the semiconductor die 58 is mounted face down to have a flip-chip first-stage dielectric carrier 1〇6. The active region 108 of the semiconductor die 58 includes an active device, a passive component, a conductive layer, and a dielectric layer formed according to the die electrical design. Analog or digital circuits, for example, may include three or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within the active region 108. The semiconductor die 58 is a solder bump Or the ball 11 is electrically and mechanically connected to the carrier 106. The solder ball array assembly 60 is electrically and machine-finished using solder bumps or balls 112! The ground is connected to a second stage structure having a solder ball array. a printed circuit board mounted with semiconductor die 58 Bump n〇, signal line U4 and solder 13 201101399 Bump U2 is electrically connected to the printed signal track of the printed code 52. A glue compound or sealant 116 is deposited on the semiconductor die 58 and (4) The component is physically isolated and electrically isolated. The flip-chip semiconductor component provides a short conductive path from the active component on the semiconductor die 58 to the conductive trace on the printed circuit board 52 to reduce signal transmission distance and reduce capacitance. And improving the overall circuit execution efficiency. In another embodiment, the material conductor die 58 can be mechanically and electrically connected directly to the printed circuit without using the intermediate carrier 1G6 and using the flip-chip first-stage configuration. The plate 52 ° 3h illustrates a method of forming a vertical interconnect structure having a conductive pillar and an under bump metallization layer that is relatively fixed to the interconnect structure based on the alignment of the semiconductor die. In the figure, temporary or sacrificed The substrate or carrier 120 comprises, for example, a stone, a polymer, a polymer composite, a metal foil, a ceramic slab, a glass, a glass epoxy, a yttria, a tape, or a suitable low structure for structural support. The substrate of the hard material. The selective seed layer 122 can be formed on the carrier 120 for subsequent electroplating process. A conductive layer 124 is used, gas phase, gas phase deposition, chemical vapor deposition, sputtering, electroplating, no An electroplating process or other suitable metal deposition process is patterned to form the carrier 120. The conductive layer 124 can be aluminum, copper 'tin, nickel, gold, silver, tungsten, polysilicon or other suitable conductive material to have one or more layers. Conductive Layer 124 includes a wettable contact pad for later forming a conductive post. In one embodiment: a wet turbid contact pad of 24 is pre-bonded to carrier 12, conductive layer 126 using physical vapor deposition, Chemical vapor deposition, splashing 14 201101399

Plating, Electro-Ore, I Electroplating Process "Other suitable metal deposition processes are patterned to form on the seed layer 122. Conductive layer 126 can be one or more of aluminum, copper, tin:, nickel, gold, silver, or other suitable electrically conductive material. Conductive layer 126 is coplanar with conductive layer 124. The conductive layer 126 is an under bump metallization layer fixed at a relative position of the conductive layer 124. The under bump metallization layer 126 can be a multi-metal stack having an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer may be titanium, titanium nitride (TiN), titanium tungsten (Tiw), aluminum or chromium (Cr). The barrier layer is formed on the adhesive layer and may be made of nickel, nickel vanadium (nw), Platinum (Pt) palladium (Pd), titanium tungsten or chromium copper (CrCu). The barrier layer inhibits the diffusion of copper into the grain active region. The seed layer can be copper, recorded, recorded vanadium, gold or Aluminium. A seed layer is formed on the barrier layer. The under bump metallization enhances the low resistance interconnection and the barrier of the seed layer for solder diffusion and solder wetting capability. In Figure 3b, a plurality of conductive layers A post or rod 128 is formed on the m-contact pad of the conductive layer 124. In an embodiment, the conductive post i28 is formed by depositing more or more photoresist layers on the seed layer 122 or the carrier 12〇. A portion of the photoresist layer on the 124 is removed and removed via a button-engraving process. The conductive material is deposited in the removed portion of the photoresist layer using a selective electro-mine process. The photoresist layer is stripped. In addition, each of the conductive pillars 128 is left. The conductive pillars 128 may be copper, freon, crane (w), gold, solder or other suitable conductive material. The conductive pillar 128 has 2 ΐ 2 〇 micrometer (four) range height. In another embodiment 'formed conductive pillars 128 may be short stud bumps or stacked bumps. In any example m 128 has solder or contains copper, silver, bismuth or One of the tin metal compounds (IMC) is produced to the under bump 15 201101399 The metallization layer 126 is a strong and tight metal to metal bond. In Figure 3c, a plurality of semiconductor dies or members 130 are oriented with metal bumps 134 A flip chip arrangement positioned over the carrier 120 is mounted to the under bump metallization layer 126. The semiconductor die 130 includes an active region 136 containing an analog or digital circuit configured to be formed in the crystal An active component, a passive component, a conductive layer, and a dielectric layer that are electrically interconnected within the particle and according to the electrical design and function of the die. For example, the circuit may include one or more transistor 'diodes and formed The other circuit components in the active surface 126 are configured with a baseband analog circuit or a digital circuit such as a digital signal processor (DSp), a special purpose integrated circuit, a memory or other signal processing circuit. Including integrated passive components for RF signal processing, such as inductors, capacitors, and resistors. In another embodiment, the S vertical semiconductor component can be mounted to the carrier 12A. The under bump metallization layer 126 is fixed. The conductive pillars 128 are mounted on the conductive layer 124 around the semiconductor die 13 . Accordingly, the under bump metallization layer 126 is fixed at the relative position of the conductive pillars 128. Block 134 and under bump metallization layer 126, semiconductor 130 self-aligns to conductive pillar 128. Figure 3d shows the use of a solder paste printing, compression molding, transfer molding, body sealing knee molding, vacuum lamination or other suitable application The device is used to deposit a 4-conductor die 130 and a sealant or sealant 4 on the conductive post 128. The sealant 138 may be a polymer composite resin, a propylene glycol acrylate having a filler: = an epoxy of a charge. The sealing is non-conductive and the semiconductor component is protected by polymerization of the == filler. 201101399 Isolating external components and contamination. The metal bumps 134 of the semiconductor die 130, which are firmly mounted to the under bump metallization layer 126, are not displaced during alignment of the conductive pillars 128 during the encapsulation process.

In Figure 3e, encapsulant 138 is ground or plasma etched to planarize the surface to form a top side build-up interconnect structure. In one embodiment, the grinder 丨 39 exposes the top surface of the conductive pillar 128 and the back surface of the semiconductor die 13 . Alternatively, the grinder 139 exposes the top surface of the conductive pillar 128 and retains the semiconductor die 13 内 embedded in the encapsulant 13 8 . In the figure, a top side build-up interconnect structure 140 is formed on the conductive pillars 128, the first surface of the sealant 138, and the back surface of the semiconductor die 13 . - Insulation or containment 142 is formed using physical vapor deposition, chemical vapor deposition, printing, spin coating, smear coating, sintering or thermal oxidation processes. The protective layer (4) may be silica sand (Si〇2), nitrite (Si3N small oxynitride eve (8) (10)), pentoxide (Ta2〇5), alumina (a12〇3) or have similar insulation and Among other materials of structural properties, one or more of the engraving processes remove the sub-protective layer 142 to expose the conductive pillars 128. The conductive layer 144 is patterned on the protective layer 142 and the conductive pillars 128 by patterning using physical vapor deposition, chemical vapor deposition, ore, electro-mine, electroless ore or other suitable metal deposition processes. The conductive layer (4) can be a copper, tin, tin, gold, silver or other suitable conductive material 22 = multiple layers. A portion of the conductive layer 144 is electrically connected to the conductive 枉US. The other part of : 4 may be electrically or electrically isolated depending on the design and power of the semiconductor component. -Insulation or protection...46 using physical vapor deposition, chemical vapor deposition 201101399 product, printing, ^^ slave gold, spray, sintering or thermal oxidation process to form in the protective layer 142 and guide mine 'Side 1: layer 144 on. The protective layer 146 can be one or more of cerium oxide, nitrogen, oxidizing, pentoxide, aluminum oxide or other materials having similar insulating and structural properties. The portion of the protective layer 146 is removed by an etching process to expose the conductive layer 144. In the palace, the carrier 120 is removed by chemical wet-type etching, plasma dry etching, mechanical shedding, chemical mechanical polishing, mechanical grinding, hot baking, laser, drawing or wet stripping. After the carrier 12 is removed, the sealant (10) provides a semiconductor crystal #13G structure. The carrier 12() is removed followed by the conductive layer 124 and the under bump metallization layer 126. In Figure 3h, a bottom side build-up interconnect structure 15 is formed on the conductive pillars 128 and the second surface of the sealant opposite the top side build-up interconnects. The conductive layer 152 is patterned on the conductive layer 124 and the under bump metallization layer 126 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless clocking, or other suitable metal deposition process. The conductive layer W can be a complex layer or layers of aluminum, copper, tin, nickel, gold, silver or other suitable electrically conductive material. Portion 152 is electrically connected to conductive pillar 128, conductive layer 124, and under bump metallization layer 126. The other part of the conductive layer 152 can be electrically and electrically isolated according to the design and function of the semiconductor element - "There is only a layer of training, pre-chemical, chemical rolling, printing, spin coating, spraying A sintering or 埶f & thermalizing process is formed on the second surface of the conductive layer 152 and the encapsulant 138.豕保竣1 1 4 can be a second generation of fossils, tantalum nitride, niobium oxynitride, pentoxide-hole 1 - bismuth, alumina or other materials with class 18 201101399 like insulation and structural properties Or more layers. The portion of the protective layer 154 is removed by the etch process to expose the conductive layer 152. - The conductive bump material is deposited on the conductive layer by evaporation, electroplating, electroless plating, solder ball dropping or screen printing process. On the layer 152. The bump material may be a combination of Ming, Tin, Li, Gold, Silver, Wrong, Foil, Copper, Solder, and the like, plus a selective flux material. For example, the bump material may be a total The tin-lead/lead, high-stagger solder or no-material tin H is suitable for bonding or bonding the bump material to the conductive layer 152. In an embodiment, the bump material is heated by heating the material beyond its melting point. Reflowing to form spheres or bumps 156. In some applications, bumps 156 are reflowed for a second time to improve electrical contact to conductive layer 15. 2. The bumps can also be compression bonded to conductive Layer 152. Bumps 156 represent some type of interconnect that can be formed on conductive layer 152 The interconnect structure may also use wiring, (iv) paste, stud bumps, micro bumps, or other electrical interconnections. The semiconductor die 13G is singulated by a pellet or laser cutting 164 to become individual After semiconductor (4) 16 singulation, the individual semiconductor components 160 may be stacked as indicated by β 4. The conductive pillars 128 are between the top side germanium layer interconnect 140 and the bottom side buildup interconnect layer 15 A vertical 2-way interconnection is provided. The conductive layer 144 is electrically connected to the conductive layer 152 of each of the semiconductor elements 160 and the metal bumps 134 through the conductive pillars 128. Figure 5 has multiple integrations formed in the top-side interconnect structure Vertical interconnect structure of passive components. Similar to the method of Figures 3a-3, semiconductor component 162 uses a sacrificial or temporary substrate or carrier having a selective seed layer. - Conductive layer 164 uses physical vapor deposition, chemical vapor deposition, Excavation, electricity 19 201101399 Two = process or other suitable metal deposition process for patterning to form a carrier. Conductive layer 164 can be Ming, steel, tin, recorded, gold, silver, crane, polycrystalline stone or other suitable conductive In the material One or more layers. The conductive layer (6) comprises a wettable contact pad for later forming a conductive post. - The conductive layer (6) uses physical vapor deposition, chemical vapor deposition, de-plating, electroless plating, electroless plating or other A suitable metal deposition process is patterned to form on the bond seed layer or carrier. Conductive I 166 can be one or more layers of aluminum, copper:, tin, nickel', gold, silver, or other suitable electrically conductive material. The conductive layer 166 is coplanar with the conductive layer 164. The conductive (four) 166 is an under bump metallization layer fixed at a position opposite to the conductive layer 164. The plurality of conductive pillars or rods 168 are formed on the conductive layer 164. In the embodiment, the conductive germanium 168 is formed by depositing one or more photoresist layers on the seed layer or carrier. A portion of the photoresist layer on the conductive layer 164 is exposed and removed via an etch developing process. Conductive material 2 is deposited in the removed portion of the photoresist layer using a selective electroplating process. " The sea photoresist layer is stripped leaving the respective conductive pillars 168. Conductive post 168 can be copper, aluminum, tungsten, gold, solder or other suitable electrically conductive material. The conductive posts have a height in the range of 2-120 microns. In another embodiment, the formed conductive pillars 168 can be short stud bumps or stacked bumps. In any example, the conductive pillars 168 have a solid and tight metal to metal bond 0 of a plurality of semiconductor grains formed by solder or a metal-containing compound containing copper, silver, antimony or tin to the under bump metallization layer 166. Or the component 丨7〇 is mounted to the under bump metallization 20 201101399. The layer 166 is a flip chip arrangement in which the metal bump 丨 74 is clamped downwardly over the carrier. The semiconductor die 170 includes an active region, a passive component that is formed in the die and electrically interconnected according to the electrical design and function of the die. , conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active table 176 to configure, for example, a digital signal processor, special purpose integrated circuit, memory, or other signal processing circuit. Base frequency analog circuit or digital circuit. The semiconductor wafer (7) may also include integrated passive components for RF signal processing, such as inductors, u capacitors, and resistors. The under bump metallization layer 166 is fixed to the opposite position of the conductive layer 164. Conductive posts 168 are mounted on conductive layer 164 around semiconductor die 17 . Accordingly, the under bump metallization layer 166 is fixed to the opposite position of the conductive pillars 168. The semiconductor die 170 self-aligns to the conductive posts 168 by mating the metal bumps 174 with the under bump metallization layer 166. aS"

A glue or sealant compound 178 is applied to the semiconductor die 17 and the conductive posts 168 ± using a solder paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination or other suitable applicator. The sealant "78 can be a polymer composite', for example, an epoxy resin with a filler, an epoxy propylene with a filler, or a polymer with a correct filler. Sealing = m is non-conductive and environmentally protects the semiconductor component from externalities, parts and contamination. With the metal bumps 174 firmly attached to the body die 170 of the under bump metallization layer 166, the die is not displaced during the encapsulation process. The encapsulant 178 is ground or electrically ground to planarize the surface while 21 201101399 forms a top side build-up interconnect structure top surface and a semiconductor die 170 structure 1 80 is formed on the conductive pillar 16 §, the die 170 On the back surface. A deposition, chemical vapor deposition, and printing process are formed. The protective layer i 82 is one of the other materials of the fossil, the antimony pentoxide, the aluminum oxide, and the other layer 182 to expose the conductive pillar. This lapping operation exposes the back surface of the conductive crucible 168. The top side build-up interconnect sealant 178 first surface and the semiconductor edge or protective layer 182 may be cerium oxide, tantalum nitride, nitrogen oxide or the like using physical vapor deposition coating, sintering or thermal oxidation. And the layer of structural properties. The portion of the first conductive layer 184 is removed by an etching process using physical vapor deposition, chemical vapor deposition, cesium clock, electric bond, electroless ore or other suitable metal deposition process for patterning to form the protective layer 182 and the conductive pillars 168. on. The conductive layer 184 can be one or more layers of the inscription, copper, tantalum, gold, silver or other suitable conductive material. The partial conductive layer 184 is electrically connected to the conductive pillars 168. Other portions of the conductive layer m may be electrically or electrically isolated depending on the design and function of the (4) semiconductor component. The resistive layers 186a-186b are separately patterned and deposited on the conductive layer 184 and the insulating layer using physical vapor deposition or chemical vapor deposition. The resistive layer 186 is TaxSiy or other metal telluride 'nitride button, nickel chrome, titanium, titanium nitride, titanium tungsten or doped polysilicon having a resistivity of 5 to 1 ohm ohm/square. An insulating layer 188 is formed over the conductive layer 18 by patterning using physical vapor deposition, chemical vapor deposition, printing, sintering or thermal oxidation processes. The insulating layer 188 can be a nitrided 7' dioxide dream, a nitrogen oxynitride eve, a pentoxide pentoxide, a zinc oxide, a cerium oxide, an aluminum oxide, a polyimine, a stupid ring 22 201101399 'women, poly phenyl ring Or among other suitable dielectric materials, the layer or the resistive layer 186 and the insulating layer 188 may be formed in the same mask and simultaneously in two layers. engraved. Alternatively, the resistive layer 186 and the insulating layer m. Etching is patterned and etched. (4) Military advance An insulating or protective layer 190 is formed on the protective bank 1 by using spin coating, physical vapor deposition, printing, sintering or thermal oxidation processes: the electrical layer m, the resistive layer 186 and the insulating layer (8). , for the day of sulphur dioxide, nitrite, gas oxidized stone, pentoxide, oxidation, ^

One of the other materials having suitable insulating properties or the X protective layer is removed to expose the conductive layer 184, electrical resistance. Part 188. The electric layer 186 and the insulating layer 192 are deposited by physical vapor deposition, chemical vapor deposition, electroplating, electroless process or other suitable metal deposition process: deposited on the protective layer 190, the conductive layer 184, The resistive layer 186 and the insulating layer are formed to form individual portions or sections for further interconnectivity. Conductive layer 〇 Thunder: Other parts can be electrically or electrically isolated depending on the connectivity of the individual semiconductor dies. Conductive layer 192 can be one or more of the layers of copper, tin, nickel, gold, silver or other suitable electrically conductive material. The Guangyi insulation or protective layer 194 is formed on the conductive layer 濩 layer 190 using spin coating, physical vapor deposition, chemical chaotic deposition, printing, sintering or thermal oxidation processes. The protective layer 194 may be ruthenium dioxide, tantalum nitride, ruthenium oxide, or aluminum oxide or a layer having more than one of the layers having suitable insulating properties. A portion of the protective layer 194 is removed to exit the conductive layer 192. 23 201101399 The structure described in the build-up interconnect structure 18〇—or more passive circuit components or integrated passive components. In one embodiment, conductive layer 184, resistive layer 186a, insulating layer 188, and conductive layer 192 are a metal-insulator-metal layer (MIM) capacitor. Resistive layer 186b is a resistor component in the passive circuit: individual segments of conductive layer m can be wound in a planar field of view: coiled to create or exhibit desired inductor characteristics. The integrated passive component structure provides the required high frequency applications such as resonators, high pass filters, low pass choppers, band passers, symmetrical high-factor f-factor resonance transformers, matching networks, and tuning capacitors. Electrical characteristic curve. The integrated passive components can be used as front-end radio frequency components that can be positioned between the antenna and the transceiver. The inductor can be a high quality factor balanced-unbalanced converter, transformer or coil operating at up to 1 〇〇 GHz. In some applications, multiple baluns are formed on the same substrate for multi-band operation. Example J ^ — or more balanced – unbalanced converters are used in mobile phones or

匕王垛仃动动通信系统(Eight _Unbalanced in the four bands of GSM) ^ ^Wwen change state provides one of the four frequency components to operate. One typical ^Bei, four one or more semiconductors The assembly requires multiple integrated passive components and their thousands of baskets called φ ^ Λ At 匕 A frequency circuit to perform the required electrical functions. 8 The carrier is subjected to chemical wet etching, dry-drying, mechanical shedding, Chemical mechanical polishing, mechanical grinding, squeezing...', roasting, laser scanning or wet stripping. After the carrier is removed, the seal is supported by ice + Α W 1 The carrier is removed and then the generaized layer 166. The conductive layer (6) and the bump under gold 24 201101399 a bottom side build-up interconnect structure is formed on the conductive pillar 168 opposite the top side build-up interconnect structure 180 and Sealant 178 conductive layer 202 is patterned using physical vapor deposition, chemical vapor deposition: an electrical process or other suitable metal deposition process, conductive layer 164 and under bump metallization layer 166. Conductive layer 2 〇2 可Ο Ο is aluminum, copper, tin, nickel, gold, silver or other One or more layers of the conductive material. The partial conductive layer 2〇2 is electrically connected to the conductive layer (6), the conductive layer 164 and the under bump metallization layer 166. The conductive layer may be according to the design and function of the semiconductor element. Formed on the conductive layer 202 and the sealant m for the common charge from the insulating or protective layer 2〇4 using physical vapor deposition, chemical vapor deposition printing, suspect coating, spraying, sintering or thermal oxidation processes. On the surface, the protective layer 2〇4 may be one or more of the group consisting of silica, yttrium, yttrium oxide, pentoxide, oxidized or other materials having similar insulating and structural properties. The conductive layer 2 is exposed by a process of removing the portion of the protective layer. A conductive bump material is deposited on the conductive layer using a steaming, electromineral, unprocessed, solder ball dropping or screen printing process. The bump material may be a combination of stellite, tin-nickel, gold, silver, erbium, bismuth, copper, solder, and the like, plus a selective fluxing (four) material. For example, the bump material may be eutectic tin. / wrong ' Shang Ming solder or no wrong rod tin. Use a suitable bonding or bonding system Bonding the ghost material to the conductive layer 2〇2. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a sphere or bump in two applications. The bumps 206 are backed up - a second time to improve the electrical contact of the pair of 201101399 conductive layers 202. The bumps can also be compression bonded to the conductive layer 202. The bumps 206 can be formed on the conductive layer 2 A type of interconnect structure on 2. The interconnect structure can also use wiring, conductive paste, stud bumps, tiny bumps, or other electrical interconnects. The conductive pillars 168 are on the top side of the layered interconnect μ 18〇 A vertical 2-way interconnection is provided between the bottom side build-up interconnect layer 200. The conductive layer 184 is a metal bump 174 electrically connected to the conductive layer 2〇2 and the semiconductor die 17〇 through the conductive pillars 168. Figure 6 illustrates an embodiment of a vertical interconnect structure having a plurality of integrated passive components formed in a bottom side interconnect structure. Similar to the method described in Figures 3a-3h, the semiconductor component 212 is fabricated with a sacrificial or temporary substrate or carrier of a selective seed layer. The conductive layer 214 is formed using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or Other suitable metal deposition processes are patterned to form on the support. Conductive layer 214 can be one or more of aluminum, copper 'tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. Conductive layer 214 includes a wettable gasket for forming a conductive post. A conductive layer 216 is patterned on the seed layer or carrier using physical vapor deposition, chemical vapor deposition, sputtering plating, electroless plating, or other suitable metal deposition process. Conductive layer 216 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. Conductive layer 216 is coplanar with conductive layer 214. Conductive layer 216 is an under bump metallization layer that is fixed to the opposite location of conductive layer 214. A plurality of conductive posts or rods 218 are formed on the wettable joints of the conductive layer 214. In one embodiment, the I##μs conductive pillars 218 are formed by depositing one or more ❹, one 曰/s of a layer on a seed layer or carrier. Portion on the Conductive Layer = The photoresist layer is exposed and removed via a one-shot development process. A conductive material is deposited in the removed portion of the photoresist layer by a selective electroplating process: the photoresist layer is stripped leaving the respective conductive pillars 218. Conductive post 218 can be copper 'H gold, solder or other suitable electrically conductive material. The conductive post 218' has a height of 2 1 2G micron circumference. In another embodiment, the formed conductive pillars 2 18 may be short stud bumps or stacked bumps. In any example, the conductive pillars 218 are metallized by solder or copper-containing silver, silver, or tin-based intermetallic compounds, and 211 are strong and tightly metal-to-metal bonded to a plurality of semiconductor crystals. The pellets or members 22 are mounted to the under bump metallization layer 216 in a flip chip arrangement in which the metal bumps 224 are positioned downwardly over the carrier. The semiconductor die 22A includes an active region 226 containing an analog or digital circuit, and the circuits are configured as active components formed in the die and electrically interconnected according to the design and function of the die. Passive component, conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 226 to configure a Z-digital signal processor, special-purpose integrated circuit, memory, or other signal processing circuit. Base frequency analog circuit or digital circuit. The semiconductor die 22 can also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors. The under bump metallization layer 216 is fixed to the opposite position of the conductive layer 214. Conductive posts 218 are mounted on conductive layer 214 around semiconductor die 220. 27 201101399 As such, the under bump metallization layer 216 is fixed at the relative position of the conductive pillars 218. The semiconductor die 220 self-aligns to the conductive pillars 218 by mating the metal germanium block 224 with the under bump metallization layer 216. A glue or sealant compound 228 is deposited onto the semiconductor die 22 and the conductive posts 218 using a solder paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination or other suitable applicator. The sealant may be a polymer composite such as an epoxy resin having a filler, a propylene glycol acrylate having a filler, or a polymer having a positive filler. The encapsulant 228 is non-conductive and environmentally protects the semiconductor component from external components and contamination. The metal bumps 244, which are firmly mounted to the semiconductor die 220 of the under bump metallization layer 216, are replaced by a metal bump 224 which is aligned with the conductive pillars 2 1 8 during the sealing process. Not shifted. The encapsulant 228 is ground or plasma etched to planarize 唁 to form a top side buildup interconnect junction. The polishing operation exposes the conductive pillars, the top surface of the 218, and the surface of the semiconductor die 22G#. The top side build-up structure 230 is formed on the conductive pillar 218, the first surface of the sealant 228, and the back surface of the bulk die 220. An insulating or protective layer plus phase deposit: chemical vapor deposition, printing, spin coating, spray coating, sintering or cardioforming (4). The protection I 232 may be a ruthenium dioxide, a ruthenium nitride- emulsifier, an oxidation layer or other materials having similar insulation and junctions, among which one or more layers. The two-dimensional protective layer 232 is removed by the engraving process to expose the conductive pillars 2丨8. The conductive layer 234 is formed by physical vapor deposition, chemical vapor deposition ore, electric ore, electroless ore strips, _^甘# human, swallowed ash or its suitable metal deposition process for patterning 28 201101399 Layer 232 and conductive pillars 218. Conductive layer 234 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 234 is electrically connected to the conductive pillars 218. ^ Other portions of the electrical layer 234 may be electrically or electrically isolated depending on the design and function of the semiconductor component. An insulating or protective layer 236 is formed over the insulating layer 232 and the conductive layer 234 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 236 can be one or more layers of SiO2, lanthanum nitride, lanthanum oxynitride, pentoxide oxide, aluminum oxide or other materials having suitable insulating properties. A portion of the protective layer 236 is removed by an etching process to expose the conductive layer 234. The support is removed by chemical wet etching, electric dry etching, mechanical shedding, chemical mechanical polishing, mechanical grinding, hot baking, laser scanning or wet stripping. After the carrier is removed, the encapsulant 228 provides structural support for the semiconductor die 22〇. The carrier is removed and the conductive layer 214 and the under bump metallization layer 2 16 are then exposed. A bottom side build-up interconnect structure 240 is formed on the second surface of the conductive pillar 218 and encapsulant 228 opposite the top side build-up interconnect structure 230. A conductive layer 242 is patterned on the conductive layer 214 and the under bump metallization layer 216 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 242 can be one or more of the layers 'copper, tin, gold, silver, or other suitable electrically conductive material. The portion of the conductive layer 242 is electrically connected to the conductive pillars 21, 8, the conductive layer 214, and the under bump metallization layer 216. The other portion of the conductive layer 242 29 201101399 may be electrically or electrically isolated depending on the design and function of the semiconductor component. The resistive layer 244 is patterned and deposited using physical vapor deposition or chemical vapor deposition. The resistive layer 244TaxSly or other metal lithium, nitrided group, chrome, titanium nitride or a doped polycrystalline spine having a resistivity of 5 to 100 ohms/square. The insulating layer 246 is formed on the conductive layer 242 using a physical vapor deposition, chemical vapor deposition, printing, sintering or thermal oxidation process. The insulating layer 246 may be nitride, sulphur dioxide, sulphur oxynitride, pentoxide, zinc oxide, oxidized oxidized, oxidized lycopene, polyiminimide, benzocyclobutene, polyphenylene. One or more of the layers of the yttrium or other suitable dielectric material. The resistive layer ... and the insulating layer 246 may be formed by the same mask and simultaneously etched. The alternative two-resistive layer 244 and insulating layer 246 can be patterned and etched with different masks. a — insulating or protective layer 248 spin coating, physical vapor deposition, chemical chaotic deposition, printing, sintering or thermal oxidation process to form on the conductive layer 242, = ... and the insulating layer ... the protective layer 248 can be two ' characteristic ΐΪOxide oxide, pentoxide pentoxide, oxidized or have suitable insulation: one or more of the other materials. A portion of the protective layer 248 exposes the conductive layer 242, the resistive layer 244, and the insulating layer 246. Patterning (10) = protective layer 248, conductive layer 242, resistive layer 244, and insulating layer 250 using physical vapor deposition, chemical vapor deposition, inductive in/electricity process, or other suitable metal deposition process In the case of individual parts or sections for further interconnectivity. The individual portions of the conductive layer can be electrically or electrically isolated depending on the connectivity of the individual semiconductor dies. Conductive layer 250 can be one or more of aluminum, tantalum, tin, gold, silver, or other suitable electrically conductive material. The cadaver-insulating or protective layer 252 is formed on the conductive layer 248 using spin coating, physical vapor deposition, chemical emulsion deposition, printing, sintering or thermal oxidation processes. The protective layer 252 may be one or more of cerium oxide, nitrogen, strontium, earth oxide, pentoxide, oxidized or one of the bismuth materials having suitable insulating properties. A portion of the Ο 露出 exposes the conductive layer 25. . "The layer (5) is removed and the structure described in the build-up interconnect structure 240 constitutes - or more passive circuit components or integrated passive components. In one embodiment, the conductive layer (4), the insulating layer (10), and the conductive layer 250 are a metal layer 'insulating layer-metal layer capacitor. Resistive layer 244 is the resistor member in the passive circuit. The individual segments of the conductive ^μ" can be wound or coiled in a planar field of view to produce: the desired inductor characteristics. - The conductive bump material is deposited on the conductive layer 25G ± using a steam bond, an electric ore, a moneyless, a solder ball drop screen printing process. The bumps (4) may be |g, ―, nickel, gold, silver, lead, antimony, copper, tantalum and combinations thereof, plus ::: flux materials. For example, the bump material can be eutectic tin/lead,

Two wrong solder or no ship solder. The bump material is bonded to the conductive layer 2 by a suitable bonding or bonding process. In one embodiment, the bump material is reflowed to form a circle by heating the material beyond its refining point. The ball or bump conductive layer is in if: the bump 254 is reflowed for a second time to improve the contact. The bumps can also be compression bonded to the conductive gastric fistula bumps 254 to represent a type of mutual phase that can be formed on the conductive layer 25〇. 201101399 even the 'π-structured interconnect structure can also use wiring, conductive paste, short Stud bumps, tiny bumps, or other electrical interconnections. Conductive posts 218 provide vertical ζ directional interconnections between top side build-up interconnect layer 230 and bottom side build-up interconnect layer 240. The conductive layer 234 is electrically connected to the conductive layers 242 and 25 and the metal bumps 22 of the semiconductor die 22 through the conductive pillars 218. Figure 7 illustrates an embodiment of a vertical interconnect structure having a plurality of integrated passive members formed in the bottom side interconnect structure. The semiconductor component 26 is used with a sacrificial or temporary substrate or carrier. A bottom side interconnect structure is formed on the carrier. A conductive layer 264 is patterned using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process to form individual portions or sections 264a-264h. The conductive layer can be one or more of aluminum, copper, tin, nickel, gold, silver or other suitable electrically conductive material. A portion of the conductive layer 264 is electrically connected to the conductive pillars 16'8. Other portions of the conductive layer 184 may be electrically or electrically isolated depending on the design and function of the semiconductor component. The resistive layer 266a is separately patterned and deposited on the conductive layer 264 and the carrier using physical vapor deposition or chemical vapor deposition. The resistive layer 266 is a doped polysilicon having a resistivity of 5 to 100 ohms/square of TaxSiy or other metal cerium, nitrided, nitrided, nitrided. The insulating layer is formed on the conductive layer (10) by physical vapor deposition, chemical vapor deposition, printing, sintering or ruthenium oxidation. The insulating layer (10) may be nitrogen cut, sulphur dioxide, sulphur oxynitride, pentoxide, zinc oxide, oxidized oxidized, oxidized, poly-imine, benzocyclobutene, polybenzazole or other suitable Dielectric material 32 201101399 • One or more layers in the material. An insulating or protective layer 270 is formed on the conductive layer 264, the resistive layer 266, and the insulating layer 268 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 27 may be cerium oxide, emulsified stone, oxynitride, pentoxide, other materials or other materials having suitable insulating properties, one or more layers. A portion of the protective layer 27 is removed to expose the conductive layer 264, the resistive layer 266, and the insulating layer 268. ❹ A conductive layer 272 is patterned and deposited on the protective layer 27, the conductive layer 264, the resistive layer, and the insulating layer using physical vapor deposition, chemical vapor deposition, sputtering, electroless ore-free processes, or other suitable metal deposition processes. 268 is formed to form individual portions or sections for further interconnectivity. Individual portions of conductive layer 272 may be electrically or electrically isolated depending on the connectivity of the individual semiconductor dies. The conductive layer 272 can be one or more of aluminum, copper, tin, nickel, gold: or its conductive & conductive material. Conductive layer 272 includes a wettable contact pad for later forming a conductive post and an under bump metallization layer that is fixed relative to the conductive pillars based on the alignment of the semiconductor conductor. The ^, 邑, or SiO layer 274 is formed on the conductive layer 272 and the ruthenium layer 270 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 274 may be ruthenium dioxide, tantalum nitride, nitrous oxide, pentoxide, oxidized or yttrium-containing material having suitable insulating properties. A portion of the protective layer 274 is removed to expose the conductive layer 272. The structure described in the build-up interconnect structure 262 constitutes one or more passive components or integrated passive components. In the embodiment, the conductive barrier layer 266a, the insulating layer 268, and the conductive layer 272 are - a metal layer - an insulating layer - a metal layer capacitor. The resistor layer is the resistor in the passive circuit. The other individual segments of the bovine conductive layer 272 can be wound or coiled in a planar field of view to create or exhibit desired inductor characteristics. A plurality of conductive posts or rods 278 are formed on the wettable contact pads of the conductive layer. In an embodiment, conductive pillars 278 are formed by depositing one or more layers of wire on interconnect structure 262. A portion of the photoresist layer on the conductive layer is exposed through the -# engraving process and the removal material is deposited in the removed portion of the photoresist layer using a selective electroplating process. The photoresist layer is stripped leaving the respective conductive pillars 278. The conductive posts can be copper, slag, crane, gold, solder or other suitable electrically conductive material. The conductive pillars have a height in the range of 2 to 120 microns. In another embodiment, the formed conductive posts 278 can be short stud bumps or stacked bumps. In any example, the conductive post 278 has a solid and tight metal to metal bond that is produced by solder or a mesometallic compound containing copper 'silver, tantalum or tin—to the under bump metallization 126. The semiconductor die or member 280 is mounted to the conductive layer 272 in a flip chip arrangement in which the metal bumps 284 are positioned downwardly over the interconnect structure 262. The semiconductor die includes an active region (3) including an analog or digital circuit, and the circuit is configured to be formed in the die and to electrically connect the active component and the passive component according to the electrical property of the die: , conductive layer and &quot; electrical layer. For example, the circuit may include - or more transistors, diodes, and other circuit components formed in the active table ® 126 to configure, for example, the number 34 201101399 • bit signal processor, 牿 牿 、, today's technical minus special purpose product Body circuit, memory or other signal virtual = circuit fundamental analog circuit or digital circuit. Semi-conductors also include integrated passive components for RF signal processing: also: containers and resistors. The electric slinger sealant or sealant compound 288 is deposited on the semiconductor die 28 using a tin-type, transfer molding, liquid-sealing molding, vacuum lamination or firing, and two: suitable for coating A, f ",,. 柙 conductive column 278. Sealant 288 ❹:: #, for example, epoxy resin with filler, with epoxy acrylate or polymer with correct filler The encapsulant 2 8 8 is a component and a protective member; and the semiconductor element is isolated from the outer core. The semiconductor die and the bump 284 are firmly mounted to the conductive layer 272. The die is not displaced during alignment of the bond during the encapsulation process. The sealant 288 is ground or __ to planarize the surface to form a layered interconnect structure. In one embodiment, the polishing operation 〇 ^ the top surface of the conductive pillar 278 and the surface of the semiconductor die · f. Instead of ten grounds, the polishing operation exposes the top surface of the conductive pillar 278 and retains the semiconductor die 28 embedded in the sealant 288. The top side layer is formed on the conductive pillar 278, and the sealant is moved to the surface = surface = "On the surface. An insulating or protective layer 292 is formed by physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation. The protective layer 292 may be dioxate, nitrogen cut, nitrogen. One or more layers of oxidized oxide, a group of alumina, or a mixture of similar insulating and structural properties. A portion of the bond is removed by a process of one (four) process = 35 201101399 292 to expose the conductive pillars 278. The layer 294 is patterned on the protective layer 292 and the conductive pillars 278 by physical vapor deposition, chemical vapor deposition, 贱 key 'electroplating, electroless plating process or other suitable metal deposition process. The conductive layer 294 can be Ming, copper. One or more of tin, nickel, gold 'silver or other suitable conductive material. A portion of conductive layer 294 is electrically connected to conductive pillar 278. Other portions of conductive layer 294 may depend on the design and function of the semiconductor component and Electro-mechanical or electrical isolation. An insulating or protective layer 296 is formed on the insulating layer 292 and the conductive layer 294 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 296 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, pentoxide oxide, aluminum oxide or other materials having similar insulating and structural properties. Part of the protection is removed by an etching process. The layer 296 exposes the conductive layer 294. The temporary carrier is removed by chemical wet etching, plasma dry etching, mechanical detachment 'chemical mechanical polishing, mechanical grinding, hot baking, laser scanning or wet f peeling. After the carrier is removed, the encapsulant 288 provides structural support for the semiconductor die 260. The carrier is removed and then the conductive layer 264 is exposed. - The insulating or protective layer 300 is deposited by physical vapor deposition, chemical vapor deposition, brushing, and spraying. A coating, sintering or thermal oxidation process is formed over the conductive layer 272 and the insulating layer 274. The protective layer may be a dioxide dioxide, nitrogen, bismuth oxynitride, bismuth oxide, aluminum oxide or similar insulating and: One or more of the other materials of the nature. The protective layer is removed by an etching process to expose the conductive layer 272. 36 201101399 - Conductive layer 298 uses physical vapor deposition, chemical vapor deposition, sputtering Patterning is performed on the conductive layer 272 by electroforming, electroless ore or other suitable metal deposition process. The conductive layer may be one or more of aluminum, copper, tin, =, gold, silver or other suitable conductive material. The portion of the knife conductive layer 298 is electrically connected to the conductive pillar 278 and the conductive layer 272. Other portions of the conductive layer 298 may be electrically or electrically isolated depending on the design and function of the semiconductor component. The material is deposited on the conductive layer 298 ± using evaporation, electroplating, electroless plating, solder ball dropping or screen printing processes. The bump material can be a combination of indium, tin, nickel, gold, silver, lead, antimony, copper, solder, and the like, plus a selective flux material. For example, the bump material can be eutectic tin/lead, high lead solder, or lead free solder. The bump material is bonded to conductive layer 298 using a suitable bonding or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 302. In some applications, bumps 302 are reflowed for a second time to improve electrical contact to conductive layer 298. The bumps can also be compression bonded to the conductive layer 298. The bumps 302 represent some type of interconnect structure that can be formed on the conductive layer 298. The interconnect structure can also use wiring, conductive paste, stud bumps, tiny bumps, or other electrical interconnects. A semiconductor die or member 304 is mounted to the back side of the semiconductor device 260 in a flip chip arrangement in which the metal bumps 306 are electrically connected to the conductive layer 298. The semiconductor die 304 includes an active component and a passive component that are embedded in an analog or digital circuit and configured to be electrically formed in the die and electrically interconnected according to the electrical design and function of the die. , conductive layer 37 201101399 and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components that are formed within the active surface 226 to configure, for example, a digital delta processor, special purpose integrated circuitry, memory, or other signal processing. The fundamental frequency analog circuit or digital circuit of the circuit. Semiconductor die 304 may also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors. An underfill material 308 is deposited over the semiconductor die 3〇4. The conductive pillars 278 provide vertical turns interconnect between the bottom side buildup interconnect layer 262 and the top side buildup interconnect layer 290. The conductive layer 294 is an integrated passive component in the conductive bump 278 electrically connected to the conductive 272 and the metal bumps and conductive layers 264 of the semiconductor die, the metal bumps 306 of the semiconductor die 304, and the interconnect layer 262. As described above, the integration is passive. _,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Ugly or even semiconductor dies can be stacked or mounted on the MOSFETs: semiconductor dies, discrete components and structures can use a two-layer interconnect layer and a bottom side build-up layer Interconnect layer. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a further detail of a representative structure of a printed circuit board mounted with a printed circuit board mounted on the surface of the table 2a_2c. Figures 3a-3h illustrate the use of a conductive pillar and alignment based on the semiconductor die. A method of forming a vertical interconnect structure with respect to a fixed under bump metallization layer. The figure illustrates a stacked semiconductor component electrically interconnected using the conductive pillars. The device has an integrated passive element formed in the top-side interconnect structure. The semiconductor component of the component. Integrated passive component formed on the "bottom side interconnect structure towel": ^ Ο 50 52 54 56 58 60 62 64 66 Main component symbol description Electronic component printed circuit board trace line wire bonding structure flip chip solder ball array裴 裴 晶片 晶片 晶片 晶片 晶片 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 Wire 82 Wiring 84 Sealant 88 Semiconductor die 90 Carrier 92 Bottom or epoxy bonding material 94 Wiring 96 Contact pad 98 Contact pad 100 Sealing compound or sealant 102 Contact pad 104 Bump 106 Carrier 108 active area 110 solder bump or sphere 112 solder bump or sphere 114 signal line 116 encapsulant compound or sealant 120 carrier 201101399

122 seed layer 124 conductive layer 126 under bump metallization layer 128 conductive pillar or rod 130 semiconductor die or member 134 metal bump 136 active surface 138 sealant or sealant compound 139 grinder 140 top side build-up Connection structure 142 insulating or protective layer 144 conductive layer 146 insulating or protective layer 150 bottom side build-up interconnect structure 152 conductive layer 154 insulating or protective layer 156 sphere or bump 160 semiconductor element 162 semiconductor element 164 conductive layer 166 conductive layer 168 Conductive post 170 Semiconductor die or member 174 Metal bump 41 201101399 176 178 180 182 184 186 188 190 192 194 200 202 204 206 212 214 216 218 220 224 226 228 230 Acting surface sealant or sealant top side increase Layered interconnect structure Insulation or protective layer Conductive layer Resistance layer Insulation layer Insulation or protective layer Conductive layer Insulation or protective layer Bottom side build-up interconnect structure Conductive layer Insulation or protective layer Ball or bump Semiconductor element Conductive layer Conductive layer Conductive column semiconductor die or member metal bump function surface sealant or sealant compound top side build-up Even the structure of the insulating layer or the protective 42232201101399

234 conductive layer 236 insulating or protective layer 240 bottom side build-up interconnect structure 242 conductive layer 244 resistive layer 246 insulating layer 248 insulating or protective layer 250 conductive layer 252 insulating or protective layer 254 ball or bump 260 semiconductor element 262 bottom Side-growth interconnect structure 264 Conductive layer 266 Resistive layer 268 Insulating layer 270 Protective layer 272 Conductive layer 274 Insulating or protective layer 278 Conductive post or rod 280 Semiconductor die or member 284 Metal bump 288 Sealant or sealant compound 290 top side build-up interconnect structure 292 insulation or protective layer 43 201101399 294 conductive layer 296 insulation or protective layer 298 conductive layer 300 insulation or protective layer 302 sphere or bump 304 semiconductor die or member 306 metal bump 308 bottom Filling material 44

Claims (1)

201101399 VII. Applicable Patent Range: κ A method for manufacturing a semiconductor component, comprising: providing a temporary carrier; forming a first conductive layer on the temporary carrier; forming a bump under metallization on the temporary carrier (UBM a layer, the under bump metallization layer is fixed at a relative position of the first conductive layer; forming a conductive pillar on the first conductive layer; mounting a semiconductor die to the under bump metallization layer to the half Leading the body grain alignment corresponding to the conductive pillar; depositing a sizing agent on the semiconductor die and around the conductive pillar, the bump down to the genus layer blocking the semiconductor die during deposition of the sealant a π-flavored f-f carrier; a first interconnect structure formed on the first surface of the sealant; and a second surface formed on the sealant opposite the first interconnect structure In the second interconnect structure, the first and the first-stones are electrically connected. The method of claim 1, wherein the first interconnect structure comprises an integrated passive component electrically connected to the conductive pillar. 45 201101399 stacking a plurality of semiconductor components; and electrically connecting the semiconductor components through the conductive pillars. The method of claim 1, wherein the forming the first interconnect structure comprises: forming a second conductive layer electrically connected to one of the conductive pillars; forming a first insulating layer on the first conductive layer And forming a third conductive layer on the first conductive layer, and the third conductive layer is electrically connected to the conductive pillar. 7. A method of fabricating a semiconductor device, comprising: providing a temporary carrier; forming a first conductive layer on the temporary carrier; forming a sub-bump metallized (10) M) layer on the temporary carrier, the under bump metallization a layer is fixed at a relative position of the first conductive layer; a conductive pillar is formed on the first conductive layer; and a semiconductor die is mounted to the under bump metallization layer to align the semiconductor die to the conductive And depositing a glue around the conductive pillar to remove the temporary carrier on the semiconductor die; forming a first interconnect structure on the first surface of the sealant; and opposing the interconnect structure The second surface of the sealant is formed - the first interconnect structure, the poor whistle _ Ώ λ* is electrically connected. ° The second interconnect structure is a method of traversing the conductive body, wherein the first interconnecting node is a passive component. The method of item 7, further comprising: removing the plane of the first interconnect structure. The method of claim 10, wherein the semiconductor crystal which is partially sealed in the sealant is removed 9. If the scope of the patent application includes electrically connecting to the conductive material. 10. As part of the scope of the patent application, the sealant is formed for use in the present invention. In the method of claim 7, the method includes stacking a plurality of semiconductor components; and electrically connecting the semiconductor components through the conductive pillars. 13. The method of claim 7, wherein forming the interconnect structure comprises: forming a second conductive layer electrically connected to one of the conductive pillars; forming a first insulating layer on the first conductive layer; A third conductive layer is formed on the second conductive layer, and the first conductive layer is electrically connected to the conductive pillar. 14. A method of fabricating a semiconductor device, comprising: forming a first interconnect structure comprising a wettable contact pad and an under bump metallization layer (UBM) fixed at opposite locations of the contact pads; Forming a conductive pillar on the wettable contact pad of the first interconnect structure; mounting a first semiconductor component to the under bump metallization layer to align the semiconductor component to the conductive pillar, a layer of glue is deposited on the semiconductor member and around the conductive pillar; and 201101399 is formed on the second surface of the encapsulant opposite the first interconnect structure - the second interconnect structure 'the first and second interconnects The structure is electrically connected through the conductive pillars. 15. The method of claim 14, wherein the under bump metallization layer is fixed to the opposite position of the conductive pillar and prevents displacement of the semiconductor component during deposition of the (IV) agent. 16. The method of claim 14, wherein the first interconnect structure comprises an integrated passive component electrically coupled to the one of the conductive pillars. The method of claim 16, wherein the integrated passive component comprises a capacitor, a resistor or an inductor. 18. The method of claim 14, further comprising mounting a second semiconductor component of the first interconnect structure opposite the first semiconductor component. 19. The method of claim 14, further comprising: removing a portion of the sealant to form a plane for the second interconnect structure. 20. The method of claim 14, further comprising: stacking a plurality of semiconductor components; and electrically connecting the semiconductor components through the conductive pillars. 21. A semiconductor device, comprising: a first conductive layer; an under bump metallization (UBM) layer fixed to a first conductive layer; a conductive pillar formed on the first conductive layer; A semiconductor component is mounted to the under bump metallization layer to align the semiconductor wafer to the conductive pillar. A glue is deposited on the semiconductor die and around the conductive pillar a first interconnect structure formed on the first surface of the encapsulant; and a second interconnect structure formed on the second surface of the encapsulant opposite the first interconnect structure, the first The second interconnect structure is electrically connected through the conductive pillars. 22. The semiconductor component of claim 21, wherein the under bump metallization layer prevents the semiconductor component from being clamped during deposition of the sealant. 23. The semiconductor component of claim 21, wherein the first, vertical velocity structure comprises an integrated passive element electrically connected to the conductive pillar: 24. The semiconductor component of claim 21, wherein the second vertical structure comprises an integrated passive element 25 electrically connected to the conductive pillar. The semiconductor component of claim 21, further comprising The conductive pillars are electrically connected to a plurality of stacked semiconductor components. 〇 Eight, schema: (such as the next page) 49