201101323 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種電子元件之佈局結構及一種定址以 • 偵測電子元件之方法。特定言之，本發明係關於一種電子元 件之高密度佈局結構，以及在此電子元件之高密度佈局結構 中所使用之一種使用定址技術以偵測電子元件之方法。 0 【先前技術】 在標準的半導體製程中，為了要評估每個製程的效率以 及確認元件在通過製程後的性能；會對晶圓進行晶圓接受度 測試（WAT, Wafer Acceptance Test)。晶圓接受度測試包含對 分布於晶粒週邊區域之測試墊進行電性測試。晶圓接受度測 試的主要目的，是要確認半導體製程的穩定性及增進產品良 率。在晶圓接受度測試下，可確保晶圓某個程度上的品質與 〇穩定性。 為了能順利進行晶圓接受度測試，分布於晶粒週邊區域 的測試鍵（test key )扮演著關鍵性的角色。為此，在電子元201101323 VI. Description of the Invention: [Technical Field] The present invention relates to a layout structure of an electronic component and a method for addressing the electronic component. In particular, the present invention relates to a high-density layout structure of an electronic component, and a method of using the addressing technique to detect an electronic component used in the high-density layout structure of the electronic component. 0 [Prior Art] In the standard semiconductor process, in order to evaluate the efficiency of each process and confirm the performance of the components after passing the process; the Wafer Acceptance Test (WAT) is performed on the wafer. Wafer acceptance testing involves electrically testing test pads distributed around the perimeter of the die. The main purpose of the wafer acceptance test is to confirm the stability of the semiconductor process and to improve product yield. Under wafer acceptance testing, it ensures a certain degree of quality and stability of the wafer. In order to successfully perform wafer acceptance testing, the test key distributed in the periphery of the die plays a key role. To this end, in the electronic element
.J . I 件之佈局結構中，即會設計有‘電子元件電連接之測試鍵。 測試鍵通常位於晶粒之間的切割道（scribe line)上，經由測 試墊（pad)而與電子元件電連接。測試鍵之佈局形式通常 與電子元件的電極數量有關。視乎電子元件的電極數量多 寡’ 一個電子元件可能與2_4個測試塾電連接。 201101323 第1圖例不一種目前已知之測試鍵配合電子元件之佈局 形式。電子元件10分別與4個，測試墊21/22/23/24電連接。 在測试墊的有限面積中，晶圓接受度測試通常在一排（Hnear .section)中，其可為行亦可以為列，最多允許安排如個測 .試墊，所以每一排中最多允許安排5個電子元件1〇。若是電 子70件1G可以允許有共極時，電子元件的數量最多還可以 加倍。現在假設測試鍵的尺寸為154〇微米（#m) * 52 6 = 〇 51004 則每個電子元件10平均所佔有的面積為51004/5 =16200.8 μιη2。 為了降低生產成本’晶圓中電子元件的臨界尺寸日漸縮 小’進而導致測試鍵區域的可南兔積也曰益減小，而漸漸感 到有所不足。如何提出一種高密^電子元件之佈局結構，以 更經濟的方式容置更多待測電子元件並使用測試鍵區域中 曰益減小的可用面積，成為本領域明顯的當務之急。 〇 【發明内容】In the layout structure of the . I. I will design a test key for the electrical connection of the electronic components. The test keys are typically located on the scribe line between the dies and are electrically connected to the electronic components via a test pad. The layout of the test keys is usually related to the number of electrodes of the electronic components. Depending on the number of electrodes in the electronic component, an electronic component may be electrically connected to 2 to 4 test ports. 201101323 The first illustration is not a form of layout of the currently known test keys with electronic components. The electronic components 10 are electrically connected to four test pads 21/22/23/24, respectively. In the limited area of the test pad, the wafer acceptance test is usually in a row (Hnear.section), which can be either a row or a column. It is allowed to arrange up to a test pad, so the maximum is in each row. It is allowed to arrange 5 electronic components 1〇. If the electronic 70 piece 1G can allow a common pole, the number of electronic components can be doubled at the most. Now assume that the size of the test key is 154 〇 micron (#m) * 52 6 = 〇 51004, and the average area occupied by each electronic component 10 is 51004/5 =16200.8 μιη2. In order to reduce the production cost, the critical dimension of electronic components in the wafer is becoming smaller and smaller, which in turn leads to a reduction in the reliability of the test button area, and gradually becomes insufficient. How to propose a high-density electronic component layout structure, to accommodate more electronic components to be tested in a more economical manner and to use the available area in the test key area to reduce the benefits, has become an obvious priority in the field. 〇 【Contents】
本發明於是提出-種高密度電子元件之佈局結構。本發 明之高密度電子元件佈局結構’可以以更經濟的方式充分^ 用測試鍵區域中有限的面積’而香相同面積中容納更多的電 子元件以及對應的測k墊。本發萌又提出一種在此高密度電 子兀件之佈局結構中，使用定址技術以偵測電子元件之S 法。本發日狀方法可以箱㈣中之t子元件在某 的品質與穩定性。 X 4 201101323 本發明首先提出一種電子元件之佈局結構，包含排列成 一矩陣之M*N個電子元件；位於矩陣之第一側邊上之第一 測試墊群，且矩陣同排之所有電子元件均與第一測試墊群中 ' ：' '',ί. 之一對應測試墊電連接；以及位於矩陣之第二側邊上之第二 測試墊群，且矩陣同排之所有電子元件均與第二測試墊群中 之一對應測試墊電連接。於本發明一實施例中，第一測試墊 群與第二測試墊群係分別與一源極、一汲極、一閘極與一基 0 極之其中一者電連接。 本發明又提出一種定址以偵測電子元件之方法。首先， 提供一佈局結構，其包含排列成一矩陣之Μ*Ν個電子元件、 位於矩陣之第一側邊上之第一測第墊群，且矩陣同排之所有 , -. ν: 電子元件均與第一測試墊群中灰―對應測試墊電連接、以及 I · 位於矩陣之第二側邊上之第二測i式墊群，且矩陣同排之所有 電子元件均與第二測試墊群中之一對應測試墊電連接。其 次，電連接第一測試墊群中之對應測試墊，以活化矩陣同排 Ο 之所有電子元件。然後，電連接第二測試墊群中之對應測試 墊，以定址而選出一特定電子元件。於是，偵測到特定電子 之元件。於本發明另一實施例中，佈局結構更包含位於矩陣 之第三側邊上之第三測試墊群。且第一測試墊群、第二測試 墊群與第三測試墊群皆不相同。‘ 【實施方式】 本發明首先提供一種高密度電子元件之佈局結構。本發 5 201101323 明之高密度電子元件佈局結構，可以更經濟的方式充分使用 測試鍵區域中有限的面積，而在相同面積中容納更多的電子 元件以及對應的測試墊來進行晶圓接受度測試。第2A、2B、 2C圖例示本發明一種高密度電子元件佈局結構之示意圖。 請參閱第2A圖，本發明電子元件之佈局結構2〇〇，包含M*N 個電子元件206，其排列成一矩陣形式、位於矩陣2〇7 之第一側邊201上之第一測試墊群21〇以及位於矩陣2〇7之 〇 第二側邊上202之第二測試墊群220。視情況需要，本發明 電子元件之佈局結構200還可以包含位於矩陣207之第三側 邊203上之第三測試墊群230以及/或是位於矩陣207之第四 側邊204上之第四測試墊群240。 在矩陣207中，M*N個電子元件206可以排列成Μ行 以及Ν列。Μ與Ν分莂為一整也。Μ與Ν可以相同，也可 以不相同。在一實施態樣中，位於矩陣207之第一侧邊201 q 上之第一測試墊群210中之任一測試墊211，即與Μ行中某 一行之所有電子元件206電連接。或是，Ν列中某一列之所 有電子元件206，會與位於矩陣207之第二側邊202上第二 測試墊群220之中，對應此列之某一測試墊221電連接。換 言之，同排之電子元件206可以視為共用同一極。任一測試 墊群中之測試墊數量’通常不會小於矩陣207的行數或是列 數，而可用作備份（redundancy)之用。 ’.1 ' / 如果電子元件206是一種雙丨亟形式之電子元件，請參閱 第2B圖，例如電阻，則各電子元件206之兩極即分別與第 6 201101323 一測試墊群210中之某一測試墊211，以及第二測試墊群2 2 〇 之中之某一測試墊221電連接。如果電子元件2〇6是一種三 極形式之電子元件，例如電晶體，則各電子元件2〇6之三極 即分別與第一測試墊群210中之某一測試墊211、第二測試 墊群220之中之某一測試墊221以及第三測試墊群23〇之中 之某一測試墊231電連接，或是浮置（floating)。此時，第 三測試墊群230與第四測試墊群240中任何一者即可以視為 〇 偽測試墊群，或是可以不存在。第2圖例示雙極形式之電子 元件，第二測试塾群230為偽測試塾群，第四測試塾群240 視為不存在。另一方面’請參閱第2C圖，如果電子元件 206是一種四極形式之電子元件，則各電子元件2〇6之四極 即分別與第一測試墊群21〇中之某一測試墊211、第二測試 墊群220之中之某一測試墊221 >第三測試墊群23〇之中之 某一測試墊231以及策四測試墊一 240之中之某一測試墊 q 241電連接。電子元件206因此奇能為雙極形式之電子元 件、二極形式之電子元件、或是四極形式之電子元件。第2d 圖例示四極形式之電子元件。 例如’如果電子元件206為一種四極形式之電子元件， 而包含源極251、汲極252、閘極253與基極254時，第一 測試墊群210、第二測試墊群220、第三測試墊群230與第 四測試墊群240即分別與各電子元件206之源極251、汲極 252、閘極253與基梃254之其;中一者電連接。無論電子元 • 件206有多少極’余一昶試#群21〇、第二測試墊群220、 201101323 視情況需要之第三賴墊群23G與視情況需要之第四測試塾 群240白不相同。當電子元件為二極形式之電子元件時，第一 測試墊群210與第二測試塾群22〇中，所有測試墊2ii、221之總數 為選自M+N、2N和2M之其中之-。#電子元件為三極形式之 電子元件時，第-測試墊群训、第二測試墊群22〇與第三測試墊 群现中’所有測試塾加⑵卜加之總數為選自胳㈣口）^^ 之其中之-。當電子元件為四極形式之電子元件時，第一測試塾 〇群210、第二測試塾群220、第三測試塾群23〇中與第四測試塾群 240中所有測試墊2U、22卜2M、241之總數為2(m+n)。本發明 電子元件之佈局結構200中之導線，可以以彼此絕緣的方式 交錯排列。例如，使用半導體製程中習知之多層金屬層（M1， M2 ... Μη)和金屬插塞，來作為電子元件之佈局結構2〇〇中 之導線和測試塾。 因為第一測試墊群210、第二測試墊群22〇、視情況需 ❹要之第二測試墊群230與視情況需要之第四測試墊群24〇會 分別位於矩陣207之四邊，因此各別測試墊群間之相對關係 可能彼此垂直或是平行，端視各別測試墊群間之相對位置而 訂。 由於電子元件206可以視為共用同一極，本發明之高密 度電子元件佈局結構，可以更經濟的方式充分使用測試鍵區 域中有限的面積，而在相同面積中容納更多的電子元件以及 對應的測試墊。例如，測試鍵的尺寸為154〇 Am * 154〇 = 2371600 /zm2，但是每一測試塾群仍然是由2〇個測試墊所組 201101323 成’也就是在任一排中’仍然只允許最多安排20個測試墊， 所以總共有400個電子元件206。每個電子元件206平均所 佔有的面積為2371600/400 = 5929 jitm2。相較習知技藝之佈 局，每個電子元件206平均所佔有的面積只有原來的73%而 已。 本發明又提供一種定址以偵測電子元件之方法。第3-5 圖例示本發明定址以偵測電子光丨袢之方法。如第3圖所示， 〇 首先’提供一佈局結構300，其包含排列成一矩陣307之 M*N個電子元件306。佈局結構3〇〇中另外還包含位於矩陣 307之第一侧邊301上之第一測試墊群31()以及位於矩陣307 之第二侧邊上302之第二測試墊群32〇。視情況需要，本發 明電子元件之佈局結構3〇〇還可以包含位於矩陣307之第三 側邊303上之第三測試墊群33()以及/或是位於矩陣3〇7之第 四側邊304上之第四測試墊群34〇。 ❹ 在矩陣307中，個電子元件306可以排列成Μ行 以及Ν列。Μ與Ν分別為一整數。μ與Ν可以相同，也可The present invention thus proposes a layout structure of high-density electronic components. The high-density electronic component layout structure of the present invention can fully utilize the limited area in the test key area in a more economical manner, while accommodating more electronic components and corresponding k-pads in the same area. In the layout structure of the high-density electronic component, the S-method of using the addressing technique to detect electronic components is proposed. The present day method can be used for the quality and stability of the t sub-components in the box (4). X 4 201101323 The present invention firstly proposes an arrangement structure of electronic components, comprising M*N electronic components arranged in a matrix; a first test pad group located on a first side of the matrix, and all electronic components in the same row of the matrix Corresponding to one of the first test pad group ':' '', ί. corresponding to the test pad; and the second test pad group on the second side of the matrix, and all the electronic components in the same row of the matrix are One of the two test pad groups corresponds to the test pad electrical connection. In an embodiment of the invention, the first test pad group and the second test pad group are electrically connected to one of a source, a drain, a gate and a base 0, respectively. The present invention further provides a method of addressing to detect electronic components. First, a layout structure is provided, which comprises a plurality of electronic components arranged in a matrix, a first test pad group located on a first side of the matrix, and the matrix is in the same row, -. ν: electronic components are Electrically connected to the ash-corresponding test pad in the first test pad group, and I·the second i-pad group on the second side of the matrix, and all the electronic components in the same row of the matrix are combined with the second test pad group One of them corresponds to the test pad electrical connection. Secondly, the corresponding test pads in the first test pad group are electrically connected to activate all the electronic components of the matrix. Then, the corresponding test pads in the second test pad group are electrically connected to address a particular electronic component. Thus, components of a particular electron are detected. In another embodiment of the invention, the layout structure further includes a third test pad group on the third side of the matrix. And the first test pad group, the second test pad group and the third test pad group are all different. ‘Embodiment】 The present invention first provides a layout structure of high-density electronic components. The high-density electronic component layout structure of the present invention 5 201101323 can fully utilize the limited area in the test key area in a more economical manner, and accommodate more electronic components and corresponding test pads in the same area for wafer acceptance test. . 2A, 2B, and 2C are views showing a layout structure of a high-density electronic component of the present invention. Referring to FIG. 2A, the layout structure of the electronic component of the present invention includes M*N electronic components 206 arranged in a matrix form, and the first test pad group on the first side 201 of the matrix 2〇7 21〇 and a second test pad group 220 located on the second side of the matrix 2〇7. The layout structure 200 of the electronic component of the present invention may further include a third test pad group 230 on the third side 203 of the matrix 207 and/or a fourth test on the fourth side 204 of the matrix 207, as the case requires. Pad group 240. In matrix 207, M*N electronic components 206 can be arranged in a row and in a matrix. Μ and Ν are divided into a whole. Μ and Ν can be the same or different. In one embodiment, any of the first test pad groups 210 on the first side 201q of the matrix 207 is electrically coupled to all of the electronic components 206 of a row in the bank. Alternatively, all of the electronic components 206 in a column of the array will be electrically connected to a test pad 221 corresponding to the column in the second test pad group 220 located on the second side 202 of the matrix 207. In other words, the electronic components 206 in the same row can be considered to share the same pole. The number of test pads in any test pad group' is usually not less than the number of rows or columns of the matrix 207 and can be used as a redundancy. '.1 ' / If the electronic component 206 is an electronic component in the form of a double turn, please refer to FIG. 2B, for example, a resistor, and then the two poles of each electronic component 206 are respectively associated with a test pad group 210 of the sixth 201101323 The test pad 211, and one of the second test pad groups 2 2 〇 are electrically connected. If the electronic component 2〇6 is a three-pole form of electronic component, such as a transistor, the three poles of each electronic component 2〇6 are respectively associated with one of the first test pad group 210 and the second test pad. One of the test pads 221 and one of the third test pad groups 23 of the group 220 are electrically connected or floated. At this time, any one of the third test pad group 230 and the fourth test pad group 240 may be regarded as a pseudo test pad group or may not exist. Fig. 2 illustrates an electronic component in the form of a bipolar, the second test group 230 is a pseudo test group, and the fourth test group 240 is considered to be absent. On the other hand, please refer to FIG. 2C. If the electronic component 206 is a quadrupole electronic component, the four poles of each electronic component 2〇6 are respectively associated with one of the first test pad groups 21〇, 211 One of the test pads 221 > one of the third test pad groups 23 and one of the test pads 241 of the fourth test pad group 241 are electrically connected. The electronic component 206 is thus a bipolar electronic component, a bipolar electronic component, or a quadrupole electronic component. Figure 2d illustrates an electronic component in the form of a quadrupole. For example, if the electronic component 206 is a quadrupole electronic component including the source 251, the drain 252, the gate 253 and the base 254, the first test pad group 210, the second test pad group 220, and the third test The pad group 230 and the fourth test pad group 240 are electrically connected to one of the source 251, the drain 252, the gate 253 and the base 254 of each electronic component 206, respectively. No matter how many poles the electronic component 206 has, the remaining test group 21, the second test pad group 220, and the 201101323, depending on the situation, the fourth test group 23G is different from the fourth test group 240 as needed. When the electronic component is a two-pole electronic component, the total number of all test pads 2ii, 221 in the first test pad group 210 and the second test pad group 22 is selected from the group consisting of M+N, 2N, and 2M- . #Electrical components are three-pole form of electronic components, the first test pad group training, the second test pad group 22〇 and the third test pad group are in the middle of the 'all tests plus (2) the total number is selected from the four (four) mouth) ^^ Among them -. When the electronic component is a quadrupole electronic component, all the test pads 2U, 22, and 2M in the first test group 210, the second test group 220, the third test group 23, and the fourth test group 240 The total number of 241 is 2 (m+n). The wires in the layout structure 200 of the electronic component of the present invention may be staggered in an insulated manner from each other. For example, a conventional multilayer metal layer (M1, M2 ... Μη) and a metal plug in a semiconductor process are used as the wires and test pads in the layout structure of the electronic component. Because the first test pad group 210, the second test pad group 22, the second test pad group 230 and the fourth test pad group 24 as needed, respectively, are located on the four sides of the matrix 207, respectively The relative relationship between the test pad groups may be perpendicular or parallel to each other, depending on the relative position between the individual test pad groups. Since the electronic component 206 can be regarded as sharing the same pole, the high-density electronic component layout structure of the present invention can fully utilize the limited area in the test key area in a more economical manner, and accommodate more electronic components and corresponding ones in the same area. Test pad. For example, the size of the test button is 154〇Am * 154〇= 2371600 /zm2, but each test group is still composed of 2〇 test pads 201101323 into 'that is, in any row' still only allows a maximum of 20 A test pad, so there are a total of 400 electronic components 206. Each electronic component 206 occupies an average area of 2371600/400 = 5929 jitm2. Compared to the prior art, each electronic component 206 occupies an average of 73% of the original area. The present invention also provides a method of addressing to detect electronic components. Figures 3-5 illustrate a method of addressing the invention to detect an electronic stop. As shown in Fig. 3, 〇 first provides a layout structure 300 comprising M*N electronic components 306 arranged in a matrix 307. The layout structure 3 further includes a first test pad group 31() on the first side 301 of the matrix 307 and a second test pad group 32〇 on the second side 302 of the matrix 307. The layout structure 3 of the electronic component of the present invention may further include a third test pad group 33() on the third side 303 of the matrix 307 and/or a fourth side of the matrix 3〇7, as occasion demands. The fourth test pad group 34 on 304. ❹ In matrix 307, individual electronic components 306 can be arranged in a row and in a row. Μ and Ν are each an integer. μ and Ν can be the same, or
I 以不相同。在一實施態樣中，位於矩陣307之第一側邊301 上之第一測試墊群31〇中之任一測試墊311，即與Μ行中某 —行之所有電子元件3〇6電連接。或是，Ν列中某一列之所 有電子το件306 ’會與位於矩陣3〇7之第二側邊3〇2上第二 測減塾群320之中，對應此列之某一測試墊32ι電連接，視 情況需要之第三測試墊群33〇以及第四測試墊群34〇亦同。 換§之，同排之電子元件3〇6可以視為共用同一極。任一測 201101323 試墊群中之測試墊數量，通常不會小於矩陣307的行數或是 列數，而可用作備份之用。 電子元件306可能為雙極形式之電子元件、三極形式之 電子元件、或是四極形式之電子元件。如果電子元件3〇6是 一種雙極形式之電子元件，例如電阻，則各電子元件3〇6之 兩極即分別與第一測試墊群310中之某一測試墊31〗，以及 第二測試墊群320之中之某一測試墊321電連接。如果電子 〇 元件3〇6是一種三極形式之電子元件，例如電晶體，或是一 種四極形式之電子元件，則各電子元件3〇6之各極即分別與 測試墊群中之某一測試墊電連接，或是浮置。此時，視情況 需要第三測試墊群330與第四測試墊群340中任何一者可以 為偽測試墊群，或是可以不存在。第3圖例示四極形式之電 子元件。 如果電子元件306為一種多極形式之電子元件，而包含 Q 源極351、沒極352、閘極353及/或基極354時，第一測試 墊群310、第二測試墊群32〇、第三測試墊群33〇與第四測 試墊群340即分別與各電子元4 306之源極35卜汲極352、 間極353及/或基極354之其中一者電連接。無論電子元件 306有多少極，第一測試墊群31 〇、第二測試墊群、第三 測試墊群330與第四測試墊群34〇皆不相同。當電子元件為 二極形式之電子元件時，第一測試墊群310與第二測試墊群32〇 中，所有測試墊31卜321之總數為選自m+N、2N和2M之其中之 。當電子兀件為三極形式之電子元件時，第一測試墊群3〗〇、 201101323 第二測試墊群320與第三測試墊群330中，所有測試墊311、32l、 331之總數為選自2M+N和2N+M之其中之一。當電子元件為四 極形式之電子元件時，第一測試墊群310、第二測試墊群320、 第三測試墊群330中與第四測試墊群340中所有測試墊311、321、 331、341之總數為2(M+N)。本發明電子元件之佈局結構300 中之導線’可以以彼此絕緣的方式交錯排列。例如，使用半 導體製程中習知之多層金屬層（Ml, M2…Μη)和金屬插 Ο 塞’來作為電子元件之佈局結構300中之導線和測試墊。因 為第一測試墊群310、第二測試墊群320、視情況需要之第 三測試墊群33〇與視谱況需要‘ϋ四測試墊群340會分別位 於矩陣307之四邊’因此各別測試墊群間之相對關係可能彼 此垂直或是平行，端視各別測試墊群間之相對位置而訂。 其次’如第4圖所示，電連接第一測試墊群310中之某 一對應測試墊311，以活化矩陣307同排之所有電子元件 ❹ 306。此時’祇有被選出的同排電子元件306才會被活化。 然後’如第5圖所示，電連接第二測試墊群320中之某一對 應測試墊321，即可以定址而選出一特定電子元件306,。由 ν ；· 於先前所被選出的同排電子元办1〇6係各別且獨立地電連接 至第二測試墊群320中之某一對應測試墊321，因此第二測 试墊群320中之某一對應測試塾321被電連接時，同排電子 元件306中祇有某一個特定的電子元件306,會被影響。於 是’特定的電子之元件306’即被偵測到。如果電子元件306 為一種三極或是四極形式之電子元件，可以使用類似之步驟 201101323 開啟並偵測任意一個特定的電子，元件，例如，電連接第三測 . ' ； 試墊群330中之某二對應測試墊，及/或電連接第四測試墊群 340中之某一對應測試墊以偵測一特定電子元件，而不影響 相同矩陣中所有其他的電子元件。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 〇 【圖式簡單說明】 第1圖例示一種自前已知之須j試鍵配合電子元件之佈局 形式。 ' 第2A/2B/2C/2D圖例示本發明一種高密度電子元件佈 局結構之示意圖。 第3-5圖例示本發明定址以偵測電子元件之方法。 〇 【主要元件符號說明】 10電子元件 21/22/23/24 測試墊 200, 300佈局結構 w 201,301第一側邊 202, 302第二側邊 203, 303第三侧邊 204, 304第四側邊 12 201101323 206, 306, 306’電子元件 207, 307 矩陣 210, 310第一測試墊群 211, 221，231, 241，311，321, 331，341 測試墊 220, 320第二測試墊群 230, 330第三測試墊群 240, 340第四測試墊群 q 251，351 源極 252, 352 汲極 253, 353 閘極 254, 354 基極I is not the same. In one embodiment, any one of the first test pad groups 31 on the first side 301 of the matrix 307 is electrically connected to all of the electronic components 3〇6 of a row in the bank. . Alternatively, all of the electrons τ' of a column in the array will be in the second measurement group 320 on the second side 3〇2 of the matrix 3〇7, corresponding to a test pad 32 of the column. The electrical connection, as the case requires, the third test pad group 33〇 and the fourth test pad group 34〇 are also the same. In other words, the electronic components 3〇6 in the same row can be regarded as sharing the same pole. The number of test pads in the 201101323 test pad group is usually not less than the number of rows or columns of the matrix 307, and can be used as a backup. The electronic component 306 may be an electronic component in the form of a bipolar, an electronic component in the form of a three-pole, or an electronic component in the form of a quadrupole. If the electronic component 3〇6 is a bipolar electronic component, such as a resistor, the two poles of each electronic component 3〇6 are respectively associated with a test pad 31 of the first test pad group 310, and the second test pad. One of the test pads 321 of the group 320 is electrically connected. If the electronic germanium component 3〇6 is a three-pole form of electronic component, such as a transistor, or a quadrupole form of electronic component, the respective poles of each electronic component 3〇6 are respectively tested with a test pad group. The pads are electrically connected or floating. At this time, any one of the third test pad group 330 and the fourth test pad group 340 may be a dummy test pad group as needed, or may not exist. Figure 3 illustrates an electronic component in the form of a quadrupole. If the electronic component 306 is a multi-pole electronic component including the Q source 351, the gate 352, the gate 353, and/or the base 354, the first test pad group 310, the second test pad group 32, The third test pad group 33A and the fourth test pad group 340 are electrically connected to one of the source 35 dipole 352, the interpole 353 and/or the base 354 of each of the electronic components 4 306, respectively. Regardless of the number of poles of the electronic component 306, the first test pad group 31, the second test pad group, the third test pad group 330, and the fourth test pad group 34 are all different. When the electronic component is a two-pole electronic component, the total number of all test pads 31 321 in the first test pad group 310 and the second test pad group 32 is selected from the group consisting of m+N, 2N and 2M. When the electronic component is a three-pole electronic component, the total number of all the test pads 311, 32l, 331 is selected in the first test pad group 3, 201101323, the second test pad group 320 and the third test pad group 330. One of 2M+N and 2N+M. When the electronic component is a quadrupole electronic component, the first test pad group 310, the second test pad group 320, the third test pad group 330, and all the test pads 311, 321, 331 and 341 of the fourth test pad group 340 The total number is 2 (M+N). The wires ' in the layout structure 300 of the electronic component of the present invention may be staggered in an insulated manner from each other. For example, a conventional multilayer metal layer (M1, M2...Μ) and a metal plug ’ are used as the wires and test pads in the layout structure 300 of the electronic component. Because the first test pad group 310, the second test pad group 320, the third test pad group 33 as needed, and the visual condition need 'four test pad groups 340 will be located on the four sides of the matrix 307 respectively', so the respective tests The relative relationship between the groups of pads may be perpendicular or parallel to each other, depending on the relative position between the individual test pad groups. Next, as shown in Fig. 4, one of the corresponding test pads 311 in the first test pad group 310 is electrically connected to activate all of the electronic components 306 in the same row of the matrix 307. At this time, only the selected row of electronic components 306 will be activated. Then, as shown in Fig. 5, a corresponding one of the test pads 321 of the second test pad group 320 is electrically connected, i.e., a specific electronic component 306 can be selected. The first test pad group 320 is electrically and independently connected to the corresponding test pad 321 of the second test pad group 320 by ν; When one of the corresponding test pads 321 is electrically connected, only one of the specific electronic components 306 in the same row of electronic components 306 is affected. The 'specific electronic component 306' is then detected. If the electronic component 306 is a three- or four-pole electronic component, a similar step 201101323 can be used to turn on and detect any particular electronic component, for example, electrically connected to the third test. One of the two corresponding test pads, and/or one of the corresponding test pads of the fourth test pad group 340 is electrically connected to detect a particular electronic component without affecting all other electronic components in the same matrix. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. 〇 [Simple description of the drawing] Fig. 1 illustrates a layout form of the electronic component that has been known from the previous test. The 2A/2B/2C/2D diagram illustrates a schematic diagram of a high-density electronic component layout structure of the present invention. Figures 3-5 illustrate a method of addressing the invention to detect electronic components. 〇 [Main component symbol description] 10 electronic components 21/22/23/24 test pad 200, 300 layout structure w 201, 301 first side 202, 302 second side 203, 303 third side 204, 304 fourth side Side 12 201101323 206, 306, 306' electronic component 207, 307 matrix 210, 310 first test pad group 211, 221, 231, 241, 311, 321, and 331, 341 test pad 220, 320 second test pad group 230, 330 third test pad group 240, 340 fourth test pad group q 251, 351 source 252, 352 drain 253, 353 gate 254, 354 base
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