201044269 六、發明說明： 【發明所屬之技術領域】 本發明係關於 本發明係關於/ 一種微處理器及其微運算執行方法。具體而言’ ㈣於被阻_態下可先行執行之微處 理器及其微運算執行方法 【先前技術】 由於科技的進步，電腦已成為人們的生活中不^缺少的工具。 ^ ,外卢搜盔古要核心’其直接影響電腦 在電腦的硬體設備中，微處理裔為一主要杨 的執行速度。因此，隨著需微處理器處理的資料量日I龐大’人 們對於微處理器之執行速度的要求也越來越高。近成年微處里°。 的設計蓬勃發展，相對於依序（in-order)執行之微處理器八有 亂序（out-of-〇rder)執行功能的微處理器設計’已大幅地提升執 行速度，故越來越受到人們之青睞，成為微處理設計之主流。 請參閱第1圖，其係為一傳統具有亂序執行功能之微處理器1。 此微處理器1包含一解碼器1〇1、一暫存器集合1〇3、一微運算槽 W5、一派遣單元1〇7、一執行單元1〇9以及一重排序緩衝器Π1。 解碼器101將電腦指令解碼為微運算1〇2。微運算槽1〇5自解碼器 1(>ι接收微運算102以及自暫存器集合1〇3讀取微運算1〇2之運算 元104’並暫存微運算1()2以及運算元刚。 微，异102及運算元1()4皆已讀入並暫存於微運算槽1〇5後， 加^ ( 1〇7將微運算102及運算元HM派遣至執行單元109。需 _者於派遣至執行單元109之前，微運算102係處於一 執仃狀態，但派遣至執行單元日寺，微運算脱可處於一 201044269 亂序執行狀態。簡言之，派遣單元1〇7派遣微運算102時，僅考 慮微運算102及其運算元104是否皆已暫存於微運算槽1〇5，不考. 慮於該時刻派遣微運算1〇2是否會造成寫入後寫入危障。 執行單元109接收微運算1〇2及其運算元後，執行微運算丨〇2， 並產生運算結果106’然後將運算結果丨〇6將被存入重排序緩衝器 (Re-Order Buffer，ROB) lu並前饋至微運算槽105，以作為暫存 於微運算槽1G5之-具相依關係之微運算之運算元。換言之，前201044269 VI. Description of the Invention: [Technical Field] The present invention relates to a microprocessor and a micro-operation execution method thereof. Specifically, (4) Microprocessors and their micro-operation execution methods that can be executed first in the blocked state. [Prior Art] Due to advances in technology, computers have become a tool that people do not lack. ^, the outer Lu search helmet ancient core 'it directly affects the computer In the computer's hardware equipment, the micro-processing is a major Yang's execution speed. Therefore, as the amount of data that needs to be processed by the microprocessor is huge, the requirements for the execution speed of the microprocessor are increasing. Near adulthood. The design is booming, and the microprocessor design with out-of-〇rder execution function in parallel with the in-order execution has greatly improved the execution speed, so more and more It has been favored by people and has become the mainstream of micro-processing design. Please refer to FIG. 1, which is a conventional microprocessor 1 having an out-of-order execution function. The microprocessor 1 includes a decoder 1〇1, a register set 1〇3, a micro-operation slot W5, a dispatch unit 1〇7, an execution unit 1〇9, and a reorder buffer Π1. The decoder 101 decodes the computer instructions into a micro-operation 1〇2. The micro-computing slot 1〇5 reads from the decoder 1 (> i receives the micro-operation 102 and reads the arithmetic unit 104 of the micro-operation 1〇2 from the register set 1〇3 and temporarily stores the micro-operation 1() 2 and the operation After the micro, the different 102 and the operation unit 1 () 4 have been read in and temporarily stored in the micro-operation slot 1 〇 5, add ^ (1 〇 7 to dispatch the micro-operation 102 and the operation element HM to the execution unit 109. Before the dispatch to the execution unit 109, the micro-operation 102 is in a stubborn state, but is dispatched to the execution unit Riji, and the micro-operation can be in a disordered execution state of 201044269. In short, the dispatch unit 1〇7 When the micro-operation 102 is dispatched, it is only considered whether the micro-operation 102 and its arithmetic unit 104 are temporarily stored in the micro-operation slot 1〇5, and it is not considered whether or not the micro-operation 1〇2 is dispatched at this time. The execution unit 109 receives the micro-operation 1〇2 and its operand, performs the micro-operation 丨〇2, and generates the operation result 106', and then stores the operation result 丨〇6 into the reorder buffer (Re-Order). Buffer, ROB) lu and feed forward to the micro-operation slot 105, as a micro-operation operation with a dependency relationship temporarily stored in the micro-operation slot 1G5 Yuan. In other words, before
饋至微^運算槽1 〇 5 宣曾z, 〈運舁結果106對應有微運算1〇2之一辨識碼， 微運算槽105内待讀λ ^ ，入之運算元依據辨識碼，判斷是否使用前饋 回來之運具結果1 〇6 i甘 0為其運算元。接著，重排序緩衝器111暫存 運算結果106，並將運暂u 雙鼻結果106重新排序而成還原成依序執行狀 態之運算結果108。於义 歌後，重排序缓衝器111將運算結果108依序 地寫回至暫存器集合103。Feeding to the micro^ operation slot 1 〇5 Xuan Zeng z, <The operation result 106 corresponds to one of the micro-operations 1〇2 identification code, the micro-operation slot 105 is to be read λ ^, and the input operation element is based on the identification code to determine whether The result of using the tool fed back is 1 〇6 i Gan0 is its operand. Next, the reorder buffer 111 temporarily stores the operation result 106, and reorders the traffic u-nose results 106 to restore the result of the operation to the sequential execution state 108. After the song, the reorder buffer 111 sequentially writes the result 108 back to the scratchpad set 103.
同樣的，任何孰来t U ，、、％此技術者可輕易了解，運算結果108亦會被 前饋至微運算槽1〇5，比 運算結果108亦對應有微運算102之辨識 碼，因此微運算槽】η 内待讀入之運算元可依據辨識碼，判斷是 否使用前饋回來之運曾 '結果108為其運算元。需說明者，微運算 槽105内可能有—刦a 執订順序較低之微運算，此微運算被讀入微運 算槽105之時間點 係介於運算結果106被前饋至微運算槽1〇5 之時間點及運算妹罢， 、°衣“8被前饋至微運算槽1〇5之時間點。因此， §執行H序#χ低之微運算係、讀取前饋回來之運算結果⑽為其運 异元。簡言之，微速 $养所需之運算元不一定是自暫存器集合1〇3 S買取’也可自重排岸炫從D。 辨斤纹衝器111或自執行單元109得到，在此不 201044269 加以贅述。 由於，微處理器1需藉由重排序緩衝器111將亂序執行所產生 的運算結果重新排序以恢復原本的依序執行狀態，因而增加微處 理器1的複雜度及耗電量。另一方面，實現重排序緩衝器111需 使用額外的暫存器及電路，因而增加其硬體需求，使處理器的硬 體成本提高。 综上所述，如何降低處理器的複雜度及耗電量，以及如何縮減 硬體需求同時維持效能而達到成本最小化，為該領域之業者亟需 解決之問題。 【發明内容】 本發明之一目的在於提供一種微處理器，其包含一暫存器集 合、一阻斷單元、一微運算槽以及一派遣單元。該阻斷單元用以 儲存一阻斷狀態旗標及一目前阻斷辨識碼，接收一第一微運算及 一第二微運算，判斷該第一微運算具有一例外條件，以更新該阻 斷狀態旗標為已阻斷，且更新該目前阻斷辨識碼為該第一微運算 之一辨識碼，以及根據該阻斷狀態旗標，設定該第二微運算之一 阻斷辨識碼為該目前阻斷辨識碼。該微運算槽用以自該阻斷單元 接收並暫存該第一微運算及該第二微運算，自該暫存器集合讀取 並暫存與該第一微運算相對應之至少一第一運算元以及與該第二 微運算相對應之至少一第二運算元，並因應已暫存該至少一第二 運算元，設定該第二微運算之一狀態位元為已就緒。該派遣單元， 用以根據該第二微運算之一先行位元、該阻斷辨識碼以及該狀態 位元，判斷該第二微運算係處於一未先行、已阻斷與已就緒之狀 201044269 態，以自該微運算槽派遣該第二微運算以及該至少一第二運算 元，俾該第二微運算可先行執行。 本發明之另一目的在於提供一種用於一微處理器之微運算執行 方法。該微處理器包含一暫存器集合、一阻斷單元、一微運算槽 以及一派遣單元。該阻斷單元儲存一阻斷狀態旗標及一目前阻斷 辨識碼。該微運算執行方法包含下列步驟：（a)使該阻斷單元接收 一第一微運算及一第二微運算；（b)使該阻斷單元判斷一第一微運 ^ 算具有一例外條件，以更新該阻斷狀態旗標為已阻斷及更新該目 前阻斷辨識碼為該第一微運算之一辨識碼；（c)使該阻斷單元根據 該阻斷狀態旗標設定該第二微運算之一阻斷辨識碼為該目前阻斷 辨識碼；（d)使該微運算槽自該阻斷單元接收並暫存該第一微運算 及該第二微運算；（e)使該微運算槽自該暫存器集合讀取並暫存與 該第一微運算相對應之至少一第一運算元以及與該第二微運算相 對應之至少一第二運算元，並因應已暫存該至少一第二運算元， 設定該第二微運算之一狀態位元為已就緒；以及（〇使該派遣單元 〇 根據該第二微運算之一先行位元、該阻斷辨識碼以及該狀態位 元，判斷該第二微運算係處於一未先行、已阻斷與已就緒之狀態， 以自該微運算槽派遣該第二微運算以及該至少一第二運算元，俾 該第二微運算可先行執行。 综上所述，本發明之微處理器係可透過一先行（slip)機制，使 被阻斷的微運算可先行執行，並前饋其執行結果至微運算槽，以 提供儲存於微運算槽内之微運算所需之運算元。因此，在不顯著 增加額外硬體與微處理器複雜度的情況下，本發明之微處理器具 7 201044269 有與習知具重排序緩衝器之微處理器相近之效能，使微處理器具 有低成本高效能的特性且更具市場價值。 為讓本發明之上述目的、技術特徵、和優點能更明顯易懂，下 文係以較佳實施例、配合所附圖式進行詳細說明。 【實施方式】 本發明係提供一種微處理器及其資料寫入方法。本發明之微處 理器藉由一阻斷單元及一例外偵測單元，在一微運算具有一例外 條件下，讓執行順序於該微運算之後之另一微運算可先行執行， 以提升處理器之指令執行效率。以下之實施例係用以舉例說明本 發明内容，並非用以限制本發明。需說明者，以下實施例及圖式 中，與本發明無關之元件已省略而未繪示，且圖式中各元件間之 尺寸關係僅為求容易瞭解，非用以限制實際比例。 第2圖係繪示本發明第一實施例之微處理器2之示意圖。微處 理器2包含一解碼器201、一暫存器集合203、一阻斷單元205、 一微運算槽207、一派遣單元209、一執行單元211以及一例外偵 測單元213。解碼器201係用以將一指令解碼為至少一微指令，為 方便後續說明，本實施例假設解碼器201將一指令解碼為一第一 微運算202及一第二微運算204，於其他實施例中，解碼器201 係可將一指令解碼為其它數目之微指令，並不以此為限。 需注意者，在第一實施例中，第一微運算202及第二微運算204 可為指令單元（Instruction Unit, IU )微運算以及記憶體管理單元 (Memory Management Unit, MMU)微運算其中之一。若微運算 為「ADD ΑΧ,ΒΧ」，則需自暫存器集合203讀取之運算元為兩個運 201044269 算元’即ΑΧ及BX。若微運算為「MOV ΑΧ,BX」，則需自暫存哭 集合203讀取之運算元為一個運算元，即BX。此外，本實施例中， 「第一」及「第二」僅用來區分第一微運算202與第二微運算2〇4 之相對依序（in-order)執行順序（亦即，若微處理器不具有亂序 執行功能而需依序執行時，第一微運算202需先被派遣至執行單 元213執行，第二微運算2〇4則須於第一微運算2〇2之後被派遣 至執行單元213執行）。換言之，當第一微運算202與第二微運算 ^ 204間存在其他微運算時，亦能執行本發明之技術手段。此外，第 微運异202與第一微運昇· 204各自具有一先行位元、一阻斷辨 識碼以及一狀態位元，其功能與作用將描述於後。 暫存器集合203用以儲存一與第一微運算202相對應之至少一 第一運算元206以及與第二微運算204相對應之至少一第二運算 兀2〇8’阻斷單元2〇5儲存有一阻斷狀態旗標及一目前阻斷辨識 碼。随斷單元2〇5自解碼器201接收第一微運算2〇2及第二微運 算204後’將判斷第一微運算2〇2是否具有一例外（excepti〇n) 〇 條件’以更新該阻斷狀態旗標。 若第一微運算202具有一例外條件時，阻斷單元205則更新該 目月阻斷辨識碼為第一微運算202之一辨識碼且更新該阻斷狀態 旗標為已阻斷’以指示目前正有微指令應被阻斷。隨後，阻斷單 70 2〇5根據該阻斷狀態旗標，設定第二微運算204之一阻斷辨識 碼為s亥目前阻斷辨識碼。換言之，第二微運算2〇4係因第一微運 异2〇2可能發生例外而被阻斷，且其阻斷辨識碼係被設定為第一 微運鼻202之辨識碼，以標明第二微運算2〇4係因第一微運算202 9 201044269 而被阻斷。 微運异槽207用以自阻斷單元2的 辦早兀203接收並暫存第一微運算2〇2 及第一微運鼻2〇4，並根據第一料運曾1 弟微運鼻202及第二微運算204自暫 存器集合203讀取並暫存第_丄軍篡亓 乐連鼻凡2〇6以及第二運算元2〇8。隨 後，微運算槽207因應已暫在筮一逭首 晋存弟運异元206及第二運算元208， 分別設定第一微運算202之一壯能你- , ^ 狀L位7L及第二微運算204之一狀 態位元為已就緒。 第一微運异202之執行順序係先於第二微運算2〇4，因此當根據 第一微運鼻202之一先行位元、一阻斷辨識碼以及一狀態位元， 判斷第一微運算202係處於一未先行' 未阻斷及已就緒之狀態後， 派遣單元‘209係自微運异槽207派遣第—微運算202以及第一運 算元206至執行單元211’俾執行單元211可根據第一運算元206, 執行第一微運算，以產生一第一運算結果21〇。 此外，於派遣第一微運算202以及第一運算元206後，派遣單 元209亦根據第二微運算2〇4之一先行位元、一阻斷辨識碼以及 一狀態位元’判斷第·一微運算204係處於一未先行、已阻斷與已 就緒之狀態，以自微運算槽207派遣第二微運算204以及第二運 算元208至執行單元211。執行單元211更用以根據第二運算元 208，執行第二微運算204 ’以得一第二運算結果212 ’並前饋第 二運算結果212至微運算槽207。 需注意者，於派遣第二微運算204以及第二運算元208後’派 遣單元209係設定第二微運算204之先行位元為已先行’以指示 第二微運算204於阻斷狀態時，已被派遣執行過，當下次派遣單 201044269 元209根據第二微運算204之先行位元、阻斷辨識碼以及狀熊位 元’判斷第二微運算204係處於一已先行、已阻斷與已就緒之狀 態時’將不再派遣執行第二微運算204，直到其阻斷狀態已解除 由於第二微運算204係處於已阻斷之狀態，故派遣至執行單元 後’微運算槽207仍需暫存第二微運算204及第二運算元.2〇8直 到第二微運算204之阻斷狀態被解除且被派遣。 另一方面，於本實施例中，例外偵測單元213係用以於執行时 元211處讀取第一微運算202’以偵測第一微運算2〇2是否確實發 生例外。於其他實施例中，例外偵測單元213係可由它處讀取第 一微運异202，並不以此為限。若例外债測單元213偵測出第—微 運算202確發生例外，則產生一抹除訊號216至微運算槽2〇7，俾 微運算槽207根據抹除訊號216,抹除所有於該第一微運算之後被 讀入並暫存於該微運槽207之微運算，即抹除所有暫存於為微運 算槽207且其依序執行順序係於第—微運算2〇2後之微運算。 若第一微運算係可正常執行，意即第一微運算2〇2未發生例外， 〇 則例外偵測單元213傳送第一微運算202之辨識碼2〇2，至阻斷單 元205與微運算槽207’俾阻斷單元205根據第一微運算202之辨 識碼202，更新其所儲存之阻斷狀態旗標及目前阻斷辨識碼，微 運算槽207因應第二微運算2〇4之阻斷辨識碼係與第一微運算202 之辨識碼202,相符，解除第二微運算2〇4之阻斷狀態。此外，若 第一微運算係可正常執行，例外偵測單元213更傳送一致能訊號 214至執行單元211，俾執行單元2Π因應致能訊號214將第一運 算結果210削饋至微運算槽207並寫回至暫存器集合203。 201044269 承上所述，當第二微運算204之阻斷狀態解除後，第二微運算 204會自微運算槽207重新被派遣至執行單元21卜俾執行單元211 因應第二微運算204之該阻斷狀態解除，將第二運算結果212再 次前饋至微運算槽207並寫回至暫存器集合203。需注意者，由於 第二微運算204先前已執行過一次並將第二運算結果212前饋至 微運算槽207’因此於微運算槽207内與第二微運算204相依之微 運算即可因其運算元已就緒而一起被派遣至執行單元211，不需再 因第二微運算204而等待。 此外’派遣單元209於判斷第二微運算204係處於該未先行、 已阻斷與已就緒之狀態後，可於一延遲時間後再派遣第二微運算 204以及第二運算元208至執行單元211，其中該延遲時間係可與 微處理器2之一工作時脈呈一倍數關係。如此一來，執行第二微 運算204後所產生的第二運算結果212即可因該延遲時間而延遲 前饋至微運算槽207，以提供較晚被微運算槽207接收並暫存的微 運算所需之運算元。 為更彰顯本發明之技術特徵，請參考表1，其係用以表示暫存於 微運算槽207之三個微運算，其中微運算「MOV [MEX]，AX」之 辨識碼為「1」、微運算「ADD BX，CX」之辨識碼為「2」以及微運 算「MOVDX，BX」之辨識碼為「3」。該等辨識碼用以代表該等微 運算之依序執行順序。 表1 辨識碼 微運算 狀態位元 阻斷辨識碼 先行位元 1 MOV [MEX],AX 0 _ 12 201044269 2 ADD BX,CX 0 1 0 3 MOV DX,BX 0 1 0 當阻斷單元205自解碼器201讀取微運算「MOV [MEX]，AX」 後，一旦判斷微運算「MOV [MEX]，AX」具有一例外條件時，即 將阻斷單元205所儲存之阻斷狀態旗標更新為已阻斷，以及將目 前阻斷辨識碼更新為微運算「MOV [MEX],AX」之辨識碼「1」。 在此情況下，當阻斷單元205自解碼器201讀取微運算「ADD BX，CX」及微運算「MOV DX，BX」後，因應微運算「MOV 〇 [MEX]，AX」具有-例外條件，將微運算「ADDBX，CX」及微運算 「MOVDX,BX」之阻斷辨識碼設為微運算「MOV[MEX],AX」之 辨識碼「1」，以代表微運算「ADD BX，CX」及微運算「MOV DX，BX」 係被微運算「MOV [MEX],ΑΧ」阻斷。如此一來，當微運算槽207 自阻斷單元205接收該等微運算後，該等微運算之參數就如同表1 所示。 接著，如表2所示，當微運算槽207自暫存器集合203讀取並 〇 暫存微運算「MOV [ΜΕΧ],ΑΧ」之運算元「ΑΧ」後，微運算「MOV [MEX], ΑΧ」之狀態位元則因應微運算「MOV [MEX], ΑΧ」已就緒 被設成「1」。隨後，派遣單元209根據微運算「MOV [MEX],ΑΧ」 之狀態位元派遣微運算「MOV [ΜΕΧ]，ΑΧ」至執行單元211，因此 微運算槽207所暫存之微運算則如表3所示。 表2 辨識碼 微運算 狀態位元 阻斷辨識碼 先行位元 1 MOV『MEX],AX 1 • 13 201044269 2 ADD BX,CX 0 1 0 3 MOV DX,BX 0 1 0 表3 辨識碼 微運算 狀態位元 阻斷辨識碼 先行位元 2 ADD BX,CX 0 1 0 3 MOV DX,BX 0 1 0 隨後’如表4所示’當微運算槽207至暫存器集合2〇3讀取微 運算「ADDBX，CX」之運算元後，微運算「ADDBX，CX」之狀態 位元被設為「1」。 表4 辨識碼 微運算 狀態位元 阻斷辨識碼 先行位元 2 ADD BX,CX 1 1 0 3 MOV DX,BX 0 1 0 接下來請參閱表5，派遣單元209根據微運算「ADD BX，CX」 之狀態位元、阻斷辨識瑪以及先行位元，判斷微運算r ADD BX，CX」 係處於一未先行、已阻斷與已就緒之狀態，並先行派遣微運算 「ADD BX，CX」至執行單元211並將微運算「ADD BX，CX」之先 行位元設為「1」’執行單元211擇執行微運算r ADD BX，CX」，並 將執行結果「BX」前饋至微運算槽207,藉此微運算「MOV DX,BX」 可得到其運算元「BX」。 表5 辨識碼 微運算 狀態位元 阻斷辨識碼 先行位元 14 201044269 2 ADD BX，CX 1 1 1 3 MOV DX，BX 1 1 0 最後’如表6所示，當微運算「MOV [MEX],ΑΧ」經例外偵測 單元213確定可正常運作時，即傳送微運算「MOV [ΜΕΧ],ΑΧ」 之辨識碼「1」至微運算槽207。微運算槽207則根據辨識碼「1」 解除微運算「ADDBX，CX」與微運算「MOVDX,BX」之阻斷辨識 碼「1」。因此’在阻斷辨識碼已解除的情況下，微運算「ADD BX,CX」 與微運算「MOVDX,BX」可以一起被派遣至執行單元211執行。 執行單元211也因應微運算「ADD BX,CX」與微運算「MOV DXJBX」之阻斷辨識碼已解除，將微運算rADDBX，cx」與微運 算「MOVDX，BX」之執行結果前饋至微運算槽2〇7並寫回至暫存 器集合203。 表6 辨識碼 微運算 狀態位元 —---- 阻斷辨識碼 先行位元 2 ADD BX,CX 1 1 3 MOV DX’BX 1 〜-—--- 0 — 需注意者，上述例子僅使用三個微運算來舉例說明本發明之技 術特徵，但微運异之數目並非用以限制本發明之技術手段，因此 所屬技術領域中具有通常知識者可輕易經由上述例子理解其它數 目之微運算間之執行關係，故不贅述。 本發明之第二實施例係繪示於第3A_3C圖，其係、為適用於第一 實施例之微處理器之微運算執行方法之流程圖。微處理器包含一 解碼器、-暫存器集合、-晴單元、—微運算槽、一派遣單元、 15 201044269 , ^ 乐微運α及一第二微運 异接者，於步驟303令，使 儆連 -例外Μ 使雜斷U⑽《-微運算具有 辨識碼為該第-微運算之—辨識碼/^斷及更新該目則阻斷 微運^驟305中’使該阻斷單元根據該阻斷狀態旗標設定該第-:運具:一阻斷辨識碼為該目前阻斷辨識碼，於步驟307中二 曾^ 接收並暫存該第—微運算及該第二微運 鼻，於步驟獅中，使該微 微運 該第-微«相對紅至少―第暫存^合轉並暫存與 . 第運异兀以及與該第二微運算相 對應之至少一第二運算元。 請參閱第3Β圖’於步驟31〇中，使該微運算槽因應已暫存該至 少一第—運算元，設定該第—微運算之―狀態位元為已就緒，於 步驟311中，使該派遣單元根據該第—微運算之該狀態位元，判 斷該第:微運算係處於已就緒之狀態，以自該微運算槽派遣該第 微運异以及该至少—第一運算元，於步驟312中，使該執行單 元自該派遣單元接«第—微運算與該至少-第-運算元。 此外’於步驟313中，使該微運算槽因應已暫存該至少一第二 運算元，設定該第二微運算之一狀態位元為已就緒，於步驟314 中’使該派遣單元根據該第二微運算之—先行位元、該阻斷辨識 碼以及該狀態位元，判斷該第二微運算係處於一未先行、已阻斷 與已就緒之狀態，以自該微運算槽派遣該第二微運算以及該至少 -第二運算元。於步驟315巾，使該派造單元於派遣該第二微運 16 201044269 算以及該至少一第二運算元後，設定該第 已派遣。 •微運 算之先行位元為 Ο Ο 承上所述，於步驟317 + ’使該執行單元自該派遣單元接㈣ 第二微運算與該至少-第二運算元，於步驟319巾，使該執_ 讀據該至少-第二運算元，執行該第二微運算，以得—第 =槽於步…，使該執行單元前饋該第二運算結果:該 =’：㈣第3C圖’於步驟323中’使該執行單元根據該 ”二：一該第一微運算’以得-第-運算結果， :^ 325巾’使該例外偵測單元偵測該第—微運算是 ::::偵測單元侦測該第-微運算係可正常執行，則好 傳运—致能訊號至該執行單元。接著，於 使該執行單元因應該致能訊、7中， 並寫回該暫存g^ $連异結果則饋至微運算槽 於步驟329 *，使該派遣單元於派遣該第 -微運算至該執行單元，俾該執行單 遺4 該第二運算結果。於步驟33〇中 運异’以得 算之阻斷狀態已解 /執仃皁70因應該第二微運 該暫存器集合。 、—運算結果前饋至該微運算槽寫回 然後，於步驟 相單70產生—抹除訊號至該微運算槽。 於該第_微運 使5亥微運算槽根據該抹除訊號，抹除所有 ,, '皮讀入並暫存於該微運槽之微運算。 詳言之，於習知微處理器卜由於該第二微運算因被該第一微 17 201044269 運异所阻斷’故需等待該第—微運算之例外條件解除後才可被派 遣並執打。惟，於本發明中，為了增加微處理n的執行效率，使 該第二微運算在被阻_情況下亦可先行派遣執行，@此一旦該 第—微運算破判斷出係處於—未先行、已阻斷與已就緒之狀態， 其料先行被派遣執行，但不將所產生之該第二運算結果寫回至 暫存..集。且不自微運算槽清除第二微運算，只前饋該第二運算 結，至該微運算槽’以使該微運算槽内需要該第二運算結果作為 運算几之相關微運算處於已就緒之狀態。 注意者’如㈣—實施例所述，該派遣單元係根據該第-微 運=處於已就緒之狀態與該第二微運算處於—未先行、已阻斷與 已就緒之狀自微運算槽派遣該第—微運算及該第二微運算。 換言之，步驟311肖步驟314不具有—固定執行順序，且步驟川 與步驟314亦可同時執行。 除前料驟外’第二實施例亦能執行在第一實施例中所述之所 有功此及㈣’热悉此項技術領域者可根據第—實施例之相關描 述輕易理解，在此不加贅述。 綜上所述，本發明之微處理器於偵測一第一微運算且有一例外 條件的情況下，可使在其之後執行之第二微運算先行派遣執行， =第二微運算之執行結果㈣至微運㈣，航提供與第二微 運算相關之微運算㈣得其所需之運算元。如此—來，當例外條 件解除後’已儲存於微運算槽内之已讀人運算元之微運算即可同 時平行執行，已提升微處理之執行效率。 羊。之’本發明之微處理器在省去重排序緩衝器的情況下，透 18 201044269 過先行派遣執行的機制，使被阻斷的微運算可先行執行並前饋其 執行結果回微運算槽，以讓微運算槽内相依之微運算先獲得其所 需之運算元。因此，在不大幅增加硬體電路之情況下，本發明處 理器之效能可與具重排序緩衝器之習知微處理器之效能相近，使 處理器具有低成本高效能的特性，且提升其市場價值。 上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明 之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術 者可輕易完成之改變或均等性之安排均屬於本發明所主張之範 Ο 圍，本發明之權利保護範圍應以申請專利範圍為準。 【圖式簡單說明】 第1圖係為習知微處理器之示意圖； 第2圖係為本發明之第一實施例之微處理器之示意圖；以及 第3A-3C圖係為本發明之第二實施例之微運算執行方法之流程 圖。 【主要元件符號說明】 1 :微處理器 101 :解碼器 102 :至少一微運算 103 :暫存器集合 104 :至少一運算元 105 :微運算槽 106 :至少一運算結果 107 :派遣單元 108 :至少一運算結果 111 :重排序緩衝器 109 :執行單元 2:微處理器 201 :解碼器 202 :第一微運算 202’ ：辨識碼 19 201044269 203 :暫存器集合 204 ： 205 :阻斷單元 206 ： 207 :微運算槽 208 ： 209 :派遣單元 210 ： 211 :執行單元 212 ： 213 :例外偵測單元 214 : 216 :抹除訊號 第二微運算 第一運算元 第二運算元 第一運算結果 第二運算結果 致能訊號 20Similarly, any one of the techniques can be easily understood, and the operation result 108 is also fed forward to the micro-operation slot 1〇5, and the comparison result 108 also corresponds to the identification code of the micro-operation 102. The operation unit to be read in the micro-operating slot η can be judged according to the identification code to determine whether or not to use the feedforward return result. It should be noted that, in the micro-operation slot 105, there may be a micro-operation in which the order of the micro-operation is low, and the time at which the micro-operation is read into the micro-operation slot 105 is fed back to the micro-operation slot 1 at the operation result 106. At the time point of 5 and the operation of the sister, the "cloth" is fed to the time point of the micro-operation slot 1〇5. Therefore, the execution result of the H-order #χlow micro-operation system and the read-forward feed back (10) For its different elements. In short, the arithmetic elements required for the micro-speed support are not necessarily bought from the scratchpad set 1〇3 S', or they can be self-heavy and drained from D. It is obtained from the execution unit 109, which is not described here at 201044269. Since the microprocessor 1 needs to reorder the operation results generated by the out-of-order execution by the reordering buffer 111 to restore the original sequential execution state, thus increasing the micro The complexity and power consumption of the processor 1. On the other hand, the implementation of the reordering buffer 111 requires the use of additional registers and circuits, thereby increasing the hardware requirements and increasing the hardware cost of the processor. How to reduce the complexity and power consumption of the processor, and how to shrink The problem of reducing the hardware demand while maintaining the efficiency and minimizing the cost is an urgent problem for the practitioners in the field. SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor including a register set and a resistor a blocking unit, a micro-computing slot, and a dispatching unit. The blocking unit is configured to store a blocking status flag and a current blocking identification code, receive a first micro-operation and a second micro-operation, and determine the first The micro-operation has an exception condition to update the blocking status flag to be blocked, and update the current blocking identification code to be one of the first micro-operation identification codes, and set the according to the blocking status flag. One of the second micro-operation blocks the identification code as the current blocking identification code. The micro-operation slot is configured to receive and temporarily store the first micro operation and the second micro operation from the blocking unit, from the register The set reads and temporarily stores at least one first operation element corresponding to the first micro operation and at least one second operation element corresponding to the second micro operation, and correspondingly stores the at least one second operation element , set the second One of the operation status bits is ready. The dispatch unit is configured to determine, according to the first bit of the second micro operation, the blocking identification code and the status bit, that the second micro operation system is in a first line The state of 201044269 has been blocked and ready to dispatch the second micro-operation and the at least one second operand from the micro-operating slot, and the second micro-operation can be performed first. Another object of the present invention is A micro-operation execution method for a microprocessor is provided. The microprocessor includes a register set, a blocking unit, a micro-operation slot, and a dispatch unit. The blocking unit stores a blocking status flag. And a current blocking identification code. The micro-operation execution method comprises the following steps: (a) causing the blocking unit to receive a first micro-operation and a second micro-operation; (b) causing the blocking unit to determine a first The micro-operation has an exception condition to update the blocking status flag to block and update the current blocking identification code as one of the first micro-operation identification codes; (c) causing the blocking unit to Block status flag to set the number One of the two micro-operations blocks the identification code as the current blocking identification code; (d) causes the micro-operation slot to receive from the blocking unit and temporarily stores the first micro-operation and the second micro-operation; (e) The micro-operating slot reads from the set of registers and temporarily stores at least one first operand corresponding to the first micro-operation and at least one second opera-corresponding to the second micro-operation, and Temporarily storing the at least one second operation unit, setting a status bit of the second micro-operation to be ready; and (such that the dispatch unit 先 according to the second micro-operation one of the preceding bits, the blocking identification code And the status bit, determining that the second micro-operation system is in a state of no prior, blocked, and ready, to dispatch the second micro-operation and the at least one second operation unit from the micro-operation slot, The second micro operation can be performed first. In summary, the microprocessor of the present invention can enable the blocked micro-operation to be executed first through a slip mechanism, and feed forward the execution result to the micro-operation slot to provide storage in the micro-operation slot. The operands required for the inner micro operation. Therefore, the microprocessor of the present invention 7 201044269 has similar performance to the conventional microprocessor with reordering buffer, without significantly increasing the complexity of the additional hardware and the microprocessor, so that the microprocessor has a low Cost-effective features and more market value. The above described objects, technical features, and advantages of the present invention will become more apparent from the following description. [Embodiment] The present invention provides a microprocessor and a data writing method thereof. The microprocessor of the present invention uses a blocking unit and an exception detecting unit to perform an execution of the other micro-operation after the micro-operation with an exception to improve the processor. The instruction execution efficiency. The following examples are intended to illustrate the invention and are not intended to limit the invention. It should be noted that in the following embodiments and drawings, elements that are not related to the present invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are merely for ease of understanding and are not intended to limit the actual ratio. Fig. 2 is a schematic view showing the microprocessor 2 of the first embodiment of the present invention. The microprocessor 2 includes a decoder 201, a register set 203, a blocking unit 205, a micro-operation slot 207, a dispatch unit 209, an execution unit 211, and an exception detecting unit 213. The decoder 201 is configured to decode an instruction into at least one microinstruction. For convenience of the following description, the embodiment assumes that the decoder 201 decodes an instruction into a first micro operation 202 and a second micro operation 204. For example, the decoder 201 can decode an instruction into other numbers of microinstructions, and is not limited thereto. It should be noted that in the first embodiment, the first micro-operation 202 and the second micro-operation 204 may be an instruction unit (IU) micro-operation and a memory management unit (MMU) micro-operation. One. If the micro-operation is "ADD ΑΧ, ΒΧ", the operands to be read from the register set 203 are two 201044269 arithmetic units ie ΑΧ and BX. If the micro operation is "MOV ΑΧ, BX", the operand to be read from the temporary crying set 203 is an operand, that is, BX. In addition, in this embodiment, "first" and "second" are only used to distinguish the relative order of in-order execution of the first micro-operation 202 and the second micro-operation 2〇4 (ie, if micro When the processor does not have the out-of-order execution function and needs to be executed sequentially, the first micro-operation 202 needs to be dispatched to the execution unit 213, and the second micro-operation 2〇4 is dispatched after the first micro-operation 2〇2. Execution unit 213 executes). In other words, when there are other micro operations between the first micro-operation 202 and the second micro-operation ^ 204, the technical means of the present invention can also be performed. In addition, the first micro-transport 202 and the first micro-elevation 204 each have a look-ahead bit, a block identification code, and a status bit, the function and function of which will be described later. The register set 203 is configured to store at least one first operand 206 corresponding to the first micro-operation 202 and at least one second operation 兀2〇8' blocking unit 2 corresponding to the second micro-operation 204. 5 stores a blocking status flag and a current blocking identification code. After receiving the first micro-operation 2〇2 and the second micro-operation 204 from the decoder 201, the interrupt unit 2〇5 will determine whether the first micro-operation 2〇2 has an exception (excepti〇n) condition _ to update the Block the status flag. If the first micro-operation 202 has an exception condition, the blocking unit 205 updates the target blocking identification code to one of the first micro-operations 202 and updates the blocking status flag to blocked 'to indicate There are currently microinstructions that should be blocked. Subsequently, the blocking unit 70 2〇5 sets one of the second micro-operations 204 to block the identification code as the current blocking identification code according to the blocking status flag. In other words, the second micro-operation 2〇4 is blocked due to an exception of the first micro-transport 2〇2, and the blocking identification code is set as the identification code of the first micro-transport nose 202 to indicate the first The second micro-operation 2〇4 is blocked by the first micro-operation 202 9 201044269. The micro-transport slot 207 is used to receive and temporarily store the first micro-operation 2〇2 and the first micro-runner nose 2〇4 from the blocking unit 2, and according to the first item, the 1st brother micro-nose 202 and the second micro-operation 204 read from the register set 203 and temporarily store the first 丄 丄 篡亓 连 连 连 连 2 2 2 and the second operand 2 〇 8. Subsequently, the micro-computing slot 207 respectively sets the first micro-operation 202 to be one of the first micro-operations 202, and the second L-bit 7L and the second, respectively. One of the micro-ops 204 status bits is ready. The execution order of the first micro-transport 202 precedes the second micro-operation 2〇4, so when the first micro-bit, the first identification bit, and the one-level bit are determined according to the first micro-runner 202, the first micro is determined. After the operation 202 is in a state of not preceding 'unblocked and ready, the dispatch unit 209 dispatches the first-micro-operation 202 and the first operand 206 to the execution unit 211' from the micro-transport 207 to execute the unit 211. The first micro operation may be performed according to the first operation unit 206 to generate a first operation result 21〇. In addition, after dispatching the first micro-operation 202 and the first operation unit 206, the dispatch unit 209 also judges the first one according to the second micro-operation 2〇4 one-bit bit, one block identification code, and one state bit ' The micro-operation 204 is in a state of no prior, blocked, and ready to dispatch the second micro-operation 204 and the second operand 208 from the micro-operation slot 207 to the execution unit 211. The execution unit 211 is further configured to perform the second micro operation 204 ′ according to the second operation unit 208 to obtain a second operation result 212 ′ and feed forward the second operation result 212 to the micro operation slot 207 . It should be noted that after the second micro-operation 204 and the second operand 208 are dispatched, the dispatch unit 209 sets the pre-transmission bit of the second micro-operation 204 to be prioritized to indicate that the second micro-operation 204 is in the blocking state. Has been dispatched to execute, when the next dispatch order 201044269 yuan 209 according to the second micro-computing 204 first-order bit, block identification code and the shape of the bear bit element 'determine the second micro-operation 204 is in a pre-emptive, blocked and ready In the state of 'the second micro-operation 204 will not be dispatched until the blocking state has been released. Since the second micro-operation 204 is in the blocked state, the micro-operation slot 207 still needs to be sent after being dispatched to the execution unit. The second micro-operation 204 and the second operand .2〇8 are stored until the blocking state of the second micro-operation 204 is released and dispatched. On the other hand, in the present embodiment, the exception detecting unit 213 is configured to read the first micro-operation 202' at the execution time 211 to detect whether the first micro-operation 2 〇 2 does have an exception. In other embodiments, the exception detection unit 213 can read the first micro-transport 202 from it, and is not limited thereto. If the exception debt detecting unit 213 detects that the first micro-operation 202 has an exception, an erasing signal 216 is generated to the micro-operating slot 2〇7, and the micro-operating slot 207 erases all the first according to the erasing signal 216. After the micro-operation, the micro-operation is read and temporarily stored in the micro-slot 207, that is, all the micro-operations that are temporarily stored in the micro-operation slot 207 and whose sequential execution order is after the micro-operation 2〇2 are erased. . If the first micro-operation system can be executed normally, that is, the first micro-operation 2〇2 does not have an exception, the exception detection unit 213 transmits the identification code 2〇2 of the first micro-operation 202 to the blocking unit 205 and the micro- The operation slot 207 俾 blocking unit 205 updates its stored blocking status flag and the current blocking identification code according to the identification code 202 of the first micro-operation 202, and the micro-operation slot 207 corresponds to the second micro-operation 2〇4 The blocking identification code is consistent with the identification code 202 of the first micro-operation 202, and the blocking state of the second micro-operation 2〇4 is released. In addition, if the first micro-operation system can be executed normally, the exception detection unit 213 further transmits the coincidence signal 214 to the execution unit 211, and the execution unit 2 削 feeds the first operation result 210 to the micro-operation slot 207 according to the enable signal 214. And write back to the scratchpad set 203. 201044269 As described above, after the blocking state of the second micro-operation 204 is released, the second micro-operation 204 is re-sent from the micro-operation slot 207 to the execution unit 21. The execution unit 211 corresponds to the second micro-operation 204. The blocking state is released, and the second operation result 212 is fed back to the micro-operation slot 207 and written back to the register set 203. It should be noted that since the second micro-operation 204 has been executed once and the second operation result 212 is fed forward to the micro-operation slot 207 ′, the micro-operation between the micro-operation slot 207 and the second micro-operation 204 may be The operands are ready to be dispatched together to the execution unit 211 without waiting for the second micro-operation 204. In addition, the dispatch unit 209 may send the second micro-operation 204 and the second operand 208 to the execution unit after a delay time after determining that the second micro-operation 204 is in the state of no prior, blocked, and ready. 211, wherein the delay time is in a multiple relationship with a working clock of the microprocessor 2. In this way, the second operation result 212 generated after the execution of the second micro-operation 204 can be delayed by the delay time to the micro-operation slot 207 to provide the micro-acceptance and temporary storage of the micro-slot 207. The operands required for the operation. In order to further illustrate the technical features of the present invention, please refer to Table 1, which is used to indicate three micro-operations temporarily stored in the micro-operation slot 207, wherein the identification code of the micro-operation "MOV [MEX], AX" is "1". The identification code of the micro-calculation "ADD BX, CX" is "2" and the identification code of the micro-operation "MOVDX, BX" is "3". The identification codes are used to represent the sequential execution order of the micro-operations. Table 1 Identification code Micro-operation status bit blocking identification code leading bit 1 MOV [MEX], AX 0 _ 12 201044269 2 ADD BX, CX 0 1 0 3 MOV DX, BX 0 1 0 When blocking unit 205 self-decoding After reading the micro-operation "MOV [MEX], AX", once the micro-operation "MOV [MEX], AX" is judged to have an exceptional condition, the blocking status flag stored in the blocking unit 205 is updated to Block, and update the current blocking identification code to the identification code "1" of the micro-operation "MOV [MEX], AX". In this case, when the blocking unit 205 reads the micro-operation "ADD BX, CX" and the micro-operation "MOV DX, BX" from the decoder 201, the micro-operation "MOV 〇 [MEX], AX" has an exception - For the condition, the blocking ID of the micro-operation "ADDBX, CX" and the micro-operation "MOVDX, BX" is set to the identification code "1" of the micro-operation "MOV[MEX], AX" to represent the micro-operation "ADD BX," CX" and the micro-operation "MOV DX, BX" are blocked by the micro-operation "MOV [MEX], ΑΧ". In this way, when the micro-operation slot 207 receives the micro-operations from the blocking unit 205, the parameters of the micro-operations are as shown in Table 1. Next, as shown in Table 2, when the micro-computing slot 207 reads from the register set 203 and temporarily stores the arithmetic unit "ΑΧ" of the micro-operation "MOV [ΜΕΧ], ΑΧ", the micro-operation "MOV [MEX] The status bit of "," is set to "1" in response to the micro-calculation "MOV [MEX], ΑΧ". Then, the dispatch unit 209 dispatches the micro-operation "MOV [ΜΕΧ], ΑΧ" to the execution unit 211 according to the status bit of the micro-operation "MOV [MEX], ΑΧ", so the micro-operation temporarily stored in the micro-operation slot 207 is as shown in the table. 3 is shown. Table 2 Identification code Micro-operation status bit blocking identification code leading bit 1 MOV『MEX】, AX 1 • 13 201044269 2 ADD BX, CX 0 1 0 3 MOV DX, BX 0 1 0 Table 3 Identification code micro-operation status Bit Block Identification Code Preceding Bit 2 ADD BX, CX 0 1 0 3 MOV DX, BX 0 1 0 Subsequently 'As shown in Table 4' when the micro-operation slot 207 to the scratchpad set 2〇3 read the micro-operation After the operand of "ADDBX, CX", the status bit of the micro-operation "ADDBX, CX" is set to "1". Table 4 Identification code Micro-operation status bit block identification code pre-emption bit 2 ADD BX, CX 1 1 0 3 MOV DX, BX 0 1 0 Next, please refer to Table 5, dispatch unit 209 according to micro-operation "ADD BX, CX The status bit, blocking the identification and the leading bit, and judging the micro-operation r ADD BX, CX" are in a state of no prior, blocked and ready, and dispatch the micro-operation "ADD BX, CX" first. Go to the execution unit 211 and set the leading bit of the micro-operation "ADD BX, CX" to "1". The execution unit 211 selects the micro-operations ADD BX, CX", and feeds the execution result "BX" to the micro-operation. In the slot 207, the arithmetic unit "BX" can be obtained by the micro-operation "MOV DX, BX". Table 5 Identification code Micro-operation status bit blocking identification code leading bit 14 201044269 2 ADD BX, CX 1 1 1 3 MOV DX, BX 1 1 0 Finally 'As shown in Table 6, when the micro-operation "MOV [MEX] When the exception detecting unit 213 determines that it can operate normally, the identification code "1" of the micro-operation "MOV [ΜΕΧ], ΑΧ" is transmitted to the micro-operation slot 207. The micro-computing groove 207 cancels the micro-operation "ADDBX, CX" and the micro-operation "MOVDX, BX" blocking identification code "1" based on the identification code "1". Therefore, in the case where the blocking identification code has been released, the micro-operation "ADD BX, CX" and the micro-operation "MOVDX, BX" can be dispatched to the execution unit 211 for execution. The execution unit 211 also feeds forward the execution results of the micro-operations rADDBX, cx" and the micro-operation "MOVDX, BX" to the micro-computing "ADD BX, CX" and the micro-operation "MOV DXJBX" blocking identification code is released. The arithmetic slot 2〇7 is written back to the scratchpad set 203. Table 6 Identification code micro-operation status bit ----- Block identification code leading bit 2 ADD BX, CX 1 1 3 MOV DX'BX 1 ~----- 0 — Note, the above example is only used The three micro-operations are used to illustrate the technical features of the present invention, but the number of micro-transports is not intended to limit the technical means of the present invention. Therefore, those skilled in the art can easily understand other numbers of micro-operations via the above examples. The implementation relationship, so I will not go into details. A second embodiment of the present invention is shown in FIG. 3A-3C, which is a flowchart of a micro-operation execution method applicable to the microprocessor of the first embodiment. The microprocessor comprises a decoder, a register set, a clear unit, a micro-computing slot, a dispatch unit, 15 201044269, ^ Le Wei Yun α and a second micro-transporter, in step 303, Make the - - - Μ Μ 杂 U ( ( ( ( ( - - - - - - - - - - - - - - 305 305 305 305 305 305 305 Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ The blocking status flag sets the first:: means: a blocking identification code is the current blocking identification code, and in step 307, the second micro-operation and the second micro-operation are temporarily received and temporarily stored. And in the step lion, causing the micro-transportation of the first-micro «relative red at least" temporary storage and temporary storage and the second operation and at least one second operation element corresponding to the second micro-operation . Referring to FIG. 3A, in step 31, the micro-operation slot is configured to temporarily store the at least one first operation element, and set the status bit of the first-micro operation to be ready. In step 311, The dispatching unit determines, according to the status bit of the first-micro operation, that the first: micro-operation system is in a ready state, and dispatches the micro-transport and the at least-first operand from the micro-operating slot. In step 312, the execution unit is caused to receive the «first-micro-operation and the at least----the operation unit from the dispatch unit. In addition, in step 313, the micro-operating slot is configured to temporarily store the at least one second operand, and set one of the second micro-operation status bits to be ready, and in step 314, 'make the dispatch unit according to the The second micro-operation - the first bit, the blocking identification code, and the status bit, determining that the second micro-operation system is in a state of no prior, blocked, and ready to dispatch the micro-slot A second micro-operation and the at least-second operand. In step 315, the dispatching unit sets the dispatched unit after dispatching the second micro-transport 16 201044269 and the at least one second operand. • The first bit of the micro-operation is Ο 承, in step 317 + 'the execution unit is connected to the dispatch unit (4), the second micro-operation and the at least-second operation element, in step 319, so that Performing the second micro-operation according to the at least-second operand, so that the -th slot is in the step..., causing the execution unit to feed forward the second operation result: the =': (4) the 3C picture In step 323, 'the execution unit is based on the second two: a first micro-operation 'to obtain a ---the operation result, the :^ 325 towel' causes the exception detection unit to detect the first-micro operation is: The detecting unit detects that the first-micro operation system can be executed normally, and then transmits the signal to the execution unit. Then, the execution unit is enabled to enable the signal, 7 and write back the The temporary storage g^$-contrast result is fed to the micro-operation slot in step 329*, so that the dispatch unit dispatches the first-micro-operation to the execution unit, and the execution unit performs the second operation result. 〇中运异's calculation of the blocking state has been solved / 仃 仃 soap 70 should be the second micro-transport this register collection. If the feed back to the micro-slot is written back, then the step 70 is generated to erase the signal to the micro-slot. In the first _ micro-transfer, the 5-Hui operation slot erases all according to the erase signal. , 'The skin is read in and temporarily stored in the micro-operation of the micro-slot. In detail, in the conventional microprocessor, because the second micro-operation is blocked by the first micro-17 201044269 Waiting for the exception condition of the first micro-operation to be dispatched and executed, but in the present invention, in order to increase the execution efficiency of the micro-processing n, the second micro-operation may be preceded by being blocked. Dispatch execution, @This once the first-micro-computation breaks the judgment that the system is in the state of - no first, blocked and ready, it is dispatched first, but the second operation result is not written back to Temporarily storing the set. and not clearing the second micro-operation from the micro-operating slot, only feeding the second operation node to the micro-operation slot 'so that the second operation result is needed in the micro-operation slot as the operation The relevant micro-operation is in a ready state. Note that 'as in (four) - the embodiment, The dispatching unit dispatches the first micro-operation and the second micro-operation according to the first-micro-transmission=in the ready state and the second micro-operation is--the first, the blocked and the ready-to-use micro-operation slot In other words, step 311, step 314 does not have a fixed execution sequence, and step and step 314 can also be performed simultaneously. The second embodiment can perform all the functions described in the first embodiment. And (4) 'experienced in the technical field can be easily understood according to the description of the first embodiment, and will not be described here. In summary, the microprocessor of the present invention detects a first micro operation and has a In the case of an exceptional condition, the second micro-operation performed after it can be dispatched first, the execution result of the second micro-operation (4) to the micro-transport (4), and the micro-operation (four) related to the second micro-operation is provided. The required operation element. In this way, when the exception condition is removed, the micro-operations of the read human operands already stored in the micro-operation slot can be executed in parallel at the same time, which improves the execution efficiency of the micro-processing. sheep. In the case where the microprocessor of the present invention dispenses with the reordering buffer, the mechanism of the first dispatching execution is performed through 18 201044269, so that the blocked micro-operation can be executed first and the execution result is fed back to the micro-operation slot. In order to let the micro-operations in the micro-operating slot first obtain the required operands. Therefore, without significantly increasing the hardware circuit, the performance of the processor of the present invention can be similar to that of a conventional microprocessor with a reordering buffer, so that the processor has low-cost and high-performance characteristics and enhances its performance. Market value. The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional microprocessor; FIG. 2 is a schematic diagram of a microprocessor according to a first embodiment of the present invention; and FIG. 3A-3C is a diagram of the present invention Flowchart of the micro-operation execution method of the second embodiment. [Description of main component symbols] 1: Microprocessor 101: Decoder 102: At least one micro-operation 103: register set 104: at least one operand 105: micro-operation slot 106: at least one operation result 107: dispatch unit 108: At least one operation result 111: reorder buffer 109: execution unit 2: microprocessor 201: decoder 202: first micro-operation 202': identification code 19 201044269 203: register set 204: 205: blocking unit 206 : 207 : micro-operation slot 208 : 209 : dispatch unit 210 : 211 : execution unit 212 : 213 : exception detection unit 214 : 216 : erase signal second micro-operation first operation element second operation element first operation result Second operation result enable signal 20