TW201039569A - Viterbi decoder - Google Patents

Abstract

An enhanced Viterbi decoder is disclosed. A path metric memory stores a state matrix comprising a plurality of stages each contains 2n state elements. Each state element has an index value and a path metric, and is associated with a plurality of branch metrics. A traceback unit comprises n processing levels cascaded in series, operative to find state elements of the minimal path metrics with their indices, to build a survival path. In each processing level, at least one CSUs individually compares two different path metrics to determine a miner one, with a flag output to indicate a status of the determination. A register is provided to record all flags corresponding to the same processing level. When all registers of all processing levels are recorded with flags, an index of the state element of the minimal path metric can be accordingly determined.

Description

201039569 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to wireless communication systems, and more particularly to improved Viterbi decoders. [Prior Art] Fig. 1 is an architectural diagram of a communication system. A transmitter 11 transmits a message through an antenna 102, and a receiver 12 transmits the message through an antenna 104. The transmission channel between antennas 102 and 104 can interfere with the message. Therefore, an error control coding technique must be employed between the transmitter 110 and the receiver 120. The transmitter 110 adds some redundancy to the particular rule before transmitting the message to produce higher bit rate encoded data. Receiver 120 then uses these redundancy checks to determine the content of the originally transmitted message. The purpose of error control coding is to reduce the effects of channel noise interference, which can be roughly classified into two types: block code and convolutional code. The whirling code is more commonly used in wireless voice communication systems because of the low tolerance of voice communication to data retransmission rate and delay. Block codes can be used to deliver applications with high throughput requirements, but large delay times must be tolerated. The Viterbi algorithm is a forward error correction (Trellis) algorithm for detecting the largest-likelihood (ML) sequence, and is an ideal algorithm for solving the convolutional code. The "Err〇r Control System for Digital Communication and Storage (Pretice Hall, 1995)" written by SB Wicker describes the viterbi decoder in mobile communication VITO8-0014I00-TW/ 06O8-A41750TWf/Finay 4 201039569 Application in the system. In Figure 1, the antenna antenna in the receiver 120 receives the RF signal and converts it to the base frequency. The U 122 first transmits the baseband signal through the benefit (ADC) 124. The decoding step is performed by the number=analog digit transcoder 126. 唬 唬 供 维 维 维 维 维 维 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 维 维 维 维 维 维 维 维 维 维 维 维 维 维However, with the introduction of hardware power consumption and volume considerations, it is always necessary to improve. Therefore, important, circuit [invention] The present invention proposes an improved Viterbi solution memory in which a state matrix is stored. , including a plurality of 阼 path weights including π state elements 'per-state element having a singular two every 7-segment packet and corresponding to a plurality of branch metrics (Branch Metric). A 'k weight value The first to the nth processing levels are sequentially connected in series, and are used to find: the minimum path weight and the corresponding index value of each stage of the packet: = 70, the matrix diameter. The migration-survival path is at each processing level. In the middle, at least one comparison selection unit (CSU) compares the path weights of the two different states and outputs the smaller ones, and outputs a flag to represent the ratio of the vehicle and the fruit. The device records the round-trip of each comparison selection unit. The traceback unit can derive the index value of the state element with the smallest path weight in the second-order segment according to the register configuration of all processing levels. 6 In each comparison selection unit The first round entry and the second round input each receive a path weight of a different state element. A comparator compares VIT08-0014I00-TW/0608-A41750TWf) Tinal/ 5 201039569 the first input and the a path weight of the second input end, and outputting a flag to record one of the first input end and the second input end having a smaller path weight. A selector may selectively select the flag according to the flag Receiving the first input or the second input The path weight output. The flag may be a Boolean value, for example, the flag value 〇 represents the first input, and the flag value 1 represents the second input. The first processing level includes 2n_1 comparison options. a unit, and each input end of the 211-1 comparison selection unit sequentially corresponds to a different index value, wherein η is a natural number. 21^1 of the first processing level compares the 2η received by the selection unit The status elements are compared for pairwise alignment, and the half output is filtered to the next processing level. The number of comparison selection units for each processing level after the second processing level is half of the number of comparison selection units of the previous processing level. The last processing level has only one comparison selection unit, and the value of the output represents one of the 2n state elements in the stage of the state matrix having the smallest path weight. Similarly, the scratchpad of the first processing level contains 211.1 bits, and stores the corresponding flag of 2n_1 comparison selection units. The number of bits of the scratchpad of each processing level after the second processing level is half of the number of bits of the register of the previous processing level. The last processing level register contains one bit. Each comparison selection unit of each processing level sequentially corresponds to one bit of the register of the same processing level. The backtracking unit can infer that the minimum path weight is from the first comparison selection unit of the previous processing level based on each processing level and all subsequent registers. For example, the lookback unit infers a specific comparison selection unit based on the register configuration of the second processing level to the last processed VIT08-0014I00-TW/0608-A41750TWf/Final/6 201039569 level. The level register registers the specific input of the smallest unit. The minimum path weight is from the first processing level. The backtracking unit can then determine the value of the cable from the particular comparison option according to the first processing path weight: the backtracking unit is based on the following public B〇=Rn[〇]

Bl=Rn-l[B〇] B2=Rn.2[B〇Bi]

Bn=Ri[B〇BiB2B3...Bn

Imin~[B〇BiB2B3 . · ·Βη] The center to the Rn system is the first - _ 七 Ό ^ ^ ^ ^ 恳 stratification level to the η processing level of the register, Β〇 to Β 系 is the Bolling value 〇 Ar τ, U or 1, successively from the corresponding register to the specific address in Ri; ^ ^ Ώ , Ώ u , ^ ^ f' and the specific address is expressed as Boolean B The binary progression of Bn is also a value, Imin represents the value of the cable corresponding to the state element with the smallest path weight, and * _ ^ ^ is shown as the binary value of the Boolean value Bo to Bn. [Embodiment] FIG. 2 is a block diagram of the wei 丨 特 特 ratio decoder 126 in FIG. 1 . The state matrix is a concept of probability. Fields are used to calculate the state, state, gamma, heart rate (branch weight) and existence probability (road control weight) of a particular state state (State). ). In the Viterbi decoder m, the branch weight processor 202 receives the digit value #IN supplied by the ADC 124g, thereby calculating the probability of all the branches of the state matrix jumping from one phase to the next, also known as YIT08-0014IOO-TW. /0608-A41750TWfTinay 7 201039569 Branch weight (Brand! Metric). The output of the branch weight processor is then sent to the addition comparison selection (ACS) unit 2〇4, so that the addition comparison selection unit 204 performs the path-mechanism of the lower-stage in the state matrix according to the branch weight. Update. The addition comparison selection unit 204 in the Viterbi decoder 126 may be a plurality of parallel operations, perform a natural recursion operation to generate the state matrix, and store the state matrix in the path weight memory 2 〇6. Since the bear matrix is updated step by step, the addition comparison selection unit 2〇4 must use a large number of overlays. Therefore, the function of the path weight memory 2〇6 is similar to a double buffer for the addition comparison unit 204 to recur access. After the addition comparison selection unit 204 completes the update operation of the state matrix, the backtracking unit 2〇8 reads the gate weight memory 206 and performs the survival path operation and the maximum similarity operation to generate the message closest to the original transmission signal. Code #〇υτ. The natural recursive operation performed in the Viterbi decoder 126 can be based on various different nasal expressions, such as the Log-Maximum a Posteriori (Log-MAP) algorithm, and the maximum number of artifacts after the event ( The Max Log-MAP algorithm or the Enhanced Max Log-MAP algorithm. These algorithms are collectively referred to as Soft-in-Soft-out (SISO) decoding algorithms. However, embodiments of the present invention are also applicable to other possible Viterbi architectures and are not limited to the examples described in this paragraph. Figure 3 is a schematic diagram of a state metric with a base of four. The horizontal axis t represents time or phase, and the vertical axis represents multiple state elements contained in each phase. Taking Figure 3 as an example, the state matrix contains a plurality of state vectors h to tM. Each state vector contains n states VIT08-0014IOO-TW/0608-A41750TWfTFinal/ 8 201039569 yuan Si to SN. Taking the state element Si of the stage tkd as an example, since the cardinality of the state matrix is four (radix 4 ), there are four possible branch paths of the state element S! jumping to the next stage. In fact, in the forward error correction (trellis) structure, there is a branch that clearly defines each state element of each stage. In this example, the four branches starting from the state element Si point to the state elements a, b, c and d (not shown) of the next stage, each having a different probability coefficient τ (Sl5a), T (Sl5b) , r (Si, c) and r (Si, d). Conversely, each current state element may come from one of the four state elements of the previous stage. For example, the state element S3 of 0 in the phase tk has four branches connected to the state elements A, B, C, d (not shown) of the previous stage, each having a probability r(A, s3), r(B, s3 ), r(c, s3) and 7(d, s3). According to the post algorithm, the process of calculating these state matrices is collectively referred to as the Natural Recursion operation, and the value of each state element can be a positive probability value or a reverse probability value. In general, these probability values are also called metrics. After all the branch weights and path weights are obtained, the entire state matrix is stored in the path weight memory 206 shown in FIG. 2 in the form of these weights for subsequent ❹ backtracking unit 208 to survive. Path analysis, and maximum similarity calculation calculus. Figure 4 is an embodiment of a traceback unit 400 that may correspond to the traceback unit 208 of Figure 2. When performing the survival path analysis, it is necessary to find the one with the smallest path weight in each state element. As shown in Figure 4, there are four state elements in a phase, each with a path weight P (SD, P (S2), P (S3) and P (S4), so a total of three comparison choices are needed to find The minimum path weight. However, it is not known which state element the minimum path weight belongs to. Therefore, the traditional practice is to index these state elements. VIT08-0014I00-TW/0608-A41750TWf/Final/ 9 201039569 In this example, the index values of the four state elements are sequentially expressed as I(Si), I(S2) 'I(S3) and I(s4). A comparison selecting unit 41〇a receives the first and the first The index value I of the two state elements (S〇 and I(S2), and the path weight P (S〇 and (S2). The comparison selecting unit 410a includes a comparator 412, and compares the p (S〇 and P(( S2) to generate a selection signal #s. The comparator 412 can basically be a subtractor' and the selection signal #S can be a Boolean value representing a positive or negative sign. A selector 414 is based on the selection signal #3. The smaller one of P(S2) is selected as the output 'represented as P(A). At the same time, a selector 416 is also rooted.

According to the selection signal #S, the index value I (selecting the corresponding value from S〇 and I(S2) as the output 'is represented as 1 (A). The same 'a comparison selection unit 41% versus the third state element and The fourth state element performs the same process, selecting one of p(S3) and p(S4) as P(B), and simultaneously selecting one of the corresponding ones of l(ss) and i(s4) to output 1 (B). The 1(A) '1(B), P(A), P(B) are then subjected to the same comparison selection step in the comparison selection unit 410c, and the final output result p(c) is four. The minimum path weight in the state element, and I(c) is the (four) value of the state element having the minimum path weight. In summary, the comparison unit 4U) must simultaneously compare the index values. In order to find the minimum path weight (four), the state element of the phase is recorded as the first of the four. Although this embodiment only uses four state elements as an example, the same architecture can be extended to apply to more state elements, and this (4) is not limited thereto. Figure 5 is a traceback unit 500 in accordance with another embodiment of the present invention. In this real: in the example, you should not compare and select the index value of the state element. The temporary storage II is used to store the comparison of the path weights. Finally, the calculation method is used to find the solution. In the example, it is assumed that there is a - state energy = in the implementation center of the backtracking unit 500, the matrix is already prepared, and a path is stored in the VIT08-0014IOO-TW/0608-A41750TWf^inay 1〇, brother 2 diagram 201039569 weight memory 206 . Each phase in the state matrix contains 64 state elements. The backtracking unit 5 is replaced by the backtracking unit 208 of FIG. 2 for reading the path weight memory 206 and estimating the survival path. ❹

As shown in Fig. 5, the backtracking unit 500 includes six processing levels in series. The 64 state elements of a certain stage of a state matrix are rounded to the input end of the first processing level 510a, and finally the minimum path weight and corresponding index of the stage of the state matrix can be output by the sixth processing level 51 〇f . Each processing level includes a plurality of comparison selection units 7 (as shown in FIG. 7), which can compare the path weights of different state elements in pairs, find the smaller one, and output a flag to represent Comparing results. For example, since the comparison selection unit 700 contains two inputs, the operation of the comparison is actually subtraction. Therefore, the sign of the value obtained by subtracting the first input value from the second input value can be used as a flag to indicate the magnitude relationship between the two wheeled values. In other words, the correspondence between the two input values on the physical pin of the comparison selection unit 700 can be known through the flag value. Therefore, in this embodiment, the processing of the index value can be omitted, and the index value of the state element is directly determined by the flag. The heart's state element P0[0] to P〇[63] are input to the first processing level 51. After that, the odd state element is compared with the adjacent even state element, and the path weight is larger. The smaller the path weight is selected and output, expressed as 卩![〇] to PJ31]. Therefore, the number of rounds of the first processing level 510a is half the number of input values. As for the flag generated by each comparison selection unit 7, it is stored in a register & in the form of a Boolean value. In order to compare 64 state elements in pairs, a comparison selection unit 700 (not shown) is included in the first processing level 51A, and a total of 32 selection operations are performed, VIT08-0014I00-TW/0608- A41750TWf/Final/ n 201039569 In addition to generating 32 selection results Ρι[0] to Ρι[31], % flags ^[0] are also generated, which are sequentially stored in a 32-bit length. Ri. And so on, the first processing level 51〇a outputs the number of path weights that are halved by half? 1[0] to! > 1 [31] to the second processing level 51 (^, compared by 16 comparison selection units 700 (not shown) in the second processing level 510b, resulting in 16 comparison selection results, expressed as

Ο P2[15]. Similarly, the 16 comparison selection units 7 产生 also generate π flags, denoted as hearts (9) to Mb], and are stored in the 16-bit memory R2. % and so on, the third processing level outputs eight path weights 匕[7] to the fourth processing level 51〇d, and stores eight flag hearts [7] into the scratchpad & The fourth processing level 51〇d outputs four path weights P4[〇] to P4[3] to fifth processing level 510e, and stores four flags W0] to f4[3] to the scratchpad. The fifth processing level (10) is input: the path weights mP5[G] to p5[i] to the sixth processing level S1()f, and the flags are stored to the register R5 in the ^[1]. The last sixth processing level 5^ outputs the early-path weight p6, which is equal to the smallest of the path weights Pq[_^. The flag value f6 is a single-bit, stored in the register & When all the values of the registers Ri ~ & are complete, can you start to reverse the path weight? The corresponding index value of 6. The detailed embodiment will be explained in Fig. 8. @图图图 is a backtracking unit 6〇〇 of another embodiment of the present invention. Here, each HMm state element is taken as an example. To find the path VITOS-OOMIOO-TW/OeOB^nSOTW^!/ 12 201039569 from the state element, the three processing levels are required to include four comparison selection units 7 (8), and the first processing level 61 〇a P〇m performs pairwise alignment to round out four selections of eight path weights P〇[0] to post]. Where Pl_p. (9) and the second comparison result, expressed as p thorn is one of the smaller ones of P 〇 [2] and P0 [3], with one of the smaller ones, Pji] four bits ' and the first processing level 6; = Push. The scratchpad contains 700 output flags, which are corresponding to the corresponding bits in the four comparison selection units of T, so the temporary storage 1 1 fl[3] ’ exists in the register κ

Just for the ruler. The time value of the R1 towel may sequentially indicate that the fourth processing layer and the level 6x〇a are taken out to the second processing in the 61% of the processing level [[ π 700 仃 仃 selection comparison to generate Two comparisons select results, (10)] and P2[l]. At the same time, two corresponding flags _] and f2(1) are also stored on the corresponding bits in the register R·2, which is expressed as the ruler 2[0] and . The last processing level 610c includes only one comparison selecting unit 700, and after receiving the path weights P2[0] and Ps[1] for comparison, a comparison result P3 of a single bit is output. The comparison selection result p3 is the minimum of the eight path weights P 〇 [0] to p0 [7]. As to which state element is actually associated, it needs to be derived from the values in the registers Ri, R2 and R3. The detailed derivation process will be explained in Figure 8. The embodiments of Figs. 5 and 6 illustrate the case of 64 state elements and 8 state elements, respectively. However, it can be inferred that the processing level of the present invention can be elastically extended to n to apply to 2n state elements (η is a natural number). The derivation principle of the index value is the same, and can be flexibly applied with the value of η. Figure 7 is an embodiment of a comparison selection unit 7〇0. Each comparison VIT08-0014IOO-TW/0608-A41750TWfiTinal/ 13 201039569 The selection unit 700 includes two inputs, each for receiving path weights of different state elements, such as IVJi] and pn l[i+1]. The comparison selecting unit 7A includes a comparator 720 for comparing the input two path weights Pn i[i] and Pndi+1]. The comparator 72 performs a subtraction operation, and the output flag fn[i] can be a sign, so that it can be easily judged from which input pin the smaller value comes from. For example, the flag may be a Boolean value, the flag "value 0 represents the first input, and the flag value 1 represents the second input. The selector 710 in the comparison selection unit 700 may According to the flag, one of the two path weights PwW or pn_1[i+1] is selected as Pn[i], where the value of i is an index variable. Rn to derive the index value process. Take the comparison result of the 64 state element of Figure 5 as an example. Finally, the register value stored in the register is a Boolean value of a unit. As indicated by the thick line, the temporary crying The value is 〇, indicating that its minimum path weight is from P5[〇]. For convenience of convenience, a Boolean variable B〇' is temporarily assigned here as: B0=R6=〇. 〇 Then push back to the fifth processing level 51 〇e. Since the minimum path weight is known to be from P5[0], the register address R5[0] is read to further find the source of the previous layer. In this embodiment, the address R5[〇] is assumed. The value of 1 represents that the value of the path weight P5[0] is from the path weight of the fourth processing level? 4[〇1] (for convenience of description, the value in '[] Binary representation). Here a Boolean number B! is assigned, denoted as: Then push back. To the fourth processing level 510d, since the minimum path weight is known to be from P4[01], the scratch register bit is read. The Boolean value in the address RdOl] to VIT08-0014I00-TW/0608-A41750TWi/Fmal/ 14 201039569

Look for the source of the previous layer. In the case of I 1, the path weight can be derived. The value in the _' address R4[01] is assigned here - the Boolean variable, and the table is the processing level of P3,]. Then push back to the third processing level

The value from P3[011], 遂 reads the temporary f c, because the minimum path weight is known to find the upper-layer source in a step-by-step manner. ^The Boolean value in the address R3[〇11] is 0, so the path weight can be derived. In the example, the value-Blinn variable B3 in the address R3[011] is expressed as: - layer source It is P2[G11G]. Here, the next pushback to the second processing layer is derived from (10) off, 遂 read staging: 'Because the minimum path weight is known to further find the Boolean value in the upper-layer source existence = R2[_], the value For i, it can be derived from the upper layer of 'address _11〇', .u4tr: seeking, original, 疋pi[〇u〇i] (decimal is represented as PJ13]). Here, a Boolean variable b4 is deducted, and then pushed back to the first processing level 5l〇a, since the known minimum path weight is from Ρι[οη〇Π, 遂 reads the scratchpad address Ri [Curry's cloth The forest value 'into the step-by-step search for the original source. In this example, the value of Ri[〇 emitter^叩 is 〇, so the source of the previous layer is p〇[0 emitter 11〇1〇] (the decimal is denoted as P〇[26]). Here, using a Boolean variable Bs, it can be expressed as: From the above-mentioned reverse push and private, it can be found that the source of the minimum path weight can be sequentially derived from the register value of the subsequent processing level. And finally all the Boolean variables are strung together to get the value 'just the minimum path weight of the 64 state elements VIT08-0014I0Q-TW/0608-A41750TW f/Final/ 15 201039569 Index value: [Β〇Β1Β2Β3Β4Β5]= [〇11〇1〇]=26 value, the implementation found that the retrospective unit can determine the index B〇=Rn[〇] according to the following formula

Bl=Rn-l[B〇] Ο ❹ • · ·

Bn=Ri[B〇B1B2B3...Bn.1]

Bn] where 1 to Rn are the first processing level to the nth processing level, and 3〇 to Bn are Boolean values or! , which is obtained by the specific address in the corresponding temporary storage, and the specific address is expressed as cloth =

The binary value of Bo to Bn is arranged; w represents the index value corresponding to the state 7G with the smallest path ^, and the binary value of the table value. The value table is not arranged for the Boolean value Β θ] Β η. The second embodiment highlights the advantage of finding the minimum path weight ‘no 4 to repeat the selection step for the index value. Port f should use the path weight value comparison selection process to leave the flag, you can push and index the value. Therefore, the back-up single-opening M b U is a long-term reduction of the hardware area of 208, which saves costs.虽 Although the scouring unit 208 finds the minimum state element of each order ^ 卽 ring 吝 4 玟 逐 one by one, the 归 return to the live path. According to this survival path, a one-to-score similarity ratio (LLR) operation can be performed to take the result of the true decoding of the VIT〇8-O014IO0-TW/0608-A41750TW^aI/J6'. 201039569 The state matrix operation structure of the present invention is not limited to a radix-4 trellis structure, and can also be applied to a radix-22 trellis structure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an architectural diagram of a communication system; Fig. 2 is an architectural diagram of a Viterbi decoder 126; Fig. 3 is a schematic diagram of a state matrix; FIG. 5 is a backtracking unit 500 according to one embodiment of the present invention; FIG. 6 is a backtracking unit 600 according to one embodiment of the present invention; FIG. 7 is an implementation of the present invention. The comparison selection unit 700 is one of the examples; the eighth diagram is a schematic diagram for deriving the index value. [Main component symbol description] 110 transmitter 102 antenna 120 receiver 124 analog digital converter 202 branch weight processor 206 path weight memory 400 backtracking unit

104 antenna 122 radio frequency module 126 Viterbi decoder 204 addition comparison selection unit 208 traceback unit 410a~410c comparison selection unit 412 comparator 414, 416 selector 416 selector 400, 500, 600 traceback unit 510a~510f first ~ Six processing level 610a first processing level 610b second processing level VIT08-0014IOO-TW/0608-A41750TW£Tiiial/ 17 201039569 610c third processing level 700 comparison selection unit 710 selector 720 comparator

VIT08-0014I00-TW/0608-A41750TWf/Final/ 18

Claims (1)

201039569 VII. Patent Application Range·· 1. A Viterbi decoder, comprising: a State Metric memory for storing a state matrix comprising a plurality of stages, each stage comprising 2n a state element, each state element has an index value and a path weight, and corresponds to a plurality of branch metrics (Branch Metric); and a backtracking unit, including the first to the η processing levels, in series, for searching The minimum path weight and the corresponding index 每一 value of each stage in the state matrix are obtained to establish a survival path, wherein: each processing level includes: at least one Compare Selection Unit (CSU), each for comparison Two different state elements have path weights and output the smaller ones, and output a flag to represent the comparison result; and a register to record the flag output by each comparison selection unit; wherein the backtracking unit is based on all processing The hierarchical register configuration derives the index value of the state element with the smallest path weight in one phase. Q 2. The Viterbi decoding according to Item 1 of the patent application scope, wherein each comparison selection unit comprises: a first input end and a second input end, each for receiving path weights of different state elements; Comparing a path weight from the first input end and the second input end, and outputting a flag to record one of the first input end and the second input end having a smaller path weight; And a selector for selectively outputting the path weight received by the first input terminal or the second input terminal according to the flag. VIT08-0014I00-TW/0608-A41750TW£Tinal/ 19 201039569 3. If the patent is rushed to 9 TS, the flag is - Brin, the flag mq Viterbi _, where the value 1 represents the second round Into the end. The first round of the Go, and the flag, is more sequential than the one of the 7Cs, and the 2n in the solid ratio is a natural number. ...different index values, 第5-of-the-norm: the Viter, the two items, for pairwise comparison, screening half of the "ds2π state elements: 6. *application fine (four) fifth The dimension of the item = level hopper, the amount of each processing level after the second processing level is the comparison selection unit of the previous processing level, the number of selection units last - the processing level contains a comparison selection unit and 〇 represents the state The value of the 2 stagnation state element in the phase of the matrix is one of the weights. τ,, there is a small path: 7. The Viterbi decoder described in item 5 of the patent scope, 2^2 The = level of the scratchpad contains a hatred element, storing the corresponding two ratios to select the flag that is rounded out; the second level of processing after each processing shield level of the cache number One year of the number of bits of the register of the nitrogen-based level; and the register of the last fluorine level includes a 彳1L element. S. The reading of the Viterbi grammar as described in Item 7 of the patent , VTT08-00U100-TW/060S-Mn5OTWffPim\/ 2〇201039569 Compare selection materials' in order to correspond to the same In the case of the Viterbi solution described in Item 8 of the standard, the minimum value of the weight is derived from the first element of the previous processing level. 罘 into a comparison list: 10· > The Viterbi decoder of the nine items, the buffer group of the processing group; the temporary storage comparison unit of the processing level to the last processing level; the specific processing ratio of the processing level is based on the weight of the first processing layer === know from the specific comparison selection unit, the minimum path corresponding to the specific round entry is the index value, the rain enters the 鳊, and the second: the 2nd dimension of the 2nd dimension of the Viterbi solution The value of the index is: 〇J Bl=Rn-l[B〇] ^Rn^BgBj] B3=Rn-3[B〇B1B2] Bn= Ri[B〇B1B2B3...Bn.I] Imin:=[B0B1B2B3...BnJ where Ri to Rn is the _ processing level of the system is the Boolean value ! or !, the processing level of the temporary VIT08-0014I00 -TW/0608-A41750TWi^iIial/ 2} ° : The local area is corresponding to the temporary register 201039569, where R! to Rn are the first processing level to the nth processing level register, Β〇 to Βη For the Boolean value 1 or 1, it is obtained from the corresponding register heart to the specific address in Ri, and the specific address is expressed as the binary value of the Boolean value Β to Βη; The index value corresponding to the state element having the smallest path weight is represented by the binary value of the Boolean value ^ to the queue. 12. The Viterbi decoder according to claim 1, wherein the The backtracking unit further performs a one-to-seven similarity ratio (LLR) operation according to the state matrix; wherein the state matrix operation structure is a radix-4 trellis structure or a radix_22trelUs structure. The Viterbi decoder according to claim 1, further comprising a plurality of addition comparison selection (ACS) units operating in parallel for performing a natural recursion according to an input sequence to generate the The state matrix 'stores the state matrix in the path weight memory. ° ❹ 14. The Viterbi decoder of claim 13, wherein the natural recursive operation uses a log-to-post probability (Log_MAP) algorithm, a maximum log-to-mass probability (Max Log-MAP) algorithm, or enhancement. One of the largest logarithmic probability (Enhanced Max Log-MAP) algorithms. VIT08-0014I00-TW/O608-A41750TWf/Final/ 22