TW201039033A - Subpixel structure and liquid crystal display panel - Google Patents

Subpixel structure and liquid crystal display panel Download PDF

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Publication number
TW201039033A
TW201039033A TW98113724A TW98113724A TW201039033A TW 201039033 A TW201039033 A TW 201039033A TW 98113724 A TW98113724 A TW 98113724A TW 98113724 A TW98113724 A TW 98113724A TW 201039033 A TW201039033 A TW 201039033A
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Taiwan
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sub
transistor
scan line
liquid crystal
crystal display
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TW98113724A
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Chinese (zh)
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TWI408474B (en
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Chien-Cheng Chen
Yu-Cheng Lin
Wen-Ming Hung
Yung-Hsun Wu
Chueh-Ju Chen
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Innolux Display Corp
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Publication of TWI408474B publication Critical patent/TWI408474B/en

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Abstract

A subpixel structure for liquid crystal display is disclosed. The pixel structure is disposed between a first substrate and a second substrate, in which the subpixel structure includes a first portion and a second portion, a data line, a first scan line and a second scan line. A first transistor is disposed on the first scan line while connected to the first portion of the subpixel structure, a second transistor is disposed on the first scan line while connected to the second portion of the subpixel structure, and a third transistor is disposed on the second scan line while connected to the second portion of the subpixel structure.

Description

201039033 、發明說明: 【發明所屬之技術領域】 本發明係關於一種液晶顯示器的子晝素結構,尤指一種可 提升電容充電能力的子晝素結構。 【先前技術】 Ο Ο 薄膜電晶體液晶顯示器(thin film transistor liquid crystal display,TFT-LCD)主要是利用成矩陣狀排列的薄膜電晶體, 並配合適當的電容、轉接墊等電子元件來驅動液晶晝素,以產 生豐富亮麗的圖形。由於薄膜電晶體液晶顯示器具有外型輕 薄、耗電量少以及無輻射污染等特性,因此被廣泛地應用在筆 記型電腦(notebook)、個人數位助理(PDA)等攜帶式資訊產品 上’甚至已有逐漸取代傳統桌上型電腦之CRT監視器以及家 用電視的趨勢。 目前薄膜電晶體液晶顯示器主要由薄膜電晶體陣列基 板、彩色濾光陣列基板以及填充於薄膜電晶體陣列基板與彩色 濾光陣列基板之間的液晶層所構成。其中薄膜電晶體陣列基板 是由多個陣列排列的薄膜電晶體以及與每個薄膜電晶體對應 配置的晝素電極所組成。彩色濾光陣列基板則具有複數個陣列 ^列而成的彩色濾光片,使液晶顯示器的每一畫素呈現豐富亮 麗的顏色。每個畫素電極與對應的薄膜電晶體一同組成一畫素 結構’並使用薄膜電晶體來作為每個畫素結構的開關元件。另 外’為了㈣個別畫素的灰階,通常會經由複數條相互垂直交 錯的掃描線(scan or gate line)與資料線(data 〇r 特定的畫素’並藉由提供適當的操作電壓,以顯轉應此 用ϋ’上述的畫素電極的部份區域通常^覆蓋於 知描線或共用配線(common line)上,以形成f 。 針對顏色顯示動作,每一書素主要由=個 畫=通常又可再分隔為兩部份,使液晶二 上達到更域峨細峨_。 3 201039033 不同部份又各自可由-條掃描線與-顆薄膜雪曰 通常會分別對對各子3的 flGf washo·果’ 生更多指向。 施加不同電壓,使液晶產 然而’為了使子畫素中的兩個部份分別 麟辭㈣T,上勒射的各掃ί線ί 啟寸間㈢大f田縮短,例如在1024χ768解 ,,,間會從原本的16 . 66毫秒㈣縮:為;' 刃毫[Technical Field] The present invention relates to a sub-cell structure of a liquid crystal display, and more particularly to a sub-tenon structure capable of improving the charging capability of a capacitor. [Prior Art] th Ο Thin film transistor liquid crystal display (TFT-LCD) mainly uses thin film transistors arranged in a matrix, and is driven by suitable electronic components such as capacitors and transfer pads. Alizarin to produce rich and beautiful graphics. Thin film transistor liquid crystal displays are widely used in portable information products such as notebooks and personal digital assistants (PDAs) because they are thin, low in power consumption, and free from radiation pollution. There is a trend to gradually replace CRT monitors and home TVs of traditional desktop computers. At present, a thin film transistor liquid crystal display mainly comprises a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer filled between the thin film transistor array substrate and the color filter array substrate. The thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array and a halogen electrode arranged corresponding to each of the thin film transistors. The color filter array substrate has a plurality of arrays of color filters, so that each pixel of the liquid crystal display has a rich and bright color. Each of the pixel electrodes forms a pixel structure together with the corresponding thin film transistor and uses a thin film transistor as a switching element for each pixel structure. In addition, in order to (4) the gray scale of individual pixels, usually through a plurality of scan or gate lines and data lines (data 〇r specific pixels) and by providing appropriate operating voltage, The partial area of the above-mentioned pixel electrode is usually covered on the known line or the common line to form f. For the color display action, each book is mainly composed of = picture = Usually, it can be further divided into two parts, so that the liquid crystal two can reach a more fine area. _ 3 201039033 Different parts can be separated by - scanning lines and - film ferrets usually have opposite flGf of each sub 3 Washo·fruit's life more pointing. Applying different voltages to make the liquid crystal produced, however, 'in order to make the two parts of the sub-pixels separate (4) T, each of the sweeping lines of the upper shots Shortened, for example, at 1024 χ 768 solution, ,, will be reduced from the original 16.66 milliseconds (four): for;

Ο ==_剩4 ·16毫秒。由於每條掃描St 間大幅降低’晝素結構中連接掃描線的儲存ΐ 谷即會有充電能力不足的問題。 _电 【發明内容】 —本,縣要揭露—種子晝素結構峨善習知子結 容易在尚頻驅動下造成充電能力不足的問題。 一、》 本發明係揭露-觀晶顯示||之子畫素結構,設於一第一 基板與一第二基板之間。子晝素結構包括一第一部份與一第二 資,?ί、一第一掃描線以及一第二掃描線與該資料線 外,子晝素結構另包括一第—電晶體設於第—掃 =並連接子晝素結構之第一部份,一第二電晶體設於第一掃 描線並連接子晝素轉之第二部份以及—第 二掃描線並連接子畫素結構之第二部份。㈣ 、本發明另一實施例係揭露一種驅動液晶顯示面板的方 法二首先提供一子晝素結構,且子畫素結構具有—第一部份與 一第二部份、一資料線、一第一掃描線以及一第二掃描線與資 料線交,設置。然後於一第一時間週期由資料線輸入一第一電 壓並對第一部份進行充電並同時對第二部份進行預充電,接著 於一第二時間週期由資料線輸入一第二電壓並僅對該第二部 份進行充電。 本發明主要在一子晝素結構中同時設置三顆或四顆薄膜 4 201039033 充 12^\的頻率驅動下可提升晝素中 晶體的架構,其中°依據本發_三顆薄膜電Ο ==_ remaining 4 · 16 milliseconds. Since each scanning St greatly reduces the storage valley connecting the scanning lines in the [in the structure of the halogen], there is a problem that the charging ability is insufficient. _Electric [Summary] - Ben, the county wants to expose - the structure of the seed 昼 峨 善 善 善 善 善 善 善 善 善 善 易 易 易 易 易 易 易 易 易 易 易 易 易 易I. The present invention discloses a sub-pixel structure of a viewing display, which is disposed between a first substrate and a second substrate. The sub-satellite structure includes a first part and a second part,? ί, a first scan line and a second scan line and the data line, the sub-tenon structure further comprises a first-electrode set on the first part of the first-scan-and-connected sub-halogen structure, The second transistor is disposed on the first scan line and connects the second portion of the sub-crystals and the second scan line and connects the second portion of the sub-pixel structure. (4) Another embodiment of the present invention discloses a method for driving a liquid crystal display panel. First, a sub-pixel structure is provided, and the sub-pixel structure has a first portion and a second portion, a data line, and a first A scan line and a second scan line intersect with the data line and are set. And then inputting a first voltage from the data line and charging the first portion in a first time period and simultaneously precharging the second portion, and then inputting a second voltage from the data line in a second time period and Only the second portion is charged. The invention mainly provides three or four thin films simultaneously in a sub-halogen structure. The structure of the crystal in the alizarin can be improved by the frequency driving of 12^390, wherein the crystal is based on the present invention.

二部鮮«結構S 線上分別設置兩顆_ϋ曰在子晝素的兩條掃描 子畫素結構中的兩除了可同時對原本的 素進行預充電。由於寺對下一個子晝 Ο Ο 素中的各部份固子晝 ,触達觀善m果 請同時參照圖!與圖2,圖i為本發 : 冓之晝素等效電路圖,圖2“ϊ 二體陣基板之間’且各子晝素結構10均包括 =平設置的掃描線12、14、一垂 ’= 貧料線16以及三顆薄膜雷曰舻1S加π \咏 14的 γ 與雜Two of the two fresh «structure S lines are respectively set to two pre-charges of the original elements in the two scan sub-pixel structures of the sub-segment. Because the temple is on the next sub-昼 Ο Ο 的 素 素 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼With FIG. 2, FIG. 1 is a schematic diagram of the equivalent circuit of the 昼 昼 , , , , , , , , , , , 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且'= poor material line 16 and three thin film Thunder 1S plus π \咏14 γ and miscellaneous

Gate)結構或上閘極(T0p Gate)結構,且每個子晝 構10包括兩個部份,例如一第一部份24與—第二部份%。 f本實施例中’薄膜電晶體18是設於掃描線12上並控制子書 ^結構10中第-部份24的畫素電極252,薄膜電晶體2〇 ^ 叹於掃描線12上並控制子晝素結構1〇中第二部份%的晝素 電極254 ’而薄膜電晶體22則是設於掃描線14上並控制子書 素結構10第二部份26的晝素電極254。 、如圖1的等效電路圖所示,薄膜電晶體18的汲極28是電 連接至子畫素結構10中第一部份24的電容3〇 ,閘極32是連 5 201039033 =極34則是連接至㈣線16。薄膜電晶體 f的〆及極36疋連接至子晝素結構10中第二部份26的電容 38,閘極奶是連接至掃描線12,而源極42則是連接至資料 ^ 16。薄膜電晶體22❾汲極μ是電連接至子晝素結構1〇中 _46是連接掃描線14,而源極48 if 1 線16。在本實施例中,設在子晝素結構1〇中 ίΤ电Γ 、%可包括儲存電容(storage caPacit〇r)及液晶電容 (lquid crystal capacitor)等’但不偈限於此。 Ο Ο ㈣子畫素結構ig時’可先開啟掃描線12,藉由開啟 ’來同時對子畫素結構ι〇的第一部份24與 获二二=丁充電。接著關閉掃描線12,開啟掃描線14, =電晶體22來對子晝素結構1G的第二部份26再 二辛ί入不驅動子畫素時,可在不同灰階下使對子 至素輸入不同電壓,達到分壓的效果。換句話說, m三顆薄膜電晶體18、2〇、22搭配兩條掃ΐ 素的充電時間,達到預充的效果。 曰加于旦 照圖3’.圖3為本發明第一實施例 Ϊ一畫素結構6。之灰階與時序圖。現以同行之畫素 構如6〇第主3f所示’本發明之薄膜電晶體液晶顯示器的 素π,60主要可由三個子晝素所組 2 ί义ίί構亦可由三個以上的子晝素來組成。每—個子書為素i J為兩個部份’例如紅色子晝素62分隔為—第一杳= =18^^的畫素結構6()主要包括三條資料線8()^:Gate structure or top gate structure, and each sub-structure 10 includes two parts, such as a first portion 24 and a second portion %. In the present embodiment, the thin film transistor 18 is a pixel electrode 252 disposed on the scanning line 12 and controlling the first portion 24 of the sub-structure 10, and the thin film transistor 2 is sighed on the scanning line 12 and controlled. The second portion of the sub-halogen structure is a halogen electrode 254', and the thin film transistor 22 is a halogen electrode 254 disposed on the scanning line 14 and controlling the second portion 26 of the sub-book structure 10. As shown in the equivalent circuit diagram of FIG. 1, the drain 28 of the thin film transistor 18 is electrically connected to the capacitor 3 of the first portion 24 of the sub-pixel structure 10, and the gate 32 is connected to 5 201039033 = pole 34 Is connected to (four) line 16. The turns and turns 36 of the thin film transistor f are connected to the capacitance 38 of the second portion 26 of the sub-tenon structure 10, the gate milk is connected to the scan line 12, and the source 42 is connected to the data ^16. The thin film transistor 22 is electrically connected to the sub-tenox structure 1 _46 is connected to the scan line 14, and the source 48 is 1 line 16. In the present embodiment, it is provided in the sub-cell structure, and the % may include a storage capacitor (storage caPacit〇r) and a liquid crystal capacitor (such as a liquid crystal capacitor), but is not limited thereto. Ο Ο (4) When the sub-pixel structure ig ’, the scan line 12 can be turned on first, and the first part 24 of the sub-pixel structure ι〇 is simultaneously charged by the turn-on ’. Then, the scan line 12 is turned off, and the scan line 14 is turned on, and the transistor 22 is used to make the pair of pixels in the different gray scales when the second portion 26 of the sub-halogen structure 1G is re-injected to the sub-pixel. Input different voltages to achieve the effect of partial pressure. In other words, the charging time of m three thin film transistors 18, 2, 22 combined with two brooms achieves the effect of pre-charging. 3 is a diagram of a first pixel structure 6 of the first embodiment of the present invention. Gray scale and timing diagram. Now, the π, 60 of the thin film transistor liquid crystal display of the present invention can be mainly composed of three sub-systems, or can be composed of three or more sub-units. Has always been composed. Each of the sub-books is a two-part element, i. For example, the red sub-element 62 is separated into - the first 杳 = = 18^^ pixel structure 6 () mainly includes three data lines 8 () ^:

及/、負料線80、82、84交錯巧署沾兩攸这A 其中掃描線88上設有六個薄膜電晶體9:::::。 脱售,分別控制各子晝素的其卜部份。舉例 6 201039033 Ϊϋΐ膜電晶體94、96以及資料線8〇 -同控制紅色子畫 9S碰份與第二部份70,掃描線88、薄膜電晶體 ^ !及貝料線82 —同控制綠色子晝素64的第一部份72 與弟一°附74 ’而掃猶犯、薄膜電晶體102、104及資料線 84則-同控制藍色子畫素66的第—部份%與第二部份%。 =地,掃描線90上設有三個薄臈電晶體1〇6、1〇8、ιι〇, ❹ ❹ W、薄膜電晶體106以及資料線80 一同控制紅色 ί ΐ t的第二部份7〇,掃描線90、薄膜電晶體108以及資 ^制綠色子晝素64的第二部份外而掃描線90'、 體以及貧料線84則一同控制藍色子畫素66的第 一邵 TO 78。 总一6G左邊顯示晝素電極與所接收之槪bt:壓之關 極:LW tP1 中第—部份68的晝素電 二-至t2'間週期内所接收到的灰階電壓,而π則為紅 ㈣^ 62>中第二部份70的畫素電極於t=〇至t2時間週期内 僅ΐϊί的灰階電壓。以下搭配晝素結構60右邊的時序圖並 晝素進行卿,㈣贿紅色子晝素62的第 /二部份7G的充電狀況及時序進行說明。在t=〇 94二夺Ί’ηΓ任何電壓輸入各掃描線88、90且各薄膜電晶體 脊祕均呈賴敵態,因此子晝素62的第一 ^te) 〇 入啟薄膜電晶體94、96的閘極並由資料線80輸 同時ί(二=二電笛壓)至薄膜電晶體94、96的源極然後 P^ ίί第附68與第二部份70的晝素電極在t1時 掃μ H16毫秒内即接收到3V的灰階電壓。接著關閉 5線88亚開啟掃描線9〇,由資料線8〇、82、84在t2時間 一 Φ二如4 · 16〜第8 . 33毫秒内的4 · 16毫秒間輸入一第 7—W電壓)至薄膜電晶體106的源極並對第二部份 仃充电。由於薄膜電晶體94、96在此時刻已關閉,因此 7 201039033 . ,一部份68的晝素電極所接收的灰階電壓是維持在3V而第 - -部70的晝素電極所接㈣丨的灰階電壓則是在5v。 * /青再參照圖4至圖6,圖4為本發明另一實施例設置四顆 $膜電晶體於子晝素結構之晝素等效電路圖,圖5為圖4中子 畫素,構之晝素示意圖,而圖6則為本實施例實際子畫素結構 之不意圖。如圖5及圖6中所示,本實施例的子畫素結構12〇 主要包括兩條水平設置的掃描線122、124、一垂直交錯掃描 ,122、124的貢料線126、一共同電極262以及四顆薄膜電 日日體128、130、132、134分別連接掃描線122、124與資料線 〇 126。如上述實施例,每個子晝素結構120主要包括兩個部份, 例如包括晝素電極256的第一部份136與包括約略V型晝 極258的第二部份138。在本實施例中,薄膜電晶體128 是设於掃描線122上並連接至子畫素結構12〇第一部份136的 晝素電極256,薄膜電晶體13〇是設於掃描線122上並連接至 子畫素結構120第二部份138的畫素電極258,薄膜電晶體132 則是設於掃描線124上並連接子畫素結構12〇第二部份138的 晝素電極258 ’薄膜電晶體134是設於掃描線124上並連接下 一個子畫素結構第一部份14〇的晝素電極260。 、如圖4的等效電路圖所示,薄膜電晶體128的汲極142是 ,接至子晝素結構120中第一部份136的電容144,閘極146 疋連接至掃描線122,而源極148則是連接至資料線。後 ^t 130 150 138曰的電容152 ’閘極154是連接至掃描線122,而源極 貝J疋連接至> 料線126。薄膜電晶體132的没極158是連接至 =晝素結構120中第二部份138的電容152,閘極16〇是連接 掃描線124,而源極162則是連接至資料線126。薄膜電晶體 ,的沒極I64是連接至下一個子晝素結構中第一部份_的 電f 166,閘極168是連接掃描線124 ,而源極17〇則是連接 至貢料線126。在本實施例中,設在子晝素結構12〇中的電容 144、152、166可包括儲存電容及液晶電容,但不侷限於此。 8 201039033 動-ΐΐϊ:’Λ'為本發明第二實施例在12°Hz頻率下驅 曰白與時序圖。如6圖所示,本發明之薄臈電 = -/:,·、、員不益的各畫素結構18〇主要由三個子晝素 圭丰紅色子畫素182、一綠色子晝素184以及一 i色子 86。但不以此為限’各晝素結構亦可由三個以上的 J來組成。每—個子晝素又再分隔為兩個部份,例如紅色子; 素182分隔為一第一部份188與-第二部份190,綠色子書: 184^分隔第—部份192與—第二部份194,藍色子晝素 ϋί —第—部份196與—第二部份198。本實施例的晝素結 構80主要包括三條資料線2〇〇、2〇2、2〇4以及 : 202、204交錯設置的三條掃描線2〇8、21〇、212。' β ❹ ❹ 在本實施例中,掃描線2〇8、21〇、212上各設有六個薄膜 電晶體,分別對應各子晝素的其中一部份。舉例來說,掃描線 208上6免有薄膜電晶體216、218、220、;222、2之4、226,其中 薄膜電晶? 216、218、220用來控制上-個晝素結構中紅色、 綠色以及藍色子畫素結構的第二部份,而薄膜電晶體222、 224、226則用來控制晝素結構18〇中紅色、綠色以及藍色子 晝素結構182、184、186的第一部份188、192、1%。掃描線 210上設有薄膜電晶體228、230、232、234、236、238,其中 薄膜電晶體228、230、232用來控制畫素結構18〇中紅色、綠 色以及藍色子畫素結構182、184、186的第一部份188、192、 196 ’而薄膜電晶體234、236、238則用來控制晝素結構180 中紅色、綠色以及藍色子畫素結構182、184、186的第二部份 190、194、198。掃描線212上設有薄膜電晶體240、242、244、 246、248、250,其中薄膜電晶體240、242、244用來控制晝 素結構180中紅色、綠色以及藍色子晝素結構182、184、186 的第二部份190、194、198,而薄膜電晶體246、248、250則 用來控制下一個畫素結構中紅色、綠色以及藍色子畫素結構的 第一部份。 晝素結構180左邊顯示晝素電極與所接收之灰階電壓之 9 201039033 Ο Ο 關係示意圖,例如Ρ1為紅色子晝素182中第一部份188的晝 素電極於t=0至t2時間週期内所接收到的灰階電壓,而ρ2則 為紅色子畫素182中第二部份190的晝素電極於t=〇至t2時間 週期内所接收到的灰階電壓。以下搭配晝素結構18〇右邊的時 序圖並$以驅動一個子晝素進行說明,例如僅對紅色晝子晝素 182的第一部份188與第二部份19〇的充電狀況及時序進行說 明。在t=o之前的上一個晝面時,薄膜電晶體216、222的閘 =會^由掃描線開啟然後由資料線2〇〇輸入一電壓(例如5V電 壓)至薄膜電晶體216、222的源極並同時對薄膜電晶體216所 控制上一個晝素中紅色子晝素的第二部份(圖未示)進行充電 以及對紅色子畫素188的第一部份188進行預充電。紅色子晝 素182中第一部份188的晝素電極在t=〇之前的時間週期即接 ,Ϊ、5ν的灰階電壓。接著關閉掃描線208並開啟掃描線210, 由貝料線200輸入-3V電壓至薄膜電晶體228、234的源極 並同時對紅色子晝素188的第一部份188及第二部份19〇進行 ^電。紅色子晝素182中第一部份188及第二部份19〇的晝素 t=0至tl的時間週期即接收到w的灰階電壓。接著關 ^知描線210並開啟掃描線212,由資料線2〇〇輸入一 5v電 ^薄膜電晶體24〇、246的源極並對第二部份19〇及下個晝 色子晝素結構的第一部份(圖未示)進行充電。由於 ^電日日體228、236在此時刻已關閉,因此第一部份188的 =,極在tl至t2的時間週期所接收的灰階電廢是維持在3V 二部份190的晝素電極所接收到的灰階電壓則是在5v。 四顆ί μ本發明主要在—子畫素結射同時設置三顆或 升早體’使子4素結構在12GHZ _率驅動下可提 各雜的充電時狀題充魏力。依據本發明的 Μ Φ ί结電晶體的架構’其中兩顆薄臈電晶體是設於子畫素結 —條掃描線並分別控制子畫素結構的第-部份與第 而/ 一顆薄膜電晶體則設於第二條掃描線並控制子畫 α構的第二部份’進而有效解決高更新頻率下,各子晝素結 201039033 Ο 以上所述僅為本發;之車;實:;;,w 與修飾,皆應屬本發明之涵蓋範圍。 本J L為本發明第一實施例設置三顆薄膜電晶體於-子晝 素結構之晝素等效電路圖。 圖2為圖1中子晝素結構之晝素示意圖。 Ο 圖3為本發明第一實施例在ρΟΗζ頻率下驅動一查士 構之灰階與時序圖。 旦 圖4為本發明另一實施例設置四顆薄膜電晶體於 結構之畫素等效電路圖。 ' 至’、 圖5為圖4中子晝素結構之畫素示意圖。 圖6為圖4中實際子晝素結構之示意圖。 圖7為本發明第二實施例驅動一晝素結構之灰階與時序 圖0 【主要元件符號說明】 1 Π 7 ▲士 ..... 子畫素結構 12 掃描線 掃描線 16 資料線 薄膜電晶體 20 薄膜電晶體 11 201039033 22 薄膜電晶體 26 第二部份 30 電容 34 源極 38 電容 42 源極 46 閘極 60 畫素結構 64 綠色子晝素 68 第一部份 72 第一部份 76 第一部份 80 資料線 84 資料線 90 掃描線 96 薄膜電晶體 100 薄膜電晶體 104 薄膜電晶體 108 薄膜電晶體 120 子晝素結構 124 掃描線 128 薄膜電晶體 132 薄膜電晶體 136 第一部份 140 第一部份 144 電容 148 源極 152 電容 156 源極 160 閘極 164 汲極 168 閘極 180 晝素結構 184 綠色子晝素 188 第一部份 24 第一部份 28 没極 32 閘極 36 汲極 40 閘極 44 汲極 48 源極 62 紅色子晝素 66 藍色子晝素 70 第二部份 74 第二部份 78 第二部份 82 資料線 88 掃描線 94 薄膜電晶體 98 薄膜電晶體 102 薄膜電晶體 106 薄膜電晶體 110 薄膜電晶體 122 掃描線 126 貧料線 130 薄膜電晶體 134 薄膜電晶體 138 第二部份 142 汲極 146 閘極 150 汲極 154 閘極 158 沒極 162 源極 166 電容 170 源極 182 紅色子晝素 186 藍色子畫素 190 第二部份 12 201039033And /, negative material lines 80, 82, 84 are intertwined with two 攸. This A has six thin film transistors 9::::: on the scanning line 88. Disposal, respectively control the subdivision of each sub-quality. Example 6 201039033 Ϊϋΐ film transistor 94, 96 and data line 8 〇 - control red sub-paint 9S hit and the second part 70, scan line 88, thin film transistor ^ ! and shell line 82 - control green The first part of the sapphire 64, 72, and the younger one with 74', and the smuggler, the thin film transistor 102, 104 and the data line 84 - the same as the control of the blue sub-pixel 66 - part and second Part%. = ground, scan line 90 is provided with three thin germanium transistors 1〇6, 1〇8, ιι〇, ❹ ❹ W, thin film transistor 106 and data line 80 together to control the second part of red ΐ 〇 t〇 The scan line 90, the thin film transistor 108, and the second portion of the green sub-halogen 64 are externally scanned, and the scan line 90', the body and the lean line 84 control the first SHA of the blue sub-pixel 66 together. 78. The left side of the total 6G shows the gray scale voltage received in the period between the halogen electrode and the received 槪bt: pressure: the first part of LW tP1 in the period from the second to the t2', and π Then, the pixel electrode of the second portion 70 of the red (four)^62> is only 灰ί gray scale voltage in the time period from t=〇 to t2. The following is a description of the timing chart on the right side of the structure of the elementary structure 60, and the charging status and timing of the second/part 7G of the red cube. At t=〇94, two voltages are input to each of the scanning lines 88 and 90, and the ridges of each of the thin film transistors are in an enemy state, so that the first portion of the sub-element 62 is infiltrated into the thin film transistor 94. The gate of 96 is transmitted by data line 80 while ί (two = two whistle pressure) to the source of thin film transistors 94, 96 and then P^ ίί 68 and the second part 70 of the halogen electrode at t1 The gray-scale voltage of 3V is received within 16 ms of the sweep. Then turn off the 5-line 88 sub-turn-on scan line 9〇, input a 7-W from the data lines 8〇, 82, 84 at t2 time Φ2 such as 4 · 16~8. The voltage is applied to the source of the thin film transistor 106 and charges the second portion. Since the thin film transistors 94, 96 are turned off at this time, 7 201039033 . , a partial 68 of the halogen electrode receives the gray scale voltage is maintained at 3V and the - - part 70 of the halogen electrode is connected (four) The grayscale voltage is at 5v. * / Qing again with reference to FIG. 4 to FIG. 6. FIG. 4 is a diagram showing a pixel equivalent circuit of four $membrane transistors in a sub-tenon structure according to another embodiment of the present invention, and FIG. 5 is a sub-pixel of FIG. FIG. 6 is a schematic diagram of the actual sub-pixel structure of the present embodiment. As shown in FIG. 5 and FIG. 6, the sub-pixel structure 12 of the present embodiment mainly includes two horizontally disposed scan lines 122 and 124, a vertical interlaced scan, a tributary line 126 of 122 and 124, and a common electrode. The 262 and the four thin film electric solar bodies 128, 130, 132, and 134 are connected to the scanning lines 122 and 124 and the data line 126, respectively. As in the above embodiment, each sub-tenon structure 120 mainly comprises two portions, for example, a first portion 136 including a halogen electrode 256 and a second portion 138 including a substantially V-shaped drain 258. In the present embodiment, the thin film transistor 128 is disposed on the scan line 122 and connected to the pixel electrode 256 of the first portion 136 of the sub-pixel structure 12, and the thin film transistor 13 is disposed on the scan line 122. The pixel electrode 258 is connected to the second portion 138 of the sub-pixel structure 120. The thin film transistor 132 is a germanium electrode 258' film which is disposed on the scan line 124 and connects the second pixel portion 138 of the sub-pixel structure 12 The transistor 134 is a halogen electrode 260 disposed on the scan line 124 and connected to the first portion 14 of the next sub-pixel structure. As shown in the equivalent circuit diagram of FIG. 4, the drain 142 of the thin film transistor 128 is connected to the capacitor 144 of the first portion 136 of the sub-morph structure 120, and the gate 146 is connected to the scan line 122, and the source The pole 148 is connected to the data line. The capacitor 152 'gate 154 of the last ^t 130 150 138 是 is connected to the scan line 122, and the source terminal J 疋 is connected to the > The gate 158 of the thin film transistor 132 is connected to the capacitor 152 of the second portion 138 of the germanium structure 120, the gate 16 is connected to the scan line 124, and the source 162 is connected to the data line 126. The thin film transistor, the poleless I64 is connected to the first part of the next sub-cell structure, the electric f 166, the gate 168 is connected to the scan line 124, and the source 17 is connected to the tributary line 126. . In the present embodiment, the capacitors 144, 152, 166 disposed in the sub-tenon structure 12A may include a storage capacitor and a liquid crystal capacitor, but are not limited thereto. 8 201039033 - ΐΐϊ: 'Λ' is a second embodiment of the invention at a frequency of 12 ° Hz and a timing diagram. As shown in Fig. 6, the thin pixel structure of the present invention = -/:, ·, and the various pixel structures that are not beneficial to the user are mainly composed of three sub-salmon genomic red sub-pixels 182 and a green sub-salmon 184. And an i dice 86. However, it is not limited to this. The structure of each element can also be composed of more than three Js. Each of the sub-categories is further divided into two parts, such as a red sub-section; the prime 182 is divided into a first part 188 and a second part 190, and the green sub-book: 184^ separates the first part 192 and The second part 194, the blue sub-single — - the first part 196 and the second part 198. The pixel structure 80 of this embodiment mainly includes three data lines 2〇〇, 2〇2, 2〇4 and three scanning lines 2〇8, 21〇, 212 which are interlaced by 202 and 204. 'β ❹ ❹ In the present embodiment, six thin film transistors are respectively disposed on the scanning lines 2〇8, 21〇, and 212, respectively corresponding to a part of each sub-halogen. For example, the scan line 208 is free of thin film transistors 216, 218, 220, 222, 2, 4, 226, wherein the thin film electro-crystals 216, 218, 220 are used to control the red color in the upper-halogen structure. The second part of the green and blue sub-pixel structure, while the thin film transistors 222, 224, 226 are used to control the red, green and blue sub-tenon structures 182, 184, 186 of the alizarin structure 18〇 The first part is 188, 192, 1%. The scan lines 210 are provided with thin film transistors 228, 230, 232, 234, 236, 238, wherein the thin film transistors 228, 230, 232 are used to control the red, green and blue sub-pixel structures in the pixel structure 18 182. The first portions 188, 192, 196' of 184, 186 and the thin film transistors 234, 236, 238 are used to control the red, green, and blue sub-pixel structures 182, 184, 186 of the alizarin structure 180. Two parts 190, 194, 198. The scan lines 212 are provided with thin film transistors 240, 242, 244, 246, 248, 250, wherein the thin film transistors 240, 242, 244 are used to control the red, green and blue sub-tenon structures 182 in the halogen structure 180, The second portion 190, 194, 198 of 184, 186, and the thin film transistors 246, 248, 250 are used to control the first portion of the red, green, and blue sub-pixel structures in the next pixel structure. The left side of the halogen structure 180 shows the relationship between the halogen electrode and the received gray scale voltage of 9 201039033 , ,, for example, Ρ 1 is the first part of the red husten 182 188 of the halogen electrode in the t=0 to t2 time period. The gray scale voltage received therein, and ρ2 is the gray scale voltage received by the pixel electrode of the second portion 190 of the red subpixel 182 during the time period from t=〇 to t2. The following is a description of the timing diagram on the right side of the 昼 结构 structure 18 并 and $ to drive a sub-segment, for example, only the charging status and timing of the first part 188 and the second part 19 昼 of the red scorpion 182 Description. When the previous facet before t=o, the gates of the thin film transistors 216, 222 are turned on by the scan line and then a voltage (for example, 5 V voltage) is input from the data line 2 to the thin film transistors 216, 222. The source simultaneously charges the second portion (not shown) of the red quinone in the upper element of the thin film transistor 216 and precharges the first portion 188 of the red sub-pixel 188. The pixel electrode of the first portion 188 of the red sub- 182 is connected to the gray scale voltage of Ϊ, 5 ν in a time period before t=〇. Then, the scan line 208 is turned off and the scan line 210 is turned on, and the -3V voltage is input from the feed line 200 to the source of the thin film transistors 228, 234 and simultaneously to the first portion 188 and the second portion 19 of the red sub-halogen 188. 〇 Conduct ^ electricity. The time period of the first part 188 and the second part 19〇 of the red subunit 182 is t0 to t1, that is, the gray level voltage of w is received. Then, the trace line 210 is turned on and the scan line 212 is turned on, and the source of the 5V electro-optical transistor 24〇, 246 is input from the data line 2〇〇 and the second portion 19〇 and the next X-ray pixel structure are input. The first part (not shown) is charged. Since the electromagnets 228, 236 are closed at this time, the first part 188 =, the gray scale electric waste received during the time period from t1 to t2 is the 190 element maintained at 3V two parts 190. The gray scale voltage received by the electrode is at 5v. Four ί μ The invention mainly sets three or liters of early body at the same time as the sub-pixel priming, so that the sub-structure of the sub-four can be lifted under the driving force of 12 GHz. According to the Μ Φ ί 电 电 ' ' ' ' ' ' ' 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中The transistor is placed on the second scanning line and controls the second part of the alpha structure' to further solve the high update frequency, and each sub-single knot 201039033 Ο is only the present hair; the car; ;;, w and modifications are all within the scope of the present invention. The present invention is a circuit diagram of a halogen equivalent of a three-film transistor in a structure of a sub-small element in the first embodiment of the present invention. 2 is a schematic diagram of a halogen element of the sub-halogen structure of FIG. Figure 3 is a gray scale and timing diagram for driving a Charles at a ρ ΟΗζ frequency according to the first embodiment of the present invention. 4 is a pixel equivalent circuit diagram of a four-film transistor in a structure according to another embodiment of the present invention. 'to', FIG. 5 is a schematic diagram of the pixel structure of the sub-tenk structure in FIG. 6 is a schematic diagram of the actual sub-halogen structure in FIG. 4. 7 is a gray scale and timing diagram for driving a halogen structure according to a second embodiment of the present invention. [Main component symbol description] 1 Π 7 ▲士..... Subpixel structure 12 scan line scan line 16 data line film Transistor 20 Thin Film Transistor 11 201039033 22 Thin Film Transistor 26 Second Part 30 Capacitor 34 Source 38 Capacitor 42 Source 46 Gate 60 Pixel Structure 64 Green Subunit 68 Part 1 72 Part 16 The first part 80 data line 84 data line 90 scan line 96 thin film transistor 100 thin film transistor 104 thin film transistor 108 thin film transistor 120 sub-halogen structure 124 scanning line 128 thin film transistor 132 thin film transistor 136 first part 140 Part 1 144 Capacitor 148 Source 152 Capacitor 156 Source 160 Gate 164 Bungee 168 Gate 180 Cell Structure 184 Green Sub Element 188 Part 1 24 Part 1 28 Pole 32 Gate 36 Bungee 40 Gate 44 Bungee 48 Source 62 Red Subunit 66 Blue Subunit 70 Second Part 74 Second Part 78 Second Part 82 Data Line 88 Scan Line 94 Film Crystal 98 Thin Film Transistor 102 Thin Film Transistor 106 Thin Film Transistor 110 Thin Film Transistor 122 Scan Line 126 Lean Line 130 Thin Film Transistor 134 Thin Film Transistor 138 Second Part 142 Bungee 146 Gate 150 Bungee 154 Gate 158 Infinite 162 Source 166 Capacitor 170 Source 182 Red Subsidiary 186 Blue Subpixel 190 Part 2 12 201039033

192 第一部份 194 第二部份 196 第一部份 198 第二部份 200 資料線 202 資料線 204 資料線 208 掃描線 210 掃描線 212 掃描線 216 溥膜電晶體 218 溥膜電晶體 220 薄膜電晶體 222 薄膜電晶體 224 薄膜電晶體 226 薄膜電晶體 228 薄膜電晶體 230 薄膜電晶體 232 薄膜電晶體 234 薄膜電晶體 236 薄膜電晶體 238 薄膜電晶體 240 薄膜電晶體 242 薄膜電晶體 244 薄膜電晶體 246 薄膜電晶體 248 薄膜電晶體 250 薄膜電晶體 252 晝素電極 254 畫素電極 256 晝素電極 258 畫素電極 260 晝素電極 262 共同電極192 Part 1 194 Part 2 196 Part 1 198 Part 2 200 Data Line 202 Data Line 204 Data Line 208 Scan Line 210 Scan Line 212 Scan Line 216 Diaphragm Transistor 218 Tantalum Transistor 220 Film Transistor 222 Thin film transistor 224 Thin film transistor 226 Thin film transistor 228 Thin film transistor 230 Thin film transistor 232 Thin film transistor 234 Thin film transistor 236 Thin film transistor 238 Thin film transistor 240 Thin film transistor 242 Thin film transistor 244 Thin film transistor 246 thin film transistor 248 thin film transistor 250 thin film transistor 252 halogen electrode 254 pixel electrode 256 halogen electrode 258 pixel electrode 260 halogen electrode 262 common electrode

1313

Claims (1)

201039033 - 七、申請專利範圍: ‘ 1· 一種液晶顯示器之子晝素結構,設於一第一基板盥— ,’該子畫素結構包括-第-部份與-第二“, 素結構另紐: ⑼且该子畫 ο 錯ίί線、一第一掃描線以及一第二掃描線與該資料線交 部$;電晶體設於該第—掃描線並連接該子晝素結構之該第一 體設於該第—掃描線並連接該子畫素結構之該第二 電晶體設於該第二掃描線並連接該子畫素結構之該第二 2. =請專利範圍第2項所述之子畫素結構,其中 3 色子晝素、—綠色子畫素或—藍色子書素籌 3. 如申睛專利範圍第:項所述之子晝素結構,另= 4. 該第-電晶體谷 設於該子畫健構之該帛二少-電容 電晶體。 仍㈣騎弟-電日%體及該第三 ❹ 5. 如申請專利範圍第i項所述之子晝素結 體設於該第二掃描線。 、、 匕括一第四電晶 6·如申請專利細第5項所述之子書辛 是連接-鄰近該子晝素結構之另中该第四電晶體 7. :申J專利範圍第5項所述之子晝;結二 L第二電晶體、第三電晶體及該第四電晶體以 8. ^申請專利範圍第丄項所述之子晝素結構, 括一彩色濾光陣列基板。 一中5亥第一基板包 9·^^利範圍第巧所述之子晝素 括一薄膜電晶體陣列基板。 ’、中該弟二基板包 201039033 -ια如申,〒範圍第1項所述之子畫素結構,另包括至少-畫素 ^ 電極献5好畫素結構之鮮-部份並連接該第-電晶體。 11. 如申凊專,範圍第1項所述之子晝素結構,另包括至少—晝素 電極设於5亥子畫素結構之該第二部份並連接該第二電晶體 第三電晶體。 12. —種驅動液晶顯示面板的方法,包括: 知:供一子晝素結構,該子晝素結構具有第一部份與一第二部 份三一貧料線、一第一掃描線以及一第二掃描線與該資料線交 錯設置, ο 於一第一時間週期由該資料線輸入一第一電壓並對該第一部份 進行充電並同時對該第二部份進行預充電;以及 於一第二時間週期由該資料線輸入一第二電壓並僅對該第二 份進行充電。 13. 如申請專利範圍第12項所述之方法,其中該第一電壓不同於★亥 第二電壓。 、βχ 14. 如申,專利範圍第12項所述之方法,另包括設置一第一電晶體 與一第二電晶體於該第一掃描線並連接該子畫素結構之該第— 部份,以及設置一第三電晶體於該第二掃描線並連接該子金 結構之該第二部份。 ι尔 ❹ 15·如申,專,範圍第14項所述之方法,另包括設置一第四電晶體 於該第二掃巧線並連接另一相鄰子晝素結構之一第一部份。曰 16. 如申請專利範圍第15項所述之方法,其中該第一電晶體、第二 電晶體、第二電晶體及該第四電晶體分別為一薄膜電晶體。 17. —種液晶顯示面板,包括: 一第一基板與一第二基板; 置 至少一子晝素結構設於該第一基板與該第二基板之間,該子書 素結構具有一第一部份與一第二部份,且該子晝素結構另1括^ 一資料線、一第一掃描線以及一第二掃描線與該資料線交錯設 9 第一電晶體設於該第一掃描線並連接該子晝素結構之該第一 15 201039033 部份; 體設於該第—掃描職連接該子晝素結構之該第二 制=電晶體設於郷二掃描線並連接該子晝麵構之該第二 18. 如申請專利範圍第17項所述之液晶顯示面板, 構係為-紅色子晝素、—綠色子晝素或—藍色子書二息素結 19. 如申請專利範圍第17項所述之液晶顯示面板,另'^括 容設於該子晝素結構之該第一部份並連接該第—電 ^ —電 Ο 20. 如申請專利範圍第17項所述之液晶顯示面板,另包二至,丨、 技結構之該第二部份並連接該第二電晶體i該Ϊ 21. 如申明專利範圍第17項所述之液晶顯示 晶體設於該第二掃描線。 礼枯弟四電 利f圍第21項所述之液晶顯示面板,財該第四電晶 體疋連接一鄰近該子晝素結構之另一子畫素結構。 23.如申請,利範圍第21項所述之液晶顯示面板,其中該第一電晶 體、第二電晶體、第三電晶體及該第四電晶體分別為一薄膜g 晶體。 、 〇 24.如申請專利範圍第n項所述之液晶顯示面板 包括一彩色濾光陣列基板。 25. 如申請專利範圍第17項所述之液晶顯示面板,其中該第二基板 包括一薄膜電晶體陣列基板。 26. 如申請專利範圍第17項所述之液晶顯示面板,另包括至少一畫 素電極設於該子晝素結構之該第一部份並連接該第一電晶體。 27. 如申請專利範圍第17項所述之液晶顯示面板,另包括至少一畫 素電極設於該子晝素結構之該第二部份並連接該第二電晶體及 該第三電晶體。 16201039033 - VII. Patent application scope: '1· A sub-structure of a liquid crystal display, which is set on a first substrate ,-, 'the sub-pixel structure includes - part-and-second', (9) and the sub-picture ο ί ίί line, a first scan line and a second scan line and the data line intersection portion; a transistor is disposed on the first scan line and connected to the first of the sub-cell structure The second transistor disposed on the first scan line and connected to the sub-pixel structure is disposed on the second scan line and connected to the second portion of the sub-pixel structure. The sub-pixel structure, in which the 3-color sub-alkaline, the green sub-pixel or the blue sub-book is 3. The sub-formal structure described in the scope of the patent scope: the other = 4. The first-electric The crystal valley is set in the sub-picture of the sub-capacitor-capacitor crystal. Still (4) riding the brother-electric day% body and the third unit 5. As described in the patent scope range i item In the second scanning line, and including a fourth electro-crystal 6 · as described in the fifth item of the patent application, the sub-book is connected-adjacent The fourth transistor 7 is in the vicinity of the sub-halogen structure. The sub-electrode according to item 5 of the patent scope of claim J; the second transistor of the second L, the third transistor and the fourth transistor are 8. ^The patented structure of the sub-division structure described in the scope of the patent application includes a color filter array substrate. The first substrate of the 5th board of the first half of the board contains a thin film transistor array substrate. ', the middle two of the substrate package 201039033 - ια如申, 〒 range of the sub-pixel structure described in item 1, and at least the - pixel ^ electrode provides 5 good pixel structure of the fresh - part and connected to the first - a transistor 11. The sub-halogen structure of the first item of claim 1, wherein at least the halogen element is disposed in the second portion of the 5th sub-pixel structure and is connected to the second transistor A three-crystal transistor. 12. A method for driving a liquid crystal display panel, comprising: knowing: for a sub-halogen structure, the sub-halogen structure has a first portion and a second portion, a lean line, a first a scan line and a second scan line are interleaved with the data line, ο a first time period The feed line inputs a first voltage and charges the first portion and simultaneously precharges the second portion; and inputs a second voltage from the data line for a second time period and only applies to the second 13. The method of claim 12, wherein the method of claim 12, wherein the first voltage is different from the second voltage of the second step, βχ 14. The method of claim 12, further comprising a first transistor and a second transistor are disposed on the first scan line and connected to the first portion of the sub-pixel structure, and a third transistor is disposed on the second scan line and connected to the sub-gold The second part of the structure. The method of claim 14, wherein the method further comprises setting a fourth transistor on the second scan line and connecting another adjacent sub-frame. The first part of the prime structure. The method of claim 15, wherein the first transistor, the second transistor, the second transistor, and the fourth transistor are each a thin film transistor. 17. A liquid crystal display panel, comprising: a first substrate and a second substrate; wherein at least one sub-cell structure is disposed between the first substrate and the second substrate, the sub-book structure has a first a portion and a second portion, and the sub-tenon structure further includes a data line, a first scan line, and a second scan line interleaved with the data line. The first transistor is disposed at the first portion. Scanning the line and connecting the first 15 201039033 portion of the sub-halogen structure; the second system=the transistor disposed in the first-scanning interface connecting the sub-decoron structure is disposed on the second scan line and connecting the sub- The second aspect of the invention is the liquid crystal display panel according to claim 17, wherein the structure is - red scorpion, - green scorpion or - blue subsistence zirconium. The liquid crystal display panel of claim 17 is further disposed in the first portion of the sub-tend structure and connected to the first electrical circuit. 20. As claimed in claim 17 The liquid crystal display panel is further provided with two parts, the second part of the structure and the connection structure The two transistor i Ϊ 21. As stated in item 17 of the liquid crystal display patentable scope crystals disposed on the second scan line. The liquid crystal display panel described in Item 21, wherein the fourth electro-optic crystal is connected to another sub-pixel structure adjacent to the sub-halogen structure. The liquid crystal display panel of claim 21, wherein the first electro-optic body, the second electro-optical crystal, the third electro-optical crystal, and the fourth electro-optical crystal are respectively a film g crystal. 〇 24. The liquid crystal display panel of claim n, wherein the liquid crystal display panel comprises a color filter array substrate. 25. The liquid crystal display panel of claim 17, wherein the second substrate comprises a thin film transistor array substrate. 26. The liquid crystal display panel of claim 17, further comprising at least one pixel electrode disposed on the first portion of the sub-tenon structure and connected to the first transistor. 27. The liquid crystal display panel of claim 17, further comprising at least one pixel electrode disposed on the second portion of the sub-tenon structure and connecting the second transistor and the third transistor. 16
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KR101435527B1 (en) * 2007-07-25 2014-08-29 삼성디스플레이 주식회사 Display device

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TWI547745B (en) * 2014-03-14 2016-09-01 群創光電股份有限公司 Liquid crystal display panel and pixel cell circuit
US9875704B2 (en) 2014-03-14 2018-01-23 Innolux Corporation Liquid crystal display panel and pixel cell circuit solving color shift problem

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