201036327201036327
Hb-2UU8-U05(3-TW 30502twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種信號轉換器，且特別是有關於一 種降低電磁干擾的信號轉換器。 【先前技術】 近年來’由於印刷電路板（printe(j circuit board » PCB)不斷進步，使得電子產品的應用曰益廣泛且需求曰 益增加，各種電子產品的電路設計也越來越複雜。為了符 合高性能及高反應度的要求，數位資料傳輸速度越來越 I"夬’而電晶體對電晶體邏輯(Transist〇r_Transist〇r L〇gie， TTL)信號傳輸的頻率極限僅約為50MHz。因此，倘若TTL 4«號要達到全擺幅(full swing)的上升時間(rising time)過長 時，TTL彳§號將無法應用在高速傳輸的方式。針對此種情 況，TTL信號在傳送的過程中，通常會透過一信號轉換器 轉換成差動小信號的方式去傳送，其中差動小信號所需的 上升時間較短，因此可以滿足高速傳輸的需求。 雖然差動小信號可以減少轉態的時間以達到更快的 操作頻率，但在傳送的過程中往往都會遇到電磁干擾 (Electromagnetic Interference，EMI)的問題。電磁干擾主要 可分為輕射性(Radiated)與傳導性(Conducted)電磁干擾。輕 射性電磁干擾是直接經由開放空間傳遞，不須要經由任何 傳輸介質，故一般僅能以遮蔽(Shielding)、接地(Grounding) 等方式來解決。而傳導性電磁干擾是經由電源導線來傳遞 雜訊。因此，連接在同一個系統的電子裝置所產生的電磁 201036327 “π-J056-TW 305〇2twf.doc/n 干擾會經由電源線而彼此相互干擾，造成在傳輸信號過程 中信號判讀錯誤’使得產品輪出功能不正常或是壽命因此 減短。 【發明内容】 本fx月k供種k號轉換器，可降低信號傳輸時發生 - 的電磁干擾。 _ 本發明提出—難號轉換ϋ，包括第-電流源、第二 〇 冑流源、切換單元、第二切換單元、第—電容單元及 第二電容單元。其中，第一電流源用以提供參考電流。第 一切換單元用以依據差動輪入信號將參考電流導向至第一 ^換單元的第-端或第三端。差動輸出信號可由第一切換 單元的第二端與第三端取出，即由第二端上的輸出信號及 第三端上的輸出信號取出差動輸出信號。第二切換單元用 以依據差動輸入k號而將流經負載的參考電流導向至第二 切換單元的第一端。第二電流源用以匯集參考電流。第一 電谷單元用以依據切換信號來調整第一電容單元所對應的 〇 電容值。第二電容單元用以依據切換信號來調整第二電容 單元所對應的電容值。 — 在本發明之一實施例中，上述之第一電容單元包括多 個第一開關及多個第一電容。其中，此些第一開關的第一 端耦接至第/切換單元的第一端，並分別依據切換信號而 決定其導通狀悲。另外，此些第一電容分別與此些第一開 關一對一對應，其中此些第一電容的第一端各自耦接至對 應之第一開關的第二端，且此些第一電容的第二端耦接至 5 201036327 HS-2008-0056-TW 30502twf.doc/n 接地電壓。 在本發明之一實施例中，上述之第二電容單元包括多 個第二開關及多個第二電容。其中，此些第二開關的第二 端耦接至第二切換單元的第一端，並分別依據切換信號而 決定其導通狀態。另外，此些第二電容分別與此些^二開 辦—對應’其t此些第二電容的第—端各自輕接至^ 二開關的第二端’且此些第二電容的第二端輕接至 按地電壓。 ，本發明之—實施例中，上述之第一電容單元與第二 轻二破參照差動輸人信號的頻率來㈣切換信號，以 相^—電容單元與第二電容單元所對應之€容值的大小 相關於差動輪入信號的頻率。 容單基於2 ’本發明可藉由設定第—電容單元及第二電 、廣]^^的电谷值，來減低開關切換所造成的電磁干擾，並 ::電流源與第二電流源所產生的雜訊。 舉實讓本發明之上述特徵和優點能更明顯易懂，下文特 cr合所附圖式作詳細說明如下。 號轉:差C态’雖可將擺幅(swing)較大的資料信 當信號鏟施π:，以符合高速傳送數位資料的需求。但 此將使ut二作的頻率越快時’電磁干擾也越嚴重，如 有功能不正常，或是壽命因此減短。 以減彳本發明的實施例提供一種信號轉換器，可 低^轉換ϋ在高速操作時難生㈣磁干擾，以避 30502twf.doc/n 201036327Hb-2UU8-U05 (3-TW 30502twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a signal converter, and more particularly to a signal converter for reducing electromagnetic interference. [Prior Art] In recent years, due to the continuous advancement of printed circuit boards (PCBs), the application of electronic products has been widely used and the demand has increased. The circuit design of various electronic products has become more and more complicated. In line with the requirements of high performance and high responsiveness, the digital data transmission speed is more and more I"夬' and the frequency limit of the transistor to Transist〇r_Transist〇r L〇gie, TTL signal transmission is only about 50MHz. Therefore, if the TTL 4« number is too long to reach the full swing, the TTL 彳§ number will not be applied to the high-speed transmission mode. For this case, the TTL signal is transmitted. In the process, it is usually transmitted by means of a signal converter to convert into a small differential signal, wherein the differential small signal requires a shorter rise time, so that it can satisfy high-speed transmission. Although the differential small signal can reduce the transition time to achieve a faster operating frequency, it often encounters electromagnetic interference (EMI) during the transmission process. Electromagnetic interference can be mainly divided into light shots. Radiated and Conducted electromagnetic interference. Light-emitting electromagnetic interference is transmitted directly through open space, without any transmission medium, so it can only be solved by Shielding, Grounding, etc. Conductive electromagnetic interference is transmitted through the power supply wires. Therefore, the electromagnetics generated by the electronic devices connected to the same system 201036327 "π-J056-TW 305〇2twf.doc/n interference will pass each other via the power line Mutual interference, causing signal interpretation errors during the transmission of signals, so that the product rotation function is abnormal or the life is shortened. [Invention content] This fx month k is for the k-type converter, which can reduce the occurrence of signal transmission - Electromagnetic interference. _ The present invention proposes a difficult-to-signal conversion, including a first current source, a second current source, a switching unit, and a second switching list. a first capacitor unit and a second capacitor unit, wherein the first current source is configured to provide a reference current. The first switching unit is configured to direct the reference current to the first end or the first unit of the first switching unit according to the differential wheeling signal. The differential output signal can be taken out by the second end and the third end of the first switching unit, that is, the differential output signal is taken out by the output signal on the second end and the output signal on the third end. The reference current flowing through the load is directed to the first end of the second switching unit in accordance with the differential input k number. A second current source is used to sink the reference current. The first valley unit is configured to adjust a value of the tantalum capacitor corresponding to the first capacitor unit according to the switching signal. The second capacitor unit is configured to adjust a capacitance value corresponding to the second capacitor unit according to the switching signal. In one embodiment of the invention, the first capacitor unit includes a plurality of first switches and a plurality of first capacitors. The first end of the first switch is coupled to the first end of the/switching unit, and determines its conduction state according to the switching signal. In addition, the first capacitors are respectively corresponding to the first switches, wherein the first ends of the first capacitors are respectively coupled to the second ends of the corresponding first switches, and the first capacitors are The second end is coupled to 5 201036327 HS-2008-0056-TW 30502twf.doc/n Ground voltage. In an embodiment of the invention, the second capacitor unit includes a plurality of second switches and a plurality of second capacitors. The second end of the second switch is coupled to the first end of the second switching unit, and determines the conduction state thereof according to the switching signal. In addition, the second capacitors respectively correspond to the second terminals of the second capacitors, and the second ends of the second capacitors are connected to the second ends of the second capacitors Lightly connect to ground voltage. In the embodiment of the present invention, the first capacitor unit and the second light-breaking reference frequency of the differential input signal (4) switch signals, and the corresponding capacitors of the capacitor unit and the second capacitor unit The magnitude of the value is related to the frequency of the differential wheeling signal. The capacity is based on 2'. The invention can reduce the electromagnetic interference caused by switching by setting the electric capacitance of the first capacitor unit and the second electric, wide, and ^^, and: the current source and the second current source The noise generated. The above features and advantages of the present invention will become more apparent from the following description. The number of turns: the difference C state can be used to slash the signal with a large swing signal to meet the demand for high-speed transmission of digital data. However, this will make the frequency of ut II faster. The electromagnetic interference will be more serious, if the function is not normal, or the life is shortened. In order to reduce the 彳 embodiment of the present invention, a signal converter can be provided, which can be low-converted and difficult to generate (4) magnetic interference during high-speed operation, so as to avoid 30502twf.doc/n 201036327
jrti>-zuu6-i;056-TW 免在傳輸信號過程中信號判讀錯誤，使得產品輸出功能不 正常。下面將參考附圖詳細闡述本發明的實施例，附圖舉 例況明了本發明的示範實關，其巾蝴標號 相似的元件。 aJrti>-zuu6-i;056-TW avoids signal interpretation errors during signal transmission, making the product output function abnormal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which FIG. a
O "圖1是依照本發明-實施例之信號轉換器的電路圖。 請=照圖1 ’本實施例所提供的信號轉換器1〇〇主要包括 -第-電流源A卜-第二電流源A2、—第—切換單元 102——第二切換單元104、一第—電容單元刚以及-第 =電容單元觀。其中，圖丨更綠示出信號轉換器1〇〇在 貫際應用上所外接的負載110。在此，負載11〇例如是作 =器1〇〇的下級電路(例如信號接收器)或是信號傳輸 通道(例如印刷電路板)··.等。為了說明方便起見，圖！更冷 不出負載110的等效電路，且此等效電路包 ^ 容CP1及電容CP2。 玉 第一電流源A1耦接電源電壓vs。第一切換單元1〇2 =第-端TM21至第三端TM23。第—切換單元1〇2的 TM21耦接至第一電流源、M。第一切換單元搬 端TM22與第三端TM23分別外接至負載11〇的兩 ^ — 一切/矣單凡104具有第一端TM41至第三端TM43。 ^二^換單元1G4的第二端施2與第三端遞3分別麵 Ϊ至第一切換單元102的第二端ΤΜ22與第三端ΤΜ23。 流源Α2输在第二切換單元刚的第一端m4i 與接地電壓GND > 。Η k 卜卜 ^ 嚷一 m 一 之間另外，弟一電容單元106耦接在 切換單元1〇2的第一端TM21與接地電壓之間。 201036327 n^-^uud-uu^o-TW 30502twf.d〇c/n 第二電容單元108與第二電流源A2相互並聯。 其中’第一電流源A1用以提供一參考電流η。第— 切換單元102用以依據一差動輸入信號D1將參考電流η 導向至其第二端ΤΜ22或第三端ΤΜ23。另一方面，第二 切換單元104會依據差動輸入信號Di而將流經負載11〇 的參考電流II導向至第二切換單元104的第—端TM41。 第二電流源A2則用以匯集參考電流Π。 如此一來’隨著第一切換單元102與第二切換單元1〇4 對參考電流II之流向的切換，參考電流II將流經負載 並在負載110的兩端形成一差動輸出信號D2,也就是壓降 在第一切換單元102之第二端TM22上的輪出信號D21以 及其第三端TM23上的輸出信號D22。在此，差動輪出信 號D2的振幅小於差動輸入信號D1的振幅，故經由信號轉 換器100轉換的差動輸入信號D1，將滿足高速傳輪的需 求。 另一方面’第一電容單元106用以依據切換信號S1 來5周整弟一電容單元1〇6所對應的電容值。第二電容單元 用以依據切換信號S1來調整第二電容單元1〇8所對應 的電容值。其中，第一電容單元106與第二電容單元1〇^ 更參照差動輸入信號D1的頻率來控制切換信號S1，使第 一電容單元106與第二電容單元108所對應之電容值的大 小相關於差動輸入信號D1的頻率。藉此，第一電容單元 與第二電容單元1〇8將可有效地濾除，第一切換單元 102與第二切換單元104在切換參考電流II之瞬間所形成 201036327 η^υυο-0056-TW 30502fwf.doc/n 的突波。 在本發明的另-實施例中，圖！中的差動輸入信號 出包括兩個互不重疊的輸人信號，而第—切換單元1〇2 與第一切換單元1〇4各可包括兩個開關。舉例來說，圖2 是依照本發明另一實施例之信號轉換器的電路圖，圖3是 ‘=照本發明—實施例之差動輸人錢與差動輪出信號的示 . —。請參，圖2與圖3，本實施例中的差動輪人信號m ❹ &括互不重*的第—輸人信號D11與第二輸人信號D12。 信號在高準位時為致能，在低準位時為失能。因此， Ϊ第Γ^入信號D11為致能之期間第二輸入信號D12為失 能，當第二輸入信號D12為致能之期間第一輸入信號Dn 為失能，且兩輸入信號不同時為致能。 —另外，第一切換單元102包括一第一開關SW1以及 :第二開關SW2。其中’第一開關SW1之第一端耦接至 第一切換單元102的第一端TM21，第一開關SW1的第二 端耦接至第一切換單元102的第二端TM22。第二開關SW2 的第一端耦接至第一切換單元1〇2的第一端TM21，第二 開關SW2的第二端耦接至第一切換單元1〇2的第三端 TM23 〇 第二切換單元104則包括一第三開關SW3以及一第 四開關SW4。其中’第三開關SW3的第一端耦接至第二 切換單元1〇4的第二端TM42，第三開關SW3的第二端耦 接至第二切換單元1〇4的第一端TM4卜第四開關SW4的 第—端耦接至第二切換單元1〇4的第三端TM43，第四開 9 201036327O " Figure 1 is a circuit diagram of a signal converter in accordance with an embodiment of the present invention. Please refer to FIG. 1 'The signal converter 1 本 provided in this embodiment mainly includes a -first current source A - a second current source A2 - a - switching unit 102 - a second switching unit 104, a first - Capacitor unit just as - - = capacitor unit view. Among them, the greener of the figure shows the load 110 externally connected to the signal converter 1 . Here, the load 11 is, for example, a lower stage circuit (e.g., a signal receiver) or a signal transmission channel (e.g., a printed circuit board). For the sake of convenience, figure! It is cooler than the equivalent circuit of load 110, and this equivalent circuit packs CP1 and capacitor CP2. The first current source A1 is coupled to the power supply voltage vs. The first switching unit 1〇2 = the first end TM21 to the third end TM23. The TM21 of the first switching unit 1〇2 is coupled to the first current source, M. The first switching unit terminal TM22 and the third terminal TM23 are externally connected to the load 11A, respectively, and the first terminal TM41 to the third terminal TM43. The second end 2 and the third end 3 of the unit 1G4 are respectively connected to the second end 22 and the third end 23 of the first switching unit 102. The source Α2 is outputted at the first end m4i of the second switching unit and the ground voltage GND >. In addition, the capacitor-cell 106 is coupled between the first terminal TM21 of the switching unit 1〇2 and the ground voltage. 201036327 n^-^uud-uu^o-TW 30502twf.d〇c/n The second capacitor unit 108 and the second current source A2 are connected in parallel with each other. Wherein the first current source A1 is used to provide a reference current η. The first switching unit 102 is configured to direct the reference current η to its second end 22 or the third end 23 according to a differential input signal D1. On the other hand, the second switching unit 104 directs the reference current II flowing through the load 11A to the first terminal TM41 of the second switching unit 104 in accordance with the differential input signal Di. The second current source A2 is used to collect the reference current Π. As a result, with the switching of the first switching unit 102 and the second switching unit 1〇4 to the flow of the reference current II, the reference current II will flow through the load and form a differential output signal D2 at both ends of the load 110, That is, the wheel-out signal D21 at the second end TM22 of the first switching unit 102 and the output signal D22 at the third terminal TM23 thereof. Here, since the amplitude of the differential wheeling signal D2 is smaller than the amplitude of the differential input signal D1, the differential input signal D1 converted via the signal converter 100 will satisfy the demand of the high speed carrier. On the other hand, the first capacitor unit 106 is configured to replace the capacitance value corresponding to the capacitor unit 1〇6 by the switching signal S1 for 5 weeks. The second capacitor unit is configured to adjust the capacitance value corresponding to the second capacitor unit 1 〇 8 according to the switching signal S1. The first capacitor unit 106 and the second capacitor unit 1 further control the switching signal S1 with reference to the frequency of the differential input signal D1, so that the first capacitor unit 106 and the second capacitor unit 108 correspond to the magnitude of the capacitance value. The frequency of the differential input signal D1. Thereby, the first capacitor unit and the second capacitor unit 1〇8 can be effectively filtered out, and the first switching unit 102 and the second switching unit 104 form 201036327 η^υυο-0056-TW at the moment of switching the reference current II. 30502fwf.doc/n's glitch. In another embodiment of the invention, the figure! The differential input signal in the middle includes two input signals that do not overlap each other, and the first switching unit 1〇2 and the first switching unit 1〇4 each include two switches. For example, FIG. 2 is a circuit diagram of a signal converter in accordance with another embodiment of the present invention, and FIG. 3 is a representation of a differential input and a differential wheeled signal according to the present invention. Referring to FIG. 2 and FIG. 3, the differential wheel human signal m ❹ & in this embodiment includes a first input signal D11 and a second input signal D12 which are not heavy*. The signal is enabled at high levels and disabled at low levels. Therefore, the second input signal D12 is disabled during the enable period of the signal D11, and the first input signal Dn is disabled during the period when the second input signal D12 is enabled, and the two input signals are different. Enable. In addition, the first switching unit 102 includes a first switch SW1 and a second switch SW2. The first end of the first switch SW1 is coupled to the first end TM21 of the first switching unit 102, and the second end of the first switch SW1 is coupled to the second end TM22 of the first switching unit 102. The first end of the second switch SW2 is coupled to the first end TM21 of the first switching unit 1〇2, and the second end of the second switch SW2 is coupled to the third end TM23 of the first switching unit 1〇2. The switching unit 104 includes a third switch SW3 and a fourth switch SW4. The first end of the third switch SW3 is coupled to the second end TM42 of the second switching unit 1〇4, and the second end of the third switch SW3 is coupled to the first end TM4 of the second switching unit 1〇4 The first end of the fourth switch SW4 is coupled to the third end TM43 of the second switching unit 1〇4, and the fourth opening is 9 201036327
JtLS-/uu5-uudo-TW 30502twf.doc/n 關SW4的第二端耦接至第二切換單元1〇4的第—端 TM41。此外，第一開關S W1至第四開關S W4可以分別由 一個至多個電晶體所構成。 針對第-切換單S 102與第二切換單元刚的細部摔 作來看。其中，第一開關SW1與第四開關sw4依據第一 輸入信號D11來切換其本身的導通狀態，而第二開關撕 與第三開關SW3依據第二輸入信號D12來切換其本 導通狀態。 在此，當第一輸入信號D11為致能之期間 --------〜弟一開關 SW1及第四關SW4為導通，而第二開關SW2及第三開 關SW3為斷開。因此，第一電流源A1所提供的來考電泣 η將由導通的第-開關SW1的第—端流人，並流經^ no而由導通的第四開關SW4的第二端流出，進而被第二 電流源A2所匯集。此時，依據參考電流II的流向可知了 ^浦單元102的第二端TM22將可產生具有高準位的 =k號D2卜且第-切換單元撤的第三端ΤΜ23將可 產生具有低準位的輸出信號D22。 對地H輸人信號⑽為致能之_，第二開 i W2及第三開關SW3為導通，而第一開關撕 ，關綱為斷開。因此，第—電流源供的表= ^ Π將由導通的第二開關SW2的第—端流入，、二一“ :二=導通的第三開關SW3的第二端流出，：= 電心原A2所匯集。此時，依據參考電流π的流 弟一切換單元1〇2的第二端观22將可產生具有低準=的 10 201036327 χ A*-*-i-w〇-v〇56-XW 30502twf.doc/n 輸出js號D21，且第一切換單元1〇2的第三端TM23將可 產生具有高準位的輸出信號D22。JtLS-/uu5-uudo-TW 30502twf.doc/n The second end of the switch SW4 is coupled to the first end TM41 of the second switching unit 1〇4. Further, the first to fourth switches S W1 to S W4 may be constituted by one to a plurality of transistors, respectively. It is seen in the detail of the first-switching single S 102 and the second switching unit. The first switch SW1 and the fourth switch sw4 switch their own on-state according to the first input signal D11, and the second switch-off and the third switch SW3 switch their on-state according to the second input signal D12. Here, when the first input signal D11 is enabled, the second switch SW1 and the fourth switch SW4 are turned on, and the second switch SW2 and the third switch SW3 are turned off. Therefore, the reference current provided by the first current source A1 will flow from the first end of the turned-on first switch SW1, and will flow through the second end of the turned-on fourth switch SW4, thereby being The second current source A2 is assembled. At this time, according to the flow direction of the reference current II, it can be known that the second end TM22 of the pump unit 102 can generate the =k number D2 with a high level and the third end ΤΜ23 of the first switching unit can be produced with a low level. Bit output signal D22. The ground H input signal (10) is enabled, the second open i W2 and the third switch SW3 are turned on, and the first switch is torn and the off is off. Therefore, the table supplied by the first current source = ^ Π will flow in from the first end of the second switch SW2 that is turned on, and the second end of the second switch SW3 that is turned on, "2" = : = = = = At this time, the second end view 22 of the switching unit 1〇2 according to the reference current π will generate 10 201036327 具有 A*-*-iw〇-v〇56-XW 30502twf with low accuracy= .doc/n outputs the js number D21, and the third terminal TM23 of the first switching unit 1〇2 will generate an output signal D22 having a high level.
值得注思疋，隨著第一開關SW1至第四開關SW4的 ^換’ 經負載110之參考電流n的流向也將不斷地反覆 交替。藉此，負載11G的兩端將可形成互不重疊的輸出信 號D21及輸出信號D22’也就是差動輸出信號D2。其中， 差動輸出㈣D2的振幅即為參考電流n之電流值與負載 no之電阻值的乘積，也就是輪出信號D21與輸出信號D22 之間的電壓差。此外，如圖3所示，差動輸出信號D2的 ，幅L2小於差動輸入信號m的振幅L1，且在第一電容 早兀106及第二電容單元1〇8的作用下，差動輸出信號d2 受電磁:擾而產生的突波將可有效地被渡除。 值付-提的是’當第—開關SW1至第四開關頌的 切換頻率越快時，第-開關s w i之第二端上的電壓，以及 第二開關SW2之第二端上的電壓，其瞬間變化所造成的電 壓突波情形也就祕重。為了減低電磁㈣，本實施例可 藉由調整第—電容單元⑽與第二電容單元⑽所等效的 電容值’錢除開_換時電壓上衝及下衝所造成的電壓 突波，並同時濾除第-電流源A1與第二電流源Μ所產生 66雜却〇 、、f此第—電容單疋106與第二電容單元108可用來 阻隔直流、存儲和敎電荷歧和輸出信號 、pi法的電麗突波。當第—開關SW1至第四開關SW4 以較面率切換時，第—電容單元1%與第二電容單元108 11 201036327It is worth noting that the flow of the reference current n through the load 110 of the first switch SW1 to the fourth switch SW4 will also alternately alternately. Thereby, both ends of the load 11G can form an output signal D21 and an output signal D22' which are mutually non-overlapping, that is, the differential output signal D2. The amplitude of the differential output (4) D2 is the product of the current value of the reference current n and the resistance value of the load no, that is, the voltage difference between the rounded signal D21 and the output signal D22. In addition, as shown in FIG. 3, the amplitude L2 of the differential output signal D2 is smaller than the amplitude L1 of the differential input signal m, and the differential output is under the action of the first capacitor 兀106 and the second capacitor unit 〇8. Signal d2 is electromagnetically: the surge generated by the disturbance will be effectively removed. The value is - when the switching frequency of the first switch SW1 to the fourth switch 越 is faster, the voltage on the second end of the first switch swi, and the voltage on the second end of the second switch SW2, The voltage surge caused by instantaneous changes is also a secret. In order to reduce the electromagnetic (4), in this embodiment, the voltage surge caused by the voltage value of the voltage-capacitor and the undershoot of the voltage-capacitor is removed by adjusting the capacitance value equivalent to the capacitance of the first capacitor unit (10) and the second capacitor unit (10), and simultaneously Filtering the first current source A1 and the second current source 产生 generates 66 miscellaneous 、, f, the first capacitor unit 106 and the second capacitor unit 108 can be used to block DC, storage and 敎 charge and output signals, pi The law of the electric rush. When the first to fourth switches SW1 to SW4 are switched at a relatively low rate, the first capacitor unit 1% and the second capacitor unit 108 11 201036327
Hb-zuus-uuDO-TW 30502twf.doc/n 的充放電次數增多且放電電流增強，此時將第一電容 106與第二電容單幻〇8㈣應的電容值必須調小以= 合瞬間放出大電流的需求。相對地，當第—開關_ 四開關S W4以較低頻率切換時，電容的充放電次數減少且 放電電流減弱，此時將第—電容單元1〇6與第二電容ηα _ 108所對躺電容值必須歌，遞合差動輸人信號早= 的頻率充放電，進而獲得穩定的輸出信號D21 &D22。 其中，第一電容單元1〇6與第二電容單元1〇8可 相互並聯的多個電容’並可藉由調整電容的並聯個數來抑 制兩電容單元所對應的電容值的大小。舉例來說，圖4 Γ 依照本發明-實施例之第—電容單元的電路圖。請同時= 照圖2及圖4’第—電容單元⑽可包括多個第五開關 SW51〜SW5N及多個第—電容C11〜C1N，其中N為正整數。 在此，多個第五開關SW51〜SW5N的第一端耦接至第 一切換單元102的第一端TM21，多個第一電容cil〜C1N 分別與多個第五開關SW5iwSWSN 一對一對應’其中多個 第一電容C11〜C1N的第一端各自耦接至對應的第五開 關，且多個第—電容cn〜C1N的第二端耦接至接地電壓 GND三另外’切換信號S1可包括切換信號S11〜S1N。 第一電容單元106可依據差動輸入信號m的頻率來 控制=換信號S11〜S1N。當第一開關SW1至第四開關SW4 以車乂同頻率切換時，第一電容單元106將依據切換信號 =1〜S1N改變第五開關SW51〜SW5N的導通個數，以減少 第一電各單元106中電容並聯的個數，進而調整出適當的 12 201036327 ηδ-ζυυδ-υ056-Τψ 30502twf.doc/n 第二電容單元106的電容值。相對地，當第一開關SW1 至第四開1 SW4卩較低頻率切換時，第五開關 SWM〜SWSN的導通個數將在切換錢川〜則的控制下 文夕’以增加第-電容單元1()6中電容並聯_數，進而 調整出適當的第一電容單元1〇6的電容值。Hb-zuus-uuDO-TW 30502twf.doc/n increases the number of charge and discharge times and increases the discharge current. At this time, the capacitance of the first capacitor 106 and the second capacitor singularly 〇8 (4) must be adjusted to be small to = large instantaneous output Current demand. In contrast, when the first switch _ four switch S W4 is switched at a lower frequency, the number of charge and discharge cycles of the capacitor is reduced and the discharge current is weakened. At this time, the first capacitor unit 1 〇 6 and the second capacitor η α _ 108 are lie on each other. The capacitance value must be sing, and the differential input signal is charged and discharged as early as the frequency, thereby obtaining a stable output signal D21 & D22. The first capacitor unit 1〇6 and the second capacitor unit 1〇8 can be connected to each other in parallel with each other and can adjust the capacitance value corresponding to the two capacitor units by adjusting the parallel number of capacitors. For example, FIG. 4 is a circuit diagram of a capacitor unit in accordance with the present invention. Please also = FIG. 2 and FIG. 4' The first capacitor unit (10) may include a plurality of fifth switches SW51 to SW5N and a plurality of first capacitors C11 to C1N, where N is a positive integer. Here, the first ends of the plurality of fifth switches SW51 SWSW5N are coupled to the first end TM21 of the first switching unit 102, and the plurality of first capacitors cil1 to C1N are respectively corresponding to the plurality of fifth switches SW5iwSWSN. The first ends of the plurality of first capacitors C11 to C1N are respectively coupled to the corresponding fifth switch, and the second ends of the plurality of first capacitors cn to C1N are coupled to the ground voltage GND 3. The other 'switching signal S1 may include The signals S11 to S1N are switched. The first capacitor unit 106 can control the = signal S11 to S1N according to the frequency of the differential input signal m. When the first switch SW1 to the fourth switch SW4 are switched at the same frequency, the first capacitor unit 106 changes the number of conduction of the fifth switches SW51 SWSW5N according to the switching signal=1~S1N to reduce the first electrical unit. The number of capacitors in parallel in 106 is adjusted to the appropriate 12 201036327 ηδ-ζυυδ-υ056-Τψ 30502twf.doc/n capacitance value of the second capacitor unit 106. In contrast, when the first switch SW1 to the fourth switch 1 SW4 卩 switch at a lower frequency, the number of turns of the fifth switch SWM SWSWSN will be switched on the control eve of the control of the chuan ～ to increase the first capacitor unit 1 The capacitance in (6) is connected in parallel to the number, and the capacitance value of the appropriate first capacitor unit 1〇6 is adjusted.
-同理類推，圖5是依照本發明一實施例之第二電 兀的電路®。請同時參關2及圖5，第—電容單元1〇8 可包括多個第六開W SW61〜SW6N &多個第二電容 C21〜C2N。其中，多個第六開關SW61〜sw6n的第一端耦 接至第二切換單^ 1G4的第—端TM4i，多個第二電容 C21〜C2N分別與多個第六開關SW6i〜sw6n 一對—對 應’其中多個第二電容C21〜C2N的第一端各自搞接至對 應的第六開關’ ^多個第二電容C21〜㈣的第二端 至接地電壓GND。 相似地帛一電谷單元1〇8可依據差動輸入信號出 的頻率來控制切換信號S11〜S1N。當第—開關簡至第 四開關SW4以較高頻率切換時，第六開關SW61〜SW6N 的導將在切換信號sn〜則的控制下變少，以減少 第-電容單元108中電容並聯的健，進整 第:電容單元刚的電容值。相對地，當第一開關= 至第四開_ SW4卩較低頻率切換時，第六開關 SW61〜SW6N的導通個數將在切換錢su〜sm的控制下 k:多，以增加第二電容單元1〇8中電容並聯的個數，進而 調整出適當的弟二電容單元的電容值。 13 201036327 hs-zuus-uudo-TW 30502twf.doc/n 綜上所述，上述諸實施例可配合信號轉換器的開關切 換頻率設定第一電容單元及第二電容單元的電容值，以減 低開關切換所造成的電磁干擾，並慮除第一電流源與第二 電流源所產生的雜訊，進而避免在傳輸信號過程中信號判 項的錯誤、產品輸出功能的不正常或是壽命的縮減。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内’當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是依照本發明一實施例說明信號轉換器的電路 圖。 圖2是依照本發明另一實施例說明信號轉換器的電路 圖。 圖3是依照本發明一實施例之差動輸入信號與差動輪 出仏號的示意圖。 圖4是依照本發明一實施例說明第一電容單元的電路 圖。 圖5是依照本發明一實施例說明第二電容單元的電路 圖。 【主要元件符號說明】 10〇、200 :信號轉換器 102 :第一切換單元 1()4 :第二切換單元 14 201036327 Γυ-ζ·\^\·/〇-υ056-ΊΓ\ν 30502twf.doc/n 106 :第一電容單元 108 :第二電容單元 110 :負載 A1 :第一電流源 A2 :第二電流源 CPI、CP2、C11 〜C1N、C21 〜C2N :電容 R0 :電阻 • TM21-TM23 :第一切換單元的端點 V TM41〜TM43 :第二切換單元的端點 VS :電源電壓 GND :接地電壓 11 ·參考電流 D1 :差動輸入信號 D11 :第一輸入信號 D12 :第二輸入信號 D2 :差動輸出信號 〇 D21、D22:輸出信號 • SI、S11〜S1N :切換信號 - SW1 〜SW4、SW51 〜SW5N、SW61 〜SW6N :開關 U、L2 :振幅 15- Similarly, Fig. 5 is a circuit ® of a second electrode in accordance with an embodiment of the present invention. Please refer to both FIG. 2 and FIG. 5. The first capacitor unit 1〇8 may include a plurality of sixth openings W SW61 SWSW6N and a plurality of second capacitors C21 to C2N. The first ends of the plurality of sixth switches SW61 to sw6n are coupled to the first end TM4i of the second switching unit 1G4, and the plurality of second capacitors C21 to C2N are respectively paired with the plurality of sixth switches SW6i to sw6n. Corresponding to the first end of the plurality of second capacitors C21 to C2N being respectively connected to the corresponding sixth switch 'the second ends of the plurality of second capacitors C21 to (4) to the ground voltage GND. Similarly, the first valley unit 1〇8 can control the switching signals S11 to S1N according to the frequency of the differential input signal. When the first switch to the fourth switch SW4 are switched at a higher frequency, the conductance of the sixth switch SW61 to SW6N will be reduced under the control of the switching signal sn~ to reduce the capacitance parallel connection in the first capacitor unit 108. , the whole: the capacitance value of the capacitor unit. In contrast, when the first switch = the fourth switch _ SW4 卩 lower frequency switching, the number of conduction of the sixth switch SW61 ~ SW6N will be more than k: under the control of switching money su ~ sm, to increase the second capacitance The number of capacitors connected in unit 1〇8 is paralleled, and then the capacitance value of the appropriate second capacitor unit is adjusted. 13 201036327 hs-zuus-uudo-TW 30502twf.doc/n In summary, the above embodiments can set the capacitance values of the first capacitor unit and the second capacitor unit in accordance with the switching frequency of the signal converter to reduce switching. The electromagnetic interference caused, and the noise generated by the first current source and the second current source are taken into consideration, thereby avoiding the error of the signal judgment, the abnormality of the product output function or the reduction of the life in the process of transmitting the signal. The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art can make a few changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a signal converter in accordance with an embodiment of the present invention. Fig. 2 is a circuit diagram showing a signal converter in accordance with another embodiment of the present invention. 3 is a schematic diagram of a differential input signal and a differential wheel spurt according to an embodiment of the invention. 4 is a circuit diagram showing a first capacitor unit in accordance with an embodiment of the present invention. Figure 5 is a circuit diagram showing a second capacitor unit in accordance with an embodiment of the present invention. [Description of main component symbols] 10〇, 200: Signal converter 102: First switching unit 1 () 4: Second switching unit 14 201036327 Γυ-ζ·\^\·/〇-υ056-ΊΓ\ν 30502twf.doc /n 106: first capacitor unit 108: second capacitor unit 110: load A1: first current source A2: second current source CPI, CP2, C11 to C1N, C21 to C2N: capacitor R0: resistor • TM21-TM23: End point V TM41 to TM43 of the first switching unit: End point VS of the second switching unit: power supply voltage GND : ground voltage 11 · reference current D1 : differential input signal D11 : first input signal D12 : second input signal D2 : Differential output signal 〇D21, D22: Output signal • SI, S11~S1N: Switching signal - SW1 to SW4, SW51 to SW5N, SW61 to SW6N: Switch U, L2: Amplitude 15