201033963 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a display, a display, and more particularly to a display driven by a multi-timing technique. [Prior Art] In a general display, it usually includes,
Driver and timing controller, ^ early start. Bude, the drive consists of a column of sluice gates: When the source driver turns the driving voltage, the β-send signal is generated by the gate driver to drive the corresponding gate. The polar line and the corresponding (4): the second subtraction causes the gate drive signal to be distorted when it is transmitted to the gate and the slave terminal, and thus the display cannot operate properly. Fig. 1 is a timing chart showing the general start pulse signal and the gate drive signal at the time of transmission. As shown in Fig. 1, when the transfer signal ΤΡ1 is generated, the idle drive signal Gout-1 is generated according to the transfer signal ΤΡ1 to be transmitted to a corresponding gate line (eg, the first gate line), and the gate The drive signal Gout-1 is attenuated according to the voltage drop (IR drop) of the gate line. Specifically, when the gate drive signal Gout_1 is initially generated to drive the idle line, the gate drive signal Gout-丨 has a square wave of the start state (i.e., Gout_1-start). Next, when the gate drive signal G〇ut_i transmits a certain distance, the gate drive signal Gout_l is severely attenuated by the voltage drop, and the distortion of the 201033963 is a distortion waveform (ie, Gout_l_end). When the next transfer signal is generated, the distorted gate drive signal Gout_l__end cannot end immediately (as indicated by symbol A), so that the gate drive signal Gout_l_end at the end of the first gate line will be compared with the second The gate driving signals Gout_2_start of the polar lines are partially overlapped, so that the display quality of the image is greatly affected. [Summary of the Invention] . <
It is an object of the present invention to provide a display and a method of driving the same to improve the display quality of an image. One aspect of the present invention relates to a display comprising a side panel, a gate driver and a plurality of source drivers. The panel contains a number of pixels configured in an array. A gate driver is used to selectively drive one of the gate lines in the panel. The source driver is configured to receive a plurality of transfer signals during a scan period, each of the transfer signals corresponding to one of the source drivers, and the source driver is driven when the source driver is triggered by the corresponding transfer signal One of the elements corresponding to the gate line is a halogen element, wherein the above-mentioned transfer signals are not completely identical. A technical aspect of the present invention relates to a method of driving a display, comprising receiving a plurality of #delivery i during a -sweep & period, and the signals respectively correspond to a source driver, wherein the above-mentioned transfer signal is completed 4 The same, and when receiving the corresponding transfer signal, drive by the corresponding driver (4). According to the technical content of the present invention, the display and the driving method thereof are applied to prevent the gate driving signal from being transmitted to the end of the gate line, thereby affecting the gate driving signal of the next 201033963 gate line, thereby improving the image display quality. [Embodiment] FIG. 2 is a view showing a display according to an embodiment of the present invention. The display 200 includes a panel 210, a timing controller 212, source drivers SD1 and SD2, and a gate driver GD. Panel 210 contains pixels arranged in an array. The timing controller 212 is coupled to the source drivers SD1 and SD2 and respectively transmits transfer pulses TP_SD 1 ❿ and TP_SD2 having different phases to the source drivers SD1 and SD2. In another embodiment, the timing controller 212 is coupled to the source drivers sdi and SD2 via control lines, respectively, and transmits the transfer signals Tp_SD1 and TP_SD2 to the source drivers SD1 and SD2, respectively, via the control lines. Further, the books on the same column are connected to one of the gate lines controlled by the gate driver GD, and are driven by the source drivers SD1 and SD2. Between one scan period (1), the gate driver GD selectively drives one of the gate lines' and the source drivers SD1 and SD2 output a driving voltage to the gate according to the transfer signals Tp sm and TP TP-SD2. The pixel corresponding to the line: In addition, in the present embodiment, the 'transfer signals TP_SD1 and TP-SD2 have different timings with each other in one scan period, so that the source driver is after the source SD1 outputs the driving voltage. SD2 is the output driver. FIG. 3 is a timing diagram showing a transfer signal and a closed-pole drive signal according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, in the first sweeping period m, the transfer signal TP1_sm is first generated for the source driver SD1 to output the driving voltage, and the corresponding gate line (eg, the first gate) Line) 201033963 is driven by the gate drive signal Gout_l, and the source driver SD1 is triggered by the transfer signal TPi_sm to drive the pixels corresponding to the first gate line. Immediately thereafter, a transfer signal TP1_SD2 which is behind the start pulse signal TP1_SD1 is generated so that the source driver SD2 outputs a drive voltage to drive the pixel corresponding to the first gate line. When the front end element corresponding to the front end portion of the first gate line and driven by the first source driver SD1 receives the gate driving signal of the pulse waveform as indicated by Gout_l_start, the end of the first gate line is corresponding The terminal element's, which is partially driven by the second source driver SD2, receives the gate drive signal of the pulse waveform as shown by Gout_l_end due to the IR drop in the gate line. Specifically, when the transfer signal TP1_SD1 is asserted, the gate drive signal Gout_1 is first generated to activate the gate line, and the gate drive signal Gout-1 has a waveform of the start state (i.e., Gout_l_start). Then, after the first time interval (e.g., At), the transfer signal TP1_SD2 which is behind the start pulse signal TP1_SD1 is generated for the source actuator SD2 to start driving the pixels corresponding to the first gate line. When the gate drive signal Gout-1 is transmitted to the end of the gate line, the waveform of the gate drive signal G〇ut_l becomes a waveform of Gout_l_end. At this time, since the transfer signal TP1_SD2 is delayed, Gout_l_end can be de-asserted in time before the next transfer signal TP2_SD2 (for the next gate line) is issued. In this way, since the gate line that is operating can be stopped before the next gate line is activated, the display quality of the image can be improved. With the multi-timing switching pulse technique described above, the charging time of each pixel can be extended as compared with the prior art by extending the duration of the gate driving signal. 6 201033963 Furthermore, the above-mentioned transfer signals TP_SD1 and TP_SD2 may be sequentially generated by the timing controller' or sequentially generated according to the corresponding source driver. Furthermore, the 'interval' can be determined by the timing controller or the source driver, which can be set to a fixed value or a variable depending on different display time requirements (such as the corresponding gate line). Figure 4 is a diagram showing a display in accordance with another embodiment of the present invention. The display 400 includes a timing controller (not shown), a panel 410, source drivers SD1, SD2, ..., and SD12, gate drivers GDU, GD12, ..., and GD GDln, and gate drivers GD21, GD22, ..., and GD2n. The gate drivers GD11, GD12, ..., and GDln are disposed on one side of the panel 410 to control the gate lines, and the gate drivers GD21, GD22, ..., and GD2n are disposed on the other side of the panel 410 to control the gates. Polar line. In one embodiment, the gate lines are all controlled by gate drivers on both sides of the panel 410; in another embodiment, the gate lines are divided into right gate lines and left gate lines, and are respectively panel Controlled by the gate drivers on both sides of the 410. As shown in Fig. 4, the transfer signals transmitted to the source driver are different in one scan cycle. For example, the signal TP_SD2 is transmitted after the time interval Μ' is transmitted after the transmission signal TP_SD1 is issued; and so on, after the transmission signal TP_SD1 is issued, the transmission signal TP_SD6 is transmitted after a time interval of 5 χΔί. Since the panel 410 is driven by the gate drivers located on both sides of the panel 410, the distortion of the gate driving signal is most severe in the middle portion of the panel 410, so the source driver SD6 corresponding to the middle portion of the gate line is SD7 will receive the transmitted signal with the maximum delay time. It is worth noting that the delay time of 7 201033963 may vary between different source drivers in addition to the delay time in the above example depending on the fixed increment value. It is also worth noting that, in the above embodiment, the source driver can receive an original transfer signal first, and then each source driver generates a corresponding one by delaying the original transfer signal by a different cycle time. Pass the signal. For example, the source driver SD1 receives the transfer signal TP_SD1' and the source driver SD2 delays the transfer signal TP_SD1 by a certain period of time 'to generate its own transfer signal TP_SD2' and so on. . In addition, the above-described transfer signals received or generated by the source driver may have different pulse widths.
It can be seen from the above embodiments of the present invention that the display driven by the multi-timing transfer signal technology can extend the start-up time (or width) of the gate drive signal, so that the charging time of the pixels in the display can be prolonged. It can be charged to the target voltage level more easily. In addition, the display driven by the multi-timing transfer signal technology described above can also solve the problem that the gate drive signal is seriously attenuated when the circuit load increases, and when the display operating frequency (ie, the start pulse signal for the gate device) When the generated frequency is increased, the period of the gate driving signal becomes too short. The present invention has been disclosed in the above embodiments, and it is not intended to be limited to those skilled in the art, and the scope of protection of the present invention is The scope of the patent application attached is subject to the provisions of the patent application. [Simple description of the drawing] When the time of the input is not normal, the start pulse signal and the gate drive signal are transmitted. 201033963 Fig. 2 is a view showing a display according to an embodiment of the present invention. Figure 3 is a timing diagram showing a transfer signal and a gate drive signal in accordance with an embodiment of the present invention. Figure 4 is a diagram showing a display in accordance with another embodiment of the present invention. [Main component symbol description] 200, 400: Display 210, 410: Panel ® 212 : Timing controller ❹ 9