201033963 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種顯 ,顯不器，且特別是有關於一種藉 由多時序働旒技術所驅動之顯示器。 【先前技術】 在-般的顯示器中’其通常會包括 、201033963 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a display, a display, and more particularly to a display driven by a multi-timing technique. [Prior Art] In a general display, it usually includes,
驅動器以及時序控制器， ^ 早始。备德、驅動由一列晝素所組成之一條水 閘極驅：作轳二Ϊ生而使源極驅動器輪出驅動電壓時， : β儿 據傳遞信號由閘極驅動器產生，以驅動 1對應的閘極線及相對應㈣ :二減，使得閘極驅動信號於傳送至閘極 、从端時發生失真的情形，並因而使顯示器無法正確地 運作。 第1圖係繪示一般啟始脈衝信號及閘極驅動信號於傳 輸時的時序圖。如帛1圖所示，當傳遞信號ΤΡ1產生時， 閑極驅動信號Gout—1會根據傳遞信號ΤΡ1產生，以傳送至 一條對應的閘極線（如：第丨閘極線），且閘極驅動信號 Gout-1會根據閘極線的電壓降(IR drop)而衰減。 具體地來說，當閘極驅動信號Gout_l —開始產生以驅 動閑極線時，閘極驅動信號Gout-丨具有啟始狀態的方波（即 Gout—1—start)。捿著，當閘極驅動信號G〇ut_i傳輸一定距 離之後’閘極驅動信號Gout_l會因電壓降而嚴重衰減，變 201033963 成失真狀態而具有失真的波形（即Gout_l_end)。 當下一個傳遞信號產生時，失真的閘極驅動信號 Gout_l__end無法即時結束(如符號A所示），如此一來，在 第1閘極線末端的閘極驅動信號Gout_l一end，會與第2間 極線的閘極驅動信號Gout_2_start部分重疊，使得影像的 顯示品質受到極大的影響。 【發明内容】 . <Driver and timing controller, ^ early start. Bude, the drive consists of a column of sluice gates: When the source driver turns the driving voltage, the β-send signal is generated by the gate driver to drive the corresponding gate. The polar line and the corresponding (4): the second subtraction causes the gate drive signal to be distorted when it is transmitted to the gate and the slave terminal, and thus the display cannot operate properly. Fig. 1 is a timing chart showing the general start pulse signal and the gate drive signal at the time of transmission. As shown in Fig. 1, when the transfer signal ΤΡ1 is generated, the idle drive signal Gout-1 is generated according to the transfer signal ΤΡ1 to be transmitted to a corresponding gate line (eg, the first gate line), and the gate The drive signal Gout-1 is attenuated according to the voltage drop (IR drop) of the gate line. Specifically, when the gate drive signal Gout_1 is initially generated to drive the idle line, the gate drive signal Gout-丨 has a square wave of the start state (i.e., Gout_1-start). Next, when the gate drive signal G〇ut_i transmits a certain distance, the gate drive signal Gout_l is severely attenuated by the voltage drop, and the distortion of the 201033963 is a distortion waveform (ie, Gout_l_end). When the next transfer signal is generated, the distorted gate drive signal Gout_l__end cannot end immediately (as indicated by symbol A), so that the gate drive signal Gout_l_end at the end of the first gate line will be compared with the second The gate driving signals Gout_2_start of the polar lines are partially overlapped, so that the display quality of the image is greatly affected. [Summary of the Invention] . <
本發明之一目的是在提供一種顯示器及其驅動方法， 藉以改善影像的顯示品質。 本發明之一技術樣態係關於一種顯示器，其包括一面 板，一閘極驅動器以及複數個源極驅動器。面板包含以陣 列形式配置之複數個晝素。閘極驅動器係用以選擇性地驅 動面板中之一閘極線。源極驅動器係用以在一掃描週期間 接收複數個傳遞信號，每一個傳遞信號係相對應於源極驅 動器其中一者，當源極驅動器由相對應之傳遞信號所觸發 時，源極驅動器驅動相對應閘極線之晝素其中之一列晝 素’其中上述傳遞信號不完全相同。 本發明之一技術樣態係關於一種驅動顯示器之方法， 其包括在-掃&週期間接收複數個#遞信i，且這 信號分別相對應於源極驅動器，其中上述傳遞信號^完4 相同，以及在接收相對應之傳遞信號時藉由相對應之 驅動器驅動㈣。 根據本發明之技術内容，應用前述顯示器及其驅動^ 法叮避免閘極驅動信號傳輸至閘極線末端時，影響下一 201033963 閘極線的閘極驅動信號，進而改善影像的顯示品質。 【實施方式】 第2圖係繪示依據本發明實施例之一種顯示器。顯示 器200包含面板210、時序控制器212、源極驅動器SD1 和SD2以及閘極驅動器GD。面板210包含以陣列形式配 置的畫素。時序控制器212耦接於源極驅動器SD1和SD2, 並分別傳送具不同相位的傳遞信號(transfer pulse) TP_SD 1 ❿ 和TP_SD2至源極驅動器SD1和SD2。在另一實施例中， 時序控制器212係分別經由控制線與源極驅動器sdi和 SD2耦接，並經由控制線各自傳送傳遞信號Tp_SD1和 TP一SD2至源極驅動器SD1和SD2。此外，同一列上的書 素係連接於由閘極驅動器GD所控制之一條閘極線，並且 由源極驅動器SD1和SD2所驅動。在一個掃描週期⑴狀 period)間，閘極驅動器GD係選擇性地驅動其中一條閘極 線’且源極驅動器SD1和SD2依據傳遞信號Tp sm和 ❹ TP—SD2，輸出驅動電壓至該閘極線所對應的畫素:另外， 在本實施例中’傳遞信號TP一SD1和TP—SD2則是在一個 掃描週期中彼此間具有不同的時序，使得在源 SD1輸出驅動電壓之後’源極驅動器SD2才立'即輸出驅^ 第3圖係纷示依據本發明實施例之一種傳遞信號和閉 極驅動信號的時序圖。參照第2圖和第3囷，在第一掃扩 週期m中，首先產生傳遞信號TP1_sm，以供源極驅^ 器SD1輸出驅動電壓，而相對應的閘極線(如：第丨閘極線) 201033963 由閘極驅動信號Gout_l所驅動，且源極驅動器SD1由傳 遞信號TPi_sm所觸發，以驅動相對應第1閘極線的晝 素。之後，立即產生落後於啟始脈衝信號TP1_SD1的傳遞 信號TP1_SD2，以供源極驅動器SD2輸出驅動電壓，驅動 相對應第1閘極線的晝素。當相對應第1閘極線前端部分 且由第一源極驅動器SD1所驅動的前端晝素，係接收如 Gout_l _start所示之脈衝波形的閘極驅動信號時，相對應第 1閘極線末端部分且由第二源極驅動器SD2所驅動的末端 晝素’會因閘極線中電壓降(IR drop)的緣故，而接收如 Gout_l_end所示之脈衝波形的閘極驅動信號。 具體地來說，當傳遞信號TP1_SD1發出（assert)時，首 先會產生閘極驅動信號Gout_l來啟動閘極線，且閘極驅動 信號Gout一 1具有啟始狀態的波形（即Gout_l_start)。然後， 在第一時間間隔（如：At)之後，落後於啟始脈衝信號 TP1_SD1的傳遞信號TP1_SD2才產生，以供源極駆動器 SD2開始驅動相對應第1閘極線的畫素。在閘極驅動信號 Gout一1傳送至閘極線末端時，閘極驅動信號G〇ut_l的波 形會變成Gout_l_end的波形。此時，由於傳遞信號 TP1_SD2延遲，因此在下一個傳遞信號TP2—SD2(供下一條 閘極線）發出前，Gout—l_end可及時地變為取消 (de-assert)。如此一來，由於在下一條閘極線啟動之前便可 停止正在動作的閘極線，因此可改善影像的顯示品質。以 上述此種多時序轉換脈衝技術而言，可相較於先前技術延 長閘極驅動信號的持續期間，使得每一個晝素的充電時間 亦因此得以延長。 6 201033963 此外’上述傳遞信號TP_SD1和TP—SD2可依序由時 序控制器產生’或者根據對應的源極驅動器依序產生。再 者’時間間隔Μ可由時序控制器或源極驅動器來決定，其 可依據不同的顯示時間需求（如相對應的閘極線)設定為定 值或變數。 第4圖係繪示依據本發明另一實施例之顯示器。顯示 器400包含時序控制器（未繪示）、面板410、源極驅動器 SD1、SD2、…和SD12、閘極驅動器GDU、GD12、…和 ❹ GDln以及閘極驅動器GD21、GD22、…和GD2n。閘極驅 動器GD11、GD12、…和GDln係配置於面板410之一侧 以控制閘極線，而閘極驅動器GD21、GD22、...和GD2n 則是配置於面板410之另一側以控制閘極線。在一實施例 中，閘極線均由面板410兩側的閘極驅動器所控制；在另 一實施例中，閘極線是分為右側閘極線以及左侧閘極線， 且分別由面板410兩側的閘極驅動器所控制。 如第4圖所示’在一個掃描週期中，傳送至源極驅動 ❹ 器的傳遞信號是不相同的。舉例來說，在傳遞信號TP_SD1 發出後經過時間間隔Μ’傳遞信號TP_SD2才發出；依此 類推，在傳遞信號TP一SD1發出後經過時間間隔5χΔί，傳 遞信號TP_SD6才發出。因為面板410是由位於面板410 兩侧的閘極驅動器所驅動’所以閘極驅動信號的失真情形 在面板410的中間部分最為嚴重，因此對應於閘極線中間 部分晝素的源極驅動器SD6和SD7，會接收具有最大延遲 時間的傳遞信號。值得注意的是’除了上述例子中依固定 增量值變化的延遲時間之外，不同源極驅動器之間所對應 7 201033963 的延遲時間亦可為變動的。 另外值得注意的是，以上述實施例而言，源極驅動器 可先接收一個原始傳遞信號，接著每一個源極驅動器再藉 由將此原始傳遞信號延遲相異之週期時間，而產生各自所 對應之傳遞信號。舉例來說，源極驅動器SD1接收傳遞信 號TP—SD1 ’而源極驅動器SD2則是藉由將傳遞信號 TP一SD1延遲一定週期時間’以產生其本身的傳遞信號 TP一SD2 ’其餘依此類推。此外，上述由源極驅動器接收或 產生的傳遞信號，其脈衝寬度可不相同。It is an object of the present invention to provide a display and a method of driving the same to improve the display quality of an image. One aspect of the present invention relates to a display comprising a side panel, a gate driver and a plurality of source drivers. The panel contains a number of pixels configured in an array. A gate driver is used to selectively drive one of the gate lines in the panel. The source driver is configured to receive a plurality of transfer signals during a scan period, each of the transfer signals corresponding to one of the source drivers, and the source driver is driven when the source driver is triggered by the corresponding transfer signal One of the elements corresponding to the gate line is a halogen element, wherein the above-mentioned transfer signals are not completely identical. A technical aspect of the present invention relates to a method of driving a display, comprising receiving a plurality of #delivery i during a -sweep & period, and the signals respectively correspond to a source driver, wherein the above-mentioned transfer signal is completed 4 The same, and when receiving the corresponding transfer signal, drive by the corresponding driver (4). According to the technical content of the present invention, the display and the driving method thereof are applied to prevent the gate driving signal from being transmitted to the end of the gate line, thereby affecting the gate driving signal of the next 201033963 gate line, thereby improving the image display quality. [Embodiment] FIG. 2 is a view showing a display according to an embodiment of the present invention. The display 200 includes a panel 210, a timing controller 212, source drivers SD1 and SD2, and a gate driver GD. Panel 210 contains pixels arranged in an array. The timing controller 212 is coupled to the source drivers SD1 and SD2 and respectively transmits transfer pulses TP_SD 1 ❿ and TP_SD2 having different phases to the source drivers SD1 and SD2. In another embodiment, the timing controller 212 is coupled to the source drivers sdi and SD2 via control lines, respectively, and transmits the transfer signals Tp_SD1 and TP_SD2 to the source drivers SD1 and SD2, respectively, via the control lines. Further, the books on the same column are connected to one of the gate lines controlled by the gate driver GD, and are driven by the source drivers SD1 and SD2. Between one scan period (1), the gate driver GD selectively drives one of the gate lines' and the source drivers SD1 and SD2 output a driving voltage to the gate according to the transfer signals Tp sm and TP TP-SD2. The pixel corresponding to the line: In addition, in the present embodiment, the 'transfer signals TP_SD1 and TP-SD2 have different timings with each other in one scan period, so that the source driver is after the source SD1 outputs the driving voltage. SD2 is the output driver. FIG. 3 is a timing diagram showing a transfer signal and a closed-pole drive signal according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, in the first sweeping period m, the transfer signal TP1_sm is first generated for the source driver SD1 to output the driving voltage, and the corresponding gate line (eg, the first gate) Line) 201033963 is driven by the gate drive signal Gout_l, and the source driver SD1 is triggered by the transfer signal TPi_sm to drive the pixels corresponding to the first gate line. Immediately thereafter, a transfer signal TP1_SD2 which is behind the start pulse signal TP1_SD1 is generated so that the source driver SD2 outputs a drive voltage to drive the pixel corresponding to the first gate line. When the front end element corresponding to the front end portion of the first gate line and driven by the first source driver SD1 receives the gate driving signal of the pulse waveform as indicated by Gout_l_start, the end of the first gate line is corresponding The terminal element's, which is partially driven by the second source driver SD2, receives the gate drive signal of the pulse waveform as shown by Gout_l_end due to the IR drop in the gate line. Specifically, when the transfer signal TP1_SD1 is asserted, the gate drive signal Gout_1 is first generated to activate the gate line, and the gate drive signal Gout-1 has a waveform of the start state (i.e., Gout_l_start). Then, after the first time interval (e.g., At), the transfer signal TP1_SD2 which is behind the start pulse signal TP1_SD1 is generated for the source actuator SD2 to start driving the pixels corresponding to the first gate line. When the gate drive signal Gout-1 is transmitted to the end of the gate line, the waveform of the gate drive signal G〇ut_l becomes a waveform of Gout_l_end. At this time, since the transfer signal TP1_SD2 is delayed, Gout_l_end can be de-asserted in time before the next transfer signal TP2_SD2 (for the next gate line) is issued. In this way, since the gate line that is operating can be stopped before the next gate line is activated, the display quality of the image can be improved. With the multi-timing switching pulse technique described above, the charging time of each pixel can be extended as compared with the prior art by extending the duration of the gate driving signal. 6 201033963 Furthermore, the above-mentioned transfer signals TP_SD1 and TP_SD2 may be sequentially generated by the timing controller' or sequentially generated according to the corresponding source driver. Furthermore, the 'interval' can be determined by the timing controller or the source driver, which can be set to a fixed value or a variable depending on different display time requirements (such as the corresponding gate line). Figure 4 is a diagram showing a display in accordance with another embodiment of the present invention. The display 400 includes a timing controller (not shown), a panel 410, source drivers SD1, SD2, ..., and SD12, gate drivers GDU, GD12, ..., and GD GDln, and gate drivers GD21, GD22, ..., and GD2n. The gate drivers GD11, GD12, ..., and GDln are disposed on one side of the panel 410 to control the gate lines, and the gate drivers GD21, GD22, ..., and GD2n are disposed on the other side of the panel 410 to control the gates. Polar line. In one embodiment, the gate lines are all controlled by gate drivers on both sides of the panel 410; in another embodiment, the gate lines are divided into right gate lines and left gate lines, and are respectively panel Controlled by the gate drivers on both sides of the 410. As shown in Fig. 4, the transfer signals transmitted to the source driver are different in one scan cycle. For example, the signal TP_SD2 is transmitted after the time interval Μ' is transmitted after the transmission signal TP_SD1 is issued; and so on, after the transmission signal TP_SD1 is issued, the transmission signal TP_SD6 is transmitted after a time interval of 5 χΔί. Since the panel 410 is driven by the gate drivers located on both sides of the panel 410, the distortion of the gate driving signal is most severe in the middle portion of the panel 410, so the source driver SD6 corresponding to the middle portion of the gate line is SD7 will receive the transmitted signal with the maximum delay time. It is worth noting that the delay time of 7 201033963 may vary between different source drivers in addition to the delay time in the above example depending on the fixed increment value. It is also worth noting that, in the above embodiment, the source driver can receive an original transfer signal first, and then each source driver generates a corresponding one by delaying the original transfer signal by a different cycle time. Pass the signal. For example, the source driver SD1 receives the transfer signal TP_SD1' and the source driver SD2 delays the transfer signal TP_SD1 by a certain period of time 'to generate its own transfer signal TP_SD2' and so on. . In addition, the above-described transfer signals received or generated by the source driver may have different pulse widths.
由上述本發明之實施例可知，應用前述多時序傳遞信 號技術所驅動之顯示器，可延長閘極驅動信號的啟動時間 (或寬度）’使得顯示器中畫素的充電時間可因此延長’且 晝素可更輕易地充電至目標電壓準位。此外，應用前述多 時序傳遞信號技術所驅動之顯示器，亦可解決當電路負載 增加時閘極驅動信號嚴重衰減的問題，以及當顯示器的操 作頻率（即用於閘極職器之啟始脈衝信號產生的頻率）增 加時’閘極驅動信號的週期變得太短的問題。 定太^然本發明已以實施方式揭露如上，然其並非用以限 範圍内明熟習此技藝者’在不脫離本發明之精神和 作各種之更動與潤飾，因此本發明之保護範 圍虽視後附之申請專利範圍所紋者為準。 【圖式簡單說明】 輸時的時^ ^繪不一般啟始脈衝信號及閘極驅動信號於傳 201033963 第2圖係繪示依據本發明實施例之一種顯示器。 第3圖係繪示依據本發明實施例之一種傳遞信號和閘 極驅動信號的時序圖。 第4圖係繪示依據本發明另一實施例之顯示器。 【主要元件符號說明】 200、400 :顯示器 210、410 :面板 ® 212 :時序控制器 ❹ 9It can be seen from the above embodiments of the present invention that the display driven by the multi-timing transfer signal technology can extend the start-up time (or width) of the gate drive signal, so that the charging time of the pixels in the display can be prolonged. It can be charged to the target voltage level more easily. In addition, the display driven by the multi-timing transfer signal technology described above can also solve the problem that the gate drive signal is seriously attenuated when the circuit load increases, and when the display operating frequency (ie, the start pulse signal for the gate device) When the generated frequency is increased, the period of the gate driving signal becomes too short. The present invention has been disclosed in the above embodiments, and it is not intended to be limited to those skilled in the art, and the scope of protection of the present invention is The scope of the patent application attached is subject to the provisions of the patent application. [Simple description of the drawing] When the time of the input is not normal, the start pulse signal and the gate drive signal are transmitted. 201033963 Fig. 2 is a view showing a display according to an embodiment of the present invention. Figure 3 is a timing diagram showing a transfer signal and a gate drive signal in accordance with an embodiment of the present invention. Figure 4 is a diagram showing a display in accordance with another embodiment of the present invention. [Main component symbol description] 200, 400: Display 210, 410: Panel ® 212 : Timing controller ❹ 9