201033710 六、發明說明： 【發明所屬之技術領域】 本發明係-種畫素佈局結構，其係制關於—種不同元件結 構(Top-gate 與 bottom-gate)，來設計 DouWe gate pjxe丨，達到維持原 single gate pixel開σ率的目的並提高D〇ub丨e gate p|xe丨開夺 佈局結構。 【先前技術】 液晶顯不器活用其薄型、輕量、低耗電力及不會帶來環境上的負 擔等的特性’在各應用領域中使用佔有率相當地高…般液晶顯示器 鬌通常係採用主勢矩陣箱動電路來控制顯示面板的作動，且隨著顯示技 術的蓬勃祕，如何提高顯示品倾_成本乃是目前料所努 服之二大課題。 為解決資料線數量及資料驅動器數量過多的導致問題，先前技術 之主動矩陣式液晶顯示面板的驅動電路係為雙閘(D〇ub丨e獅)媒動電 路’其畫素佈局結構如第所示，賴中可知，先前技術係於一基 板上以第-金屬層形成掃描線12、14、16、18、第一電晶體之閉極 2〇及第二電晶體之閘極22 ’且掃据線14與第一電晶體之閘極22連 鲁 接’知描線16與第一電晶體之閘極20連接。 將第-絕緣層覆於第-金屬層上後，於第一絕緣層上製作一個非 晶石夕層，以形成第-電晶艘之通道24及第二電晶體之通道26。再於 非晶秒層上製作-第二金屬層，以形成-數據線28、該第一電晶體之 源極30與没極32及第二電晶體之源極34與没極36。再將第二絕緣 廣覆於第二金屬層及非㈣層上，並且於第二絕緣層上製作導電薄膜 層以形成第-導電薄膜38及第二導電薄膜4Q，其中本實施例知第一 電晶艘或第二電晶體之驅動方式係採用Η型儲存電容利用共同走線 (Cson Com)的設計，因此可從圖示中得知第一電晶體的cs42位於第 一晝素44中間，第二電晶體的CS46位於第二畫素48中間。 201033710 备 上述之畫素佈局結構因為採用畫素佈局結構係採用D〇Ub|e Gate 的設計，因此掃描線14、16以俯視的角度來看，係為相鄰者。 由於double gate的設計’是將目前的source |jne數目減半，而 將gate line數目加倍，而達到整體的channe丨減少的效果，例如一般 800xRGBx480 ’總channe丨數為2880，經過double設計可減少 1200x960，總 channe丨數為 2160。 但是由於Double gate的設計，畫素掃瞄線(gate丨丨㈣的數目會增 加一倍’這樣會使得開口率下降5~7%，如果要維持原來的產品規格， 必須藉由光學或是背光模組的設計來維持原來產品的規格。為此，本 © 發明提出一種具有高開口率的畫素設計之佈局結構，以解決上述問題》 【發明内容】 本發明之主要目的在提供-種具有高開σ率的畫素設計之佈局結 構，其係利用Top-gate與bottom-gate兩種不同的元件結構，來設計 Double gate，這樣的設計可以讓兩條相鄰的掃描線(卵伯|jne)上下相 疊’達到維持開口率的目的。 本發明之另一目的在提供一種具有高開口率的畫素設計之佈局結 構，其係利用兩種不同的金屬層做為掃描線(scan nne)的導線，所以可 以上下並排，而達到維持開口率的目的。 © 本發明之又-目的在提供_種具有高開口率的畫素設計之佈局結 構，其係利用Top-gate與bottom-gate兩種不同的元件結構，由於電 壓值是相同的，所以彼此在傳遞訊號時，並不會互相干擾，可以維持 double gate降低成本的優點。 本發明提供·種具有高開口率的畫素設計之佈局結構，包括一基 板，第-金屬層於基板上形成第_掃描線、第—電㈣之閘極及遮光 面’且第-掃描線與第一電晶體之閉極連接。於第一金屬層上形成第 -絕緣層，非祕層於第—絕緣層上形成該第—f晶體之通道及第二 電晶趙之通道。第二金屬層於非晶石夕層上形成一數據線第一電晶艘 4 201033710 之源極與汲極及第二電晶體之源極與汲極，第二絕緣層則位於第二金 屬層上方。導電薄膜位於第二絕緣層上，以形成第一電晶艘及第二電 晶艘之畫素電極。導電薄膜同時也會於第二電晶體之源極與汲極的上 方形成’作為第二電晶體的閘極及第二掃描線。第二電晶體之第二掃 描線與第一電晶體之第一掃描線重疊。 本發明是利用Top-gate與bottom-gate兩種不同的元件結構，來 設計Double gate，這樣的設計可以讓兩條相鄰的掃描線(gate Hne)上 下相番。利用兩種不同的金屬層做為scan line的導線，所以可以上下 並排’而達到維持開口率的目的，這樣的設計，可以維持double gate 〇 降低成本的優點，另外由於電壓值是相同的，所以彼此在傳遞訊號時， 並不會互相干擾。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本 發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 為能詳細說明本發明請同時參照第二圖、第三圖及第四圖。本發 明之具有高開口率的畫素設計之佈局結構，係於一基板58(玻璃基板) 上以第一金屬層形成掃描線52、第一掃描線54，第一電晶體之閘極 60及遮光面62 ’且第一掃描線54與第一電晶體之閘極60連接。其 © 中’遮光面62作為第一電晶體之閘極之遮光層，係用來防止光漏流現 象。 將第一絕緣層90覆於第一金屬層上後；於第一絕緣層90上製作 一個非晶矽層92，以形成第一電晶體之通道64及第二電晶體之通道 66’本實施例之第一絕緣層90係由氧化矽或氮化矽等介電材料組成。 再於非晶矽層92上製作一第二金屬層，以形成一數據線68、第一電 晶體之源極70與汲極72及第二電晶體之源極74與汲極76。再將第 二絕緣層94覆於第二金屬層及非晶矽層92上，並且於第二絕緣層94 上製作導電薄膜層以形成第一導電薄膜78及第二導電薄膜80，本實 201033710 施例之第二絕緣層94係由氧化矽或氮化矽等介電材料組成。 其中，第二導電薄膜80 ’係作為第二電晶體的閘極96及第二掃 描線56，第二導電薄膜80位於該第二絕緣層94上及該第二電晶艘之 源極74與汲極76的上方’第二掃描線56位於第一掃描線54上方， 並向外延伸成第二電晶艘的閘極96，使得第二掃描線56與第一掃描 線 54 部分重 ^(overlap)。 其中本實施例之第一電晶髏或第二電晶體之驅動方式係採用儲存 電容利用共同走線(Cs on Com)的設計，因此可從圖示中得知第一電晶 體的CS82位於第一畫素84中間，第二電晶體的CS86位於第二畫素 Ο 88中間。本發明之另一實施例係第一電晶體或第二電晶體之驅動方式 採用儲存電容利用閘極走線（Cs on Gate)的媒動方式，設計方式相 似，故不贅述。 本發明是利用Top-gate與bottom-gate兩種不同的元件結構，來 設計Double gate，這樣的設計可以讓兩條相鄰的掃描線(gate丨丨ne)上 下相疊，本發明的實施例，可以將奇數條的晝素掃瞄線及其連接的電 晶體(薄膜電晶體），採用top gate結構；而偶數條的畫素掃瞄線及其 連接的電晶體(薄膜電晶體)，採用bottom gate結構。所以原本double gate的設計是在一個Pjxe|内會跨過兩條掃描線(scan Hne)，而利用本 © 發明的設計，雖然一樣是跨過兩條scan line，但是本發明是利用兩種 不同的金屬層（可利用_八丨灿3如丨丁0)做為3〇3门丨^的導線，所以 可以上下並排，而達到維持開口率的目的，這樣的設計，可以維持 double gate降低成本的優點，另外由於電壓值是相同的，所以彼此在 傳遞訊號時，並不會互相干擾。 唯以上所述者，僅為本發明之較佳實施例而已，並非用來限定本 發明實施之範圍。故即凡依本發明中請範圍所述之形狀、構造、特徵 及精神所為之均等變化或修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 201033710 第一圖係先前技術之畫素佈局結構示意圖。 第二圖係本發明之畫素佈局結構示意圖》 第三圖係本發明之局部畫素佈局結構示意圖。 第四圖係依據第三圖所繪之剖面線之畫素佈局結構剖示圖。 【主要元件符號說明】 12掃描線 14掃描線 16掃描線 18掃描線 20第一電晶艘之閘極 22第二電晶體之閘極 24第一電晶體之通道 26第二電晶體之通道 28數據線 30第一電晶體之源極 32第一電晶體之汲極 34第二電晶體之源極 36第二電晶體之汲極 〇 38第一導電薄膜 40第二導電薄膜 42第一電晶體的CS 44第一畫素 46第二電晶體的CS 48第二畫素 50掃描線 52掃描線 54第一掃描線 .201033710 56第二掃描線 58基板 60第一電晶體之閘極 62電極層 64第一電晶體之通道 66第二電晶體之通道 68數據線 70第一電晶體之源極 72第一電晶體之汲極 74第二電晶體之源極 76第二電晶體之汲_極 78第一導電薄膜 80第二導電薄膜 82第一電晶體的CS 84第一晝素 86第二電晶體的CS 88第二晝素 90第一絕緣層 〇 92非晶矽層 94第二絕緣層 96第二電晶體之閘極 8201033710 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a pixel layout structure for designing a DouWe gate pjxe丨 with respect to a different component structure (Top-gate and bottom-gate) Maintain the original single gate pixel σ rate and improve the layout structure of D〇ub丨e gate p|xe丨. [Prior Art] The liquid crystal display uses characteristics such as thinness, light weight, low power consumption, and no environmental burden. 'The occupancy rate in each application field is quite high... LCD monitors are usually used. The main potential matrix box moving circuit controls the operation of the display panel, and with the fascination of the display technology, how to improve the display product tilting cost is the second subject that the material is currently being accepted. In order to solve the problem of the number of data lines and the number of data drivers, the driving circuit of the active matrix liquid crystal display panel of the prior art is a double gate (D〇ub丨e lion) medium circuit, and its pixel layout structure is as follows. As shown, Laizhong knows that the prior art is to form scan lines 12, 14, 16, 18, a closed transistor 2〇 of the first transistor, and a gate 22' of the second transistor with a first metal layer on a substrate and sweep The line 14 is connected to the gate 22 of the first transistor, and the line 16 is connected to the gate 20 of the first transistor. After the first insulating layer is coated on the first metal layer, a non-crystal layer is formed on the first insulating layer to form a channel 24 of the first-electro-crystal cell and a channel 26 of the second transistor. A second metal layer is then formed over the amorphous second layer to form a -data line 28, a source 30 and a gate 32 of the first transistor, and a source 34 and a gate 36 of the second transistor. And further coating the second insulating layer on the second metal layer and the non-(four) layer, and forming a conductive thin film layer on the second insulating layer to form the first conductive film 38 and the second conductive film 4Q, wherein the first embodiment is first The driving mode of the electric crystal boat or the second transistor is designed by using a Cson Com type storage capacitor, so that the cs42 of the first transistor is located in the middle of the first halogen 44, as shown in the figure. The CS46 of the second transistor is located in the middle of the second pixel 48. 201033710 The above-mentioned pixel layout structure adopts the design of D〇Ub|e Gate in the pixel layout structure, so the scanning lines 14, 16 are adjacent to each other in a plan view. Since the design of the double gate is to halve the current number of source |jne and double the number of gate lines, the overall Channe丨 reduction effect is achieved, for example, the general 800xRGBx480 'the total number of Channe turns is 2880, which can be reduced by the double design. 1200x960, the total number of channe is 2160. However, due to the design of the Double Gate, the number of pixel scan lines (the number of gates (four) will double) will reduce the aperture ratio by 5 to 7%. If the original product specifications are to be maintained, optical or backlight must be used. The module is designed to maintain the specifications of the original product. To this end, the present invention proposes a layout structure of a pixel design having a high aperture ratio to solve the above problem. [ SUMMARY OF THE INVENTION The main object of the present invention is to provide The layout structure of the pixel design with high σ rate, which uses the two different component structures of Top-gate and bottom-gate to design the Double Gate. This design allows two adjacent scan lines (eg Jne) stacks up and down to achieve the purpose of maintaining the aperture ratio. Another object of the present invention is to provide a pixel design layout structure having a high aperture ratio, which uses two different metal layers as scan lines (scan nne) The wire can be arranged side by side to maintain the aperture ratio. © The present invention is also directed to providing a layout structure of a pixel design having a high aperture ratio, which utilizes Top-gat e and bottom-gate two different component structures, because the voltage values are the same, they do not interfere with each other when transmitting signals, and can maintain the advantage of double gate to reduce cost. The present invention provides a high aperture ratio The layout structure of the pixel design includes a substrate, the first metal layer forms a first scan line, a first (four) gate and a light blocking surface on the substrate, and the first scan line is connected to the first transistor. Forming a first insulating layer on the first metal layer, the non-secret layer forming a channel of the first f-crystal and a channel of the second electric crystal on the first insulating layer. The second metal layer is on the amorphous layer Forming a source of the first photocell 4 201033710, a source and a drain, and a source and a drain of the second transistor, and a second insulating layer over the second metal layer. The conductive film is on the second insulating layer. Forming a pixel electrode of the first electro-ceramic vessel and the second electro-ceramic vessel. The conductive film also forms a gate and a second scan as a second transistor above the source and the drain of the second transistor. a second scan line of the second transistor The first scan line of a transistor overlaps. The present invention utilizes two different component structures, Top-gate and bottom-gate, to design a double gate. This design allows two adjacent scan lines (gate Hne) to be placed up and down. The two different metal layers are used as the wires of the scan line, so they can be placed side by side to maintain the aperture ratio. This design can maintain the double gate and reduce the cost, and the voltage value is the same. Therefore, when the signals are transmitted to each other, they do not interfere with each other. The details of the present invention, the technical contents, the features and the effects achieved by the specific embodiments are explained in detail with reference to the accompanying drawings. . [Embodiment] In order to explain the present invention in detail, please refer to the second, third, and fourth drawings at the same time. The layout structure of the pixel design with high aperture ratio of the present invention is formed on a substrate 58 (glass substrate) with a first metal layer forming a scan line 52, a first scan line 54, a gate 60 of the first transistor, and The light shielding surface 62' and the first scanning line 54 are connected to the gate 60 of the first transistor. Its "Medium" light-shielding surface 62 serves as a light-shielding layer for the gate of the first transistor to prevent light leakage. After the first insulating layer 90 is coated on the first metal layer, an amorphous germanium layer 92 is formed on the first insulating layer 90 to form a channel 64 of the first transistor and a channel 66' of the second transistor. The first insulating layer 90 is composed of a dielectric material such as hafnium oxide or tantalum nitride. A second metal layer is formed on the amorphous germanium layer 92 to form a data line 68, a source 70 and a drain 72 of the first transistor, and a source 74 and a drain 76 of the second transistor. The second insulating layer 94 is coated on the second metal layer and the amorphous germanium layer 92, and a conductive thin film layer is formed on the second insulating layer 94 to form the first conductive film 78 and the second conductive film 80. The second insulating layer 94 of the embodiment is composed of a dielectric material such as hafnium oxide or tantalum nitride. The second conductive film 80' is used as the gate 96 of the second transistor and the second scan line 56. The second conductive film 80 is located on the second insulating layer 94 and the source 74 of the second transistor. The second scan line 56 above the drain 76 is located above the first scan line 54 and extends outwardly to the gate 96 of the second electro-ceramic vessel such that the second scan line 56 and the first scan line 54 partially overlap. Overlap). The driving mode of the first transistor or the second transistor of the embodiment is a design using a common capacitor (Cs on Com), so that the CS82 of the first transistor is located in the figure. In the middle of a pixel 84, the CS86 of the second transistor is located in the middle of the second pixel 88. Another embodiment of the present invention is a driving method of the first transistor or the second transistor. The storage mode uses a carrier mode of a gate-on-line (Cs on Gate), and the design is similar, so it will not be described again. The present invention utilizes two different element structures, Top-gate and bottom-gate, to design a double gate. This design allows two adjacent scan lines to be stacked one on top of the other. Embodiments of the present invention The odd-numbered pixel scanning line and its connected transistor (thin film transistor) can be used as a top gate structure; and the even number of pixel scanning lines and their connected transistors (thin film transistor) can be used. Bottom gate structure. So the original double gate design is to cross two scan lines (scan Hne) in a Pjxe|, and with the design of the invention, although the same is across two scan lines, the present invention utilizes two different The metal layer (which can be used as a wire of 3〇3 丨^), so it can be placed side by side up to maintain the aperture ratio. This design can maintain double gate cost reduction. The advantage, in addition, because the voltage values are the same, they do not interfere with each other when transmitting signals. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, any changes or modifications of the shapes, structures, features, and spirits described in the scope of the present invention should be included in the scope of the present invention. [Simple description of the schema] 201033710 The first diagram is a schematic diagram of the layout structure of the prior art. The second figure is a schematic diagram of the layout structure of the pixel of the present invention. The third figure is a schematic diagram of the partial pixel layout structure of the present invention. The fourth figure is a cross-sectional view of the pixel layout structure of the section line drawn according to the third figure. [Main component symbol description] 12 scan line 14 scan line 16 scan line 18 scan line 20 gate of the first electro-crystal cell 22 gate of the second transistor 24 channel of the first transistor 26 channel 28 of the second transistor Data line 30 first transistor source 32 first transistor drain 34 second transistor source 36 second transistor drain 〇 38 first conductive film 40 second conductive film 42 first transistor CS 44 first pixel 46 second transistor CS 48 second pixel 50 scan line 52 scan line 54 first scan line. 201033710 56 second scan line 58 substrate 60 first transistor gate 62 electrode layer 64 channel of the first transistor 66 channel of the second transistor 68 data line 70 source of the first transistor 72 drain of the first transistor 74 source of the second transistor 76 第二 of the second transistor 78 first conductive film 80 second conductive film 82 first transistor CS 84 first halogen 86 second transistor CS 88 second halogen 90 first insulating layer 〇 92 amorphous layer 94 second insulating layer 96 second transistor gate 8