201031119 六、發明說明： 【發明所屬之技術領域】 本發明涉及電子技術領域，特別涉及一種延時裝置。 【先前技術】 ❹ ❹ 通常，半報積體電路需要—個延時，㈣輸入該積體 =的控制訊號進行延時。例如，藉由在上電時對啟動訊號進行 t在上電至啟動的延時時間段内，可對積體電路的内部電路 =初=化從而避免積體電路發生故障。另外，藉由對關機訊號 延瞒_，可將龍電路_㈣路中正在 =的程式保存在記憶體中，從而防止_時積體電路的資料丟 時電Γ而^需要對該延時軸段進行調節，則必須重新設計延 =路’叫足積體電路對啟動訊號的不同延時需求。缺，重新 ㈣蝴縣，糾_花費一定的時 間興精力，給設計人貞帶來了煩惱。 【發明内容】 有ί於t，*必要提供—種延時時間段可調的延時裝置。 時操作該 容的延時單元。财_細 ^70及具有可魏 元之間，其另-端接地。卿=:控電源及訊號產生單 電容進行充電。當該可調電容;號時對可調 生單元產生輸出訊號。 達到财賴值時，該訊號產 上述延時裝置設置有可調電容。可藉由調節該可調電容的電 4 201031119 * , 容值來實現不同的充電時間及放電時間，並在該可調電容的充電 •電壓及放電電壓達到預定電壓值時產生輸出訊號。如此可有效地 實現對輸入訊號進行延時，並產生輸出訊號。該輸出訊號相對於 輸入訊號被延時了不同的時間段，滿足設計人員的電路設計需求。 【實施方式】 如圖1所示係一較佳實施方式的延時裝置iOO的功能模組 圖。延時裝置100用於對訊號源K)提供的輸入訊號的上升沿或下降 φ 沿進行延時’並產生延時後的輸出訊號提供給外部積體電路 (IntegratedCircuit，圖未示），以作為控制訊號控制積體電路完成 特定功能。例如’藉由對上電啟動訊號進行延時，可在延時時間 段對積體電路的内部電路進行初始化。 • 延時裝置包括可控電源12、延時單元15及訊號產生單元 • 16 ° 可控電源12用於在訊號源1〇提供的輸入訊號的下降沿或上 升沿提供工作電壓給延時單元15。 φ 延時單元15用於接收該工作電壓，並產生延時訊號。 訊號產生單元16用於對延時訊號進行整形，並產生輸出訊 號。 請一併參閱圖2,其為第一較佳實施方式的延時裝置100A的 具體電路圖’該延時裝置100A用於對輸入訊號的上升沿進行延時。 可控電源12A包括一直流電源Vcc、電阻R1及電子開關14A。 電子開關14A用於在訊號源1〇提供的輸入訊號的下降沿導通，在輪 入訊號的上升沿截止。在本實施方式中，電子開關14八為PNP型三 極體Q1。三極體Q1的基極藉由電阻剋連接訊號源10，射極連接直 5 '201031119 流電源Vcc。 . 延時單元15包括可調電容C及電阻R2,該可調電容c及電阻 • R2並聯在三極體Q1的集極與地之間。 訊號產生單元16包括一施密特觸發器D。施密特觸發器D具 有輸入端18、輸出端20、第-埠22及第二琿24。輪入端18^三極 體Q1的集極相連，第一埠22連接直流電源Vcc，第二埠24接地。施 密特觸發器D具有一正向閾值電壓V+及負向閾值電壓V。當輸入 φ 端18的電壓小於負向閾值電壓V-，輸出端20將輸出高電平電壓。 當輸入端18的電壓介於負向閾值電壓¥_及正向閾值電壓v+之間 時，輸出端20的輸出電壓維持不變。當輸入端18的電壓大於正向 閾值電壓V+時’輸出端2〇將輸出低電平電壓。 請一併參閱圖3，延時裝置100A的工作原理如下： 當訊號源10的輸入訊號Μ為低電平時，三極體Q1導通。直流 電源Vcc對可調電容c進行充電，從而使輸入端怊的電壓％瞬間上 升為高電平電壓。當輸人端_電壓上升至v+時，觸發器D的輸 參 出端20的電壓Vo變為低電平電壓。 當訊號源10的輸入訊號Vi從低電平變為高電平時，三極體〇1 截止。可調電容C藉由電阻R2放電，放電時間為t=R2*C，從而使 輸入端18的電壓_力下降為低電平電壓。當輸人端18的電麼Va 下降至V-時，觸發器D的輸出端2〇的電壓v〇變為高電平電壓。 如此’延時裝置100A可對訊號源1〇的輸入訊號％的上升沿 (即從低電平變為高電平）進行延時，輸出訊號Vo的上升沿相對 於輸入訊號Vi社升沿賴了時間T=R2,C。制了延遲輸入訊號 Vi的上升沿的目的，由於可調電容C的電容值可調節，故延時 201031119 T=R2*C也可調節，狀外部積體電路對延時時間段的可調節需 求。利用該麟咖段，外部積體電路可對其⑽電路進行初始 ^ ’確保频電路不會出錯。該輸出城VG還可作為控制訊號來 控制積體電路完成其他特定功能。 另外，藉由調整直流電源Vcc的大小，可實現調節觸發器D 的輸出端20的輸出電壓v〇的幅值大小，滿足不同的需求。 鲁201031119 VI. Description of the Invention: [Technical Field] The present invention relates to the field of electronic technology, and in particular to a delay device. [Prior Art] ❹ ❹ Normally, the half-report integrated circuit requires a delay, and (4) the control signal input to the integrated body = delay. For example, by delaying the start-up signal during power-on to the start-up delay period during power-on, the internal circuit of the integrated circuit can be initialized to avoid malfunction of the integrated circuit. In addition, by delaying the shutdown signal _, the program in the _ (four) way of the dragon circuit can be saved in the memory, thereby preventing the data of the _ time integrated circuit from being lost and the need for the delay axis segment To make adjustments, it is necessary to redesign the different delay requirements of the delay signal for the start signal. Lack, re- (4) Butterfly County, correcting _ spend a certain amount of time to bring energy to the designer. SUMMARY OF THE INVENTION There is a need to provide a delay device with adjustable delay time period. The delay unit of the operation is operated. Treasury _ fine ^70 and between the Wei and Yuan, the other end of the ground. Qing =: Control the power supply and signal to generate a single capacitor for charging. When the adjustable capacitor; number, the output signal is generated for the adjustable unit. When the value of the money is reached, the signal generating device has a tunable capacitor. The charging time can be adjusted by adjusting the capacitance of the adjustable capacitor to achieve different charging time and discharging time, and the output signal is generated when the charging voltage and the discharging voltage of the adjustable capacitor reach a predetermined voltage value. This effectively delays the input signal and produces an output signal. The output signal is delayed for a different period of time than the input signal to meet the designer's circuit design requirements. [Embodiment] FIG. 1 is a functional block diagram of a delay device iOO according to a preferred embodiment. The delay device 100 is configured to delay the rising edge or the falling edge of the input signal provided by the signal source K) and output the delayed output signal to the external integrated circuit (not shown) for control signal control. The integrated circuit performs a specific function. For example, by delaying the power-on start signal, the internal circuit of the integrated circuit can be initialized during the delay time period. • The delay device includes a controllable power supply 12, a delay unit 15 and a signal generation unit. • The 16 ° controllable power supply 12 is used to supply the operating voltage to the delay unit 15 at the falling or rising edge of the input signal provided by the signal source 1 . The φ delay unit 15 is configured to receive the operating voltage and generate a delay signal. The signal generating unit 16 is configured to shape the delayed signal and generate an output signal. Please refer to FIG. 2, which is a specific circuit diagram of the delay device 100A of the first preferred embodiment. The delay device 100A is used to delay the rising edge of the input signal. The controllable power supply 12A includes a DC power supply Vcc, a resistor R1, and an electronic switch 14A. The electronic switch 14A is used to turn on at the falling edge of the input signal provided by the signal source 1 and to be turned off at the rising edge of the round signal. In the present embodiment, the electronic switch 14 is a PNP type diode Q1. The base of the triode Q1 is connected to the signal source 10 by a resistor, and the emitter is connected to a direct current 5 '201031119 flow source Vcc. The delay unit 15 includes a tunable capacitor C and a resistor R2, which is connected in parallel between the collector of the transistor Q1 and the ground. The signal generating unit 16 includes a Schmitt trigger D. The Schmitt trigger D has an input terminal 18, an output terminal 20, a first - 22 and a second port 24. The collectors of the 18^ three-pole body Q1 are connected, the first port 22 is connected to the DC power source Vcc, and the second port 24 is grounded. The Schmitt trigger D has a forward threshold voltage V+ and a negative threshold voltage V. When the voltage at the input φ terminal 18 is less than the negative threshold voltage V-, the output terminal 20 will output a high level voltage. When the voltage at the input terminal 18 is between the negative threshold voltage ¥_ and the forward threshold voltage v+, the output voltage of the output terminal 20 remains unchanged. When the voltage at the input terminal 18 is greater than the forward threshold voltage V+, the output terminal 2 输出 will output a low level voltage. Referring to FIG. 3 together, the working principle of the delay device 100A is as follows: When the input signal Μ of the signal source 10 is low, the transistor Q1 is turned on. The DC power supply Vcc charges the adjustable capacitor c, so that the voltage % at the input terminal is instantaneously raised to a high level voltage. When the input terminal voltage rises to v+, the voltage Vo of the input terminal 20 of the flip-flop D becomes a low level voltage. When the input signal Vi of the signal source 10 changes from a low level to a high level, the triode 〇1 is turned off. The tunable capacitor C is discharged by the resistor R2, and the discharge time is t = R2 * C, so that the voltage _ force of the input terminal 18 is lowered to a low level voltage. When the voltage of the input terminal 18 is lowered to V-, the voltage v〇 of the output terminal 2 of the flip-flop D becomes a high level voltage. Thus, the delay device 100A can delay the rising edge of the input signal % of the signal source 1 (ie, from a low level to a high level), and the rising edge of the output signal Vo depends on the input signal Vi. T = R2, C. The purpose of delaying the rising edge of the input signal Vi is because the capacitance value of the adjustable capacitor C can be adjusted, so the delay 201031119 T=R2*C can also be adjusted, and the external integrated circuit can adjust the delay time period. With this lining, the external integrated circuit can perform an initial ^' circuit on the (10) circuit to ensure that the frequency circuit does not go wrong. The output city VG can also be used as a control signal to control the integrated circuit to perform other specific functions. In addition, by adjusting the size of the DC power source Vcc, the magnitude of the output voltage v〇 of the output terminal 20 of the flip-flop D can be adjusted to meet different requirements. Lu
如圖4所示，其為第二較佳實施方式的延時裴置1〇〇丑的具體 電路圖。該延時裝置1()_於對輸人訊號的上升沿進行延時了延 時裳置100B與延時裝置100A的區別在於可控電源12β的電子開關 在訊號源10提供的輸入訊號的上升沿導通，在輸入訊號的下降 ^截止。在本實施方式中，電子開關126為]^1>1^三極體 如此，訊號源10提供的輸入訊號的下降沿被延時，且該延時 時間段可調節。糊該延時時間段，外籠體電路可及時保存其 正在運行的程式’避免積體電路的資料丟失。另外，輸出訊躲 可作為控制訊號來控制積體電路完成特定功能。 综上所述，本發明符合發明專利要件，爰依法提出專 利申明。惟，以上所述僅為本發明之較佳實施方式，舉凡 熟悉本案技藝之人士，在援依本案創作精神所作之等效修 飾或變化，皆應包含於以下之申請專利範圍内。 【圖式簡單說明】 圖1為一較佳實施方式的延時裝置的功能模組圖。 圖2為圖1中延時裝置的第一較佳實施方式的具體電路圖。 圖3為圖2中延時裝置產生的相關電訊號的波形示意圖。 圖4為圖1中延時裝置的第二較佳實施方式的具體電路圖。 7 ,201031119 【主要元件符號說明】 訊號源 10 可控電源 12、12A、12B 電阻 Rl、R2 延時裝置 100、100A、 100B 電子開關 14A, 14B 直流電源 Vcc 可調電容 C 延時單元 15 輸入端 18 訊號產生單元 16 輸出端 20 第一埠 22 第二埠 24 施密特觸發器 D 電壓 Va 輸出訊號 Vo 輸入訊號 Vi 正向閾值電壓 V+ 負向閾值電壓 V- 時間 τ 三極體 Ql、Q2As shown in FIG. 4, it is a specific circuit diagram of the delay device of the second preferred embodiment. The delay device 1()_ delays the rising edge of the input signal. The difference between the delay setting 100B and the delay device 100A is that the electronic switch of the controllable power supply 12β is turned on at the rising edge of the input signal provided by the signal source 10, The input signal drops ^ cutoff. In the present embodiment, the electronic switch 126 is a ^1>1^triode. Thus, the falling edge of the input signal provided by the signal source 10 is delayed, and the delay period can be adjusted. For the delay period, the outer cage circuit can save its running program in time to avoid data loss of the integrated circuit. In addition, the output signal can be used as a control signal to control the integrated circuit to perform specific functions. In summary, the present invention complies with the requirements of the invention patent, and proposes a patent declaration according to law. However, the above description is only the preferred embodiment of the present invention. Any person who is familiar with the art of the present invention, equivalent modifications or variations in the spirit of the present invention should be included in the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram of a delay device according to a preferred embodiment. 2 is a detailed circuit diagram of a first preferred embodiment of the delay device of FIG. 1. 3 is a waveform diagram of related electrical signals generated by the delay device of FIG. 2. 4 is a detailed circuit diagram of a second preferred embodiment of the delay device of FIG. 1. 7 , 201031119 [Main component symbol description ] Signal source 10 Controllable power supply 12, 12A, 12B Resistor Rl, R2 Delay device 100, 100A, 100B Electronic switch 14A, 14B DC power supply Vcc Adjustable capacitor C Delay unit 15 Input terminal 18 Signal Generation unit 16 Output terminal 20 First 埠 22 Second 埠 24 Schmitt trigger D Voltage Va Output signal Vo Input signal Vi Forward threshold voltage V+ Negative threshold voltage V- Time τ Triode Ql, Q2