201031036 六、發明說明： 本申請是原申請案號095148928,申請日2006年12月 26曰，發明名稱為「具有將各發光單元彼此隔離的隔離絕緣 層的發光元件以及其製造方法」的分案申請。 【發明所屬之技術領域】 本發明是有關於一種在單一基底上具有多個發光單元 (light emitting cells)的發光元件(light emitting device)，且特 別是有關於一種具有能彼此隔離發光單元的隔離絕緣層 (isolating insulative layer)之發光元件以及一種製造上述發 光元件的方法。 【先前技術】 在一般照明（illumination)的使用上已經開發有在高電 壓與交流電(AC power)下操作的發光元件。這種發光元件 已經被Sakai等人揭露的標題為具有發光要素 (light-emitting elements)的發光元件之專利 2004/023568(Α1)中。 這種發光元件在單一基底上具有數個發光二極體（以 下歸類為發光單元）。發光單元藉由金屬線路以串聯及反向 並聯彼此相連，以使其被直接連接到一高電壓與交流電電 源0 圖1至圖3是描繪習知的一種製造具有多個發光單元 之發光元件的方法的剖面圖，而圖4則是圖2的平面圖。 請參照圖丨’在一個藍寶石（sapphire)基底1〇的一整面 上依序形成一層緩衝層(buffer layer)2〇、一層N型半導體 23016-D-pif 4 201031036 層3〇、:層主動層40和一層P型半導體層5〇。 +接著，明參照圖2 ’使用微影與蝕刻製程圖案化上述p ^、導體層50、主動層40、N型半導體層3〇與緩衝層 以便彼此隔離多個發光單元區域（Ught emitting cell regions)。然後’姓刻部分的p型半導體層％和主動層仙， 以露出如圖示虛線部分的N型半導體層3〇。因此，如圖4 ，不，會露出部分的N型半導體層3G並且在基底上形成 ❿ 夕個被溝渠電性隔離的發光單元。 請再度參照圖3’在P型半導體層5〇上形成一層透明 電極層(transparent electrode layer)60。某一發光單元的透明 電極層60經由一條導電線路(conductive wiring)70被連接 到與其相鄰的另一發光單元之露出的N型半導體層3〇。 w經由上述導電線路’在基底10上提供串聯的發光 單兀陣列並且彼此反向並聯，以便提供可在交流電電源下 操作的發光元件。 φ “然而’因為習知在製作發光元件之方法中圖案化p型 半導體層50、主動層4〇、N型半導體層30與緩衝層20， 所以會在發光單元之間形成深溝渠(deep trenches)。因此， 在溝渠中很容易殘留顆粒，而且形成彼此連接發光單元的 線路之製程是困難的。由於顆粒的關係，所以在發光單元 之間會發生漏電流(current leakage)。這種漏電流會降低發 光效率並導致元件故障(failure)。 同時’因為氮化鎵系發光元件（GaN-based light emitting devices)發射短波長光，如藍色或紫外光，所以需 23016-D-pif 5 201031036 要藉著轉換由發光元件發出的光的波長來實現混光(mixed light) ’如白色光，以使發光元件能用於一般照明。特別是 需要在一個晶片平面(chip level)具有一層波長轉換材料層 的發光元件’以簡化封裝製程(packaging processes)。 【發明内容】 「技術問題」 本發明提供一種發光元件，在一個單一基底上具有多 個發光單元並且能夠避免發光單元間的漏電流。 本發明提供一種發光元件’易於形成其十彼此連接發 光單元的線路。 本發明提供一種發光元件，可在一晶片平面發出混光。 「技術解決方法」 本發月提出-種發光元件，具有能彼此隔離數個發光 卓⑽-層隔離絕緣層，以及—種製造發光元件的方法。 二述發光，件包括基底和形成於*底上之數個發光單元。 ^ ^光單70包括下半導體層、位於下半導體層的某一區 半導體層以及位於下半導體層與上轉體層之間 的 。此外，還有―層隔軸緣層填在發光單元之間 =上發光單元。而且’還有數個線路彼此電 此，可提供避免顆粒殘留其中之 元件，並因此防止發光輩开夕心九早疋之間的-種發先 供在料i - Μ發先 間㈣電流。再者，還可提 、 l Β的區軸填滿—層隔離絕緣層的-種發 23016-D-pif 201031036 光元件，以便容易形成上述線路。 上述形成的隔離絕緣層具有和發光單元幾乎相同的高 度。也就是說，隔離絕緣層具有一個幾乎和上半導體層= 頂面-致的頂面。因此’形成在上铸體層和隱絕ς層 上的線路可以被輕易地形成。 在本發明之一實施例中，上述隔離絕緣層是由一層絕 緣層形成的’並由譬如Si〇2或SOG製的。 在本發明之一實施例中，上述隔離絕緣層具有以數個 半導體層堆疊的結構，這些半導體層是藉由數道離子植入 製程反摻雜(counterdoped)的。此外，每一及掾雜沾主道 層是藉由於1015〜1022 i〇ns/cm2之劑量下注入至少二種選自 包括N、0' Fe與V所組成之族群的離子到所述半導體層 而形成的。 同時，可以在發光單元的相應上半導體層上配置透明 電極層（transparent electrode layers)。在此時，每一線路會 通過上述透明電極層電性連接至上半導體層。 在本發明之一實施例中，上述發光元件還包括含磷光 體（phosphors)的一層波長轉換材料層（wavelength conversion material layer)。上述波長轉換材料層覆蓋發光 單元以及隔離絕緣層。因此’提供能夠在一晶片平面實現 如白色光的混光的一種發光元件。 本發明另提出一種製造發光元件的方法，包括在一個 基底上形成一層下半導體層、一層主動層和一層上半導體 層。然後’形成一層隔離絕緣層，以彼此隔離數個發光單 23016-D-pif 7 201031036 ^域。接著’在相應的發光單元區域中暴露一部分的下 層，以形成數個發光單元。之後，以線路彼此電性 發光單元。每一線路連接其中一個發光單元的下 牛導體層和與其相㈣另—發光單元的上半導體層。 在形成上述線路之前，可在每一發光單元的上半 ft形成i透明電極層。在上半導體層上的透明電極層 被用以均勻分佈電流(current fl〇w)。 包』另：實施例中’上述隔離絕緣層的形成可 體層，以形成彼此隔離上述發光單元 J與:： 其上Sit入上述溝渠之步驟包括在具有溝渠形成 除在上4=:而且，可以使用CMp製程去 可包在括本ft另道一f施例f ’上述隔離絕緣層的形成也 ρ::、上 層上形成數解幕圖案—k rns) &義ώ發光單兀區域。然後，以罩幕 :個：:植入罩幕’在上半導體層與下半導體層中;主入離 子，再去除上述罩幕圖案。 以反可選自包括N、0、F#v所組成之族群， 以反摻雜上述下半導體層、上轉體層與主動層。因此， 可以不用蝕刻緩衝層、下半導體層、主動層與上半導體層 就猎由上述離子植入製程來形成隔離絕緣層。 曰 23〇16-D-pif 8 201031036 、在形成上述線路之後，也可包括形成一層覆蓋發光單 元以及Png離絕緣層的波長轉換材料層。這層波長轉換材料 層含磷光體。 上述波長轉換材料層可以藉由以下步驟形成，首先在 具有發光單元的基底及形成於其上的隔離絕緣層上設置具 有個入口（inlet)的-個蓋子(cap；)，再通過上述入口注入 含磷光體的樹脂(resin)，接著固化上述注入的樹脂。另一 # 方面’波長轉換材料層可以藉由用—層雜樹脂層（㈣ =pe resm layer)覆蓋基底然後固化上述膠狀細旨層而形 成。此外，波長轉換材料層還可以藉由利用一種喷霧製程， 在基底上供應樹脂與奈米級磷光體(_ sized phosphors) 而形成。 7 「有利的效力」 發：，提供一種發光元件，其中有形成於發光 早疋之間的一層隔離絕緣層，以避免在單-基底上發光單 =間的漏電流。而且，上述隔離絕緣層還可促進線路的 _形^上述發光單元可藉由所述線路彼此電性相連。同時， =發光單元以及隔離絕緣層上形成有一層含磷光體的 j轉換材料層’所以可以提供在一晶片平 光的一種發光元件。 扣色 為讓本發明之上述特徵和優點能更明顯易懂 ，較佳實關，魏麵_式 綱 文特 【實施方式】 下 U下將使用_料盡贿本發明之數個實施例 23016-D-pif 201031036 列實施例只是被提供來作說明的目的，以使本發明所屬技 術領域中具有通常知識者可以完全瞭解本發明之精神。因 此’本發明未被限制在下列實施例，而可以其它形式實現。 在這些附圖中，元件(elements)之寬度、長度、厚度與同樣 的元件為了能夠方便說明所以可被誇大顯示。相同的元件 符號在整篇說明書與圖式中代表相同的元件。 圖5和圖6分別是依照本發明之一實施例的一種具有 能彼此隔離數個發光單元(light emitting cells)的一層隔離 絕緣層（isolating insulative layer)之發光元件(light emitting device)的剖面圖與平面圖。 請參照圖5和圖6 ’多個發光單元i〇〇a與i〇〇b被形 成在一個基底110上。每個發光單元1〇〇a與1〇〇b包括一 層N型半導體層130、形成在部分n型半導體層130上的 一層主動層140和形成在主動層HO上的一層p型半導體 層150。此外’在基底no和個別的發光單元1〇〇a、1〇〇b 之間插入緩衝層(bufferlayers)120。雖然緩衝層120在圖5 中顯示彼此被隔離，但是本發明並不限於此。也就是說， 在某些情況下，當緩衝層是高電阻(high_resistance)層或者 絕緣層，則緩衝層120可以是彼此連續的。而且，可以在 P型半導體層150上形成一層透明電極層（transparem electrode layer) 160。同時’發光單元1〇〇a與1〇〇b之間的 區域被一層隔離絕緣層200填滿，以使相鄰的發光單元彼 此隔離。隔離絕緣層200可以被形成為具有幾乎和發光單 元100a與l〇〇b相同的高度。 23016-D-pif 10 201031036 另外，在發光單元與隔離絕緣層200上形成有數條線 路(wirings)170 ’以彼此電性連接發光單元4一線路170 連接其中-個發光單元100b的N型半導體層13〇和與發 光單元100b相鄰的另一發光單元100a的透明電極層 160，以使發光單元彼此電性連接。 此外，在發光單元100a、100b與隔離絕緣層200上可 覆蓋一層波長轉換材料層（wavelength conversion material 馨 layer)180。這層波長轉換材料層18〇包含磷光體 (phosphors)，以使從發光單元發出的至少一部分的光能夠 被轉換波長。因此，可在一晶片平面上實現具有各種波長 的光與如白色光之混光。 這時，基底110可以是一個絕緣或導體基底。在基底 110是一個導體基底的情況下’使用緩衝層120或其它絕 緣層（未繪示）來電性絕緣基底110和發光單元100a與 100b。再者，用緩衝層120來避免導因於基底110和N型 半導體層130之間的晶格失配(lattice mismatch)之缺陷發 ❹ 生。 N型半導體層130是一種摻雜N型雜質(impurities)的 半導體層。N型半導體層可以是氮化鎵系化合物半導體層 (GaN-based compound semiconductor layer)，但是本發明並 不限於此。亦即，可使用多種半導體層。而且，N型半導 體層130也可包括一層N型包覆層（clad layer)。另一方面， P型半導體層150是一種摻雜P型雜質的半導體層。P型 半導體層可以是氮化鎵系化合物半導體層，但是本發明並 23016-D-pif 201031036 不限於此。換句話說，可使用多種半導體層。而且’ p型 半導體層150也可包括一層p型包覆層。 每一 N型與p型半導體層130和150可被形成為包含 至少兩層的一種多層膜(nmltilayer film)。在以氣化嫁系化 合物半導體層形成N型與P型半導體層的情況下，可分別 使用矽(Si)與鎂(Mg)雜質。不過，本發明並不限於此。亦 即’可使用多種類之雜質。 主動層140可以是具有單一量子井(quantum well)層的 一個單一量子井結構或是一個在其中由量子井層與緩衝層 重複形成之多量子井結構。同時，根據組成主動層的材料 之種類，發出的光之波長會改變。每一緩衝層與井層可以 是由AlJriyGanyN (〇Sx+ySl)形成的。在此同時，緩衝層 可由一種具備比井層的帶隙(band gap)更大的材料所形 成。雖然每一緩衝層與井層可以不用摻雜雜質，但是本發 明並不限於此。亦即，可在每一緩衝層與井層摻雜雜質。 使用透明電極層160可以使P型半導體層150上的電 流分布(current spreading)—致。而銦錫氧化物(indium tin oxide，ITO)或鎳/金可被用作透明電極層。 隔離絕緣層200則可彼此電性絕緣形成在基底U〇上 的發光單元100a與100b並且也可避免發光單元i〇〇a與 100b之間的區域中有顆粒殘留。 在本發明的某些實施例中，隔離絕緣層200是由一層 透明的絕緣層形成的，如Si〇2膜或旋塗式玻璃(Spin on Glass，SOG)。 23016-D-pif 12 201031036 在本發明的其他實施例中，隔離絕緣層200可具有以 數個半導體層堆疊的結構，這些半導體層是藉由數&離子 植入製程反摻雜(counter doped)的。換句話說，隔離絕緣層 200可以具有—種結構，這種結構中有被轉換成高電阻層 或絕緣層的形成於基底110上之緩衝層120、N型半導體 層130、主動層140和P型半導體層15〇，而上述各層是 被植入相反摻雜離子(counter doping 。 • ^線路170是被形成來電性連接上述彼此電性隔離的發 光單元100a與100b。此時，每一線路17〇是由金屬材料 形成，如銀(Ag)、銅(Cu)、鋁(A1)、鎢(w)或鈦(Ti)，但是 本發明並不限於此。亦即，線路可使用如多晶矽的一種半 導體材料形成。 雖然在本發明的上述實施例中已經描述N型與p型半 導體層130和150是分別配置在發光元件的下部與上部， 但是本發明並不限於此。換句話說，P型與N型半導體層 150和130也可分別配置在發光元件的下部與上部。 ❿ 圖7至圖10是依照本發明之一實施例的一種製造發光 元件的方法的剖面圖。 請參照圖7，在一個基底110上形成一層半導體 層130、一層主動層14〇和一層p型半導體層15〇。基底 110 可以疋一種 Al2〇3、Sic、ZnO、Si、GaAs、GaP、LiAl2〇3、 BN、AIN或GaN基底。基底可以是一種絕緣或導體基底。 此外，每一 N型半導體層130、主動層140和P型半導體 層150可以用有機金屬化學氣相沉積法(M0CVD)或分子 23016-D-pif 13 201031036 ^晶(臟)製程來形成如氮化㈣化 在n型半導體層no形成夕今π 千导體丨m 緩衝層m例如可由一 =成;:層緩衝層。這種 如⑽、Α1Ν或隨。氮化111族化合物半導體形成， 於8 ’使用微影與蝕刻製程圖案化形成 ==半導體層、主動層與上半導體層，以形 離多個發光單元區域的—個溝渠155。結果，可 也可與上述各層一起被域。在此同時’緩衝層- 彼入ri明參照圖9 ’溝渠155被以一層隔離絕緣層200 4奶乂、絕緣層細可以是—種透明的絕緣材料，如Si〇2 或！SGG 〇 f使用SQG填人溝渠的情形中，可在觸〜_啊 ^速下持續5至60秒旋轉塗佈上述SOG。所以，SOG =均勻地塗在基底11G上，並在溝渠155中填入。 ®在1〇〜3〇0 C約20至200秒固化所述SOG，以形 ^層S〇G膜。塗佈製程與固化SOG的步驟可重複執行 人。因此，可避免在溝渠155中形成孔洞(v〇ids)。此外， G膜不只被形成在溝渠155中，也會形成在p型半導體 的购。所以可使用cmp製程或整面_刻製程 米去除形成在P型半導體層150上的SOG膜。 隨後’請參照圖10，使用微影與钱刻製程去除每一發 中的部份P型半導體層15〇與主動層14〇，以露出 縣的N型半導體層130。所以，在基底110上形成了 23016-D-pif 201031036 多個由隔離絕緣層2GG相互隔離之發光單元。 接著在P型半導體層150上形成-層透明電極層 160。可使用一種剝離製程_-〇汗process)形成ITO或 Ni/Au製的透明電極層16〇。 4 -然後’形成用來連接發光單元之線路17〇(如圖$ 不）’以f此電性連接發光單元。線路17〇可藉由一種步進 式覆蓋製程(steP-coverprocess)形成。也就是說，在發光 • 元與隔離絕緣層200上形成一層光阻層，以露出發光單元 與隔離絕緣層2GG將形成線路的區域。之後，利用一道 鑛或沉積製程沉積-種導電材料，再去除上述光阻層。結 果，形^ 了用來連接發光單元100a與1〇〇b之線路17〇 “接著，在有線路Π0形成其上的基底上形成一層含磷 光體的波長轉換材料層180(如圖5所示）。上述波長轉換材 =層180可以藉由供應一種含磷光體的透明材料如環氧樹 月曰或矽氧烷樹脂(silicone resin)來覆蓋發光單元。可藉由一 種製模(molding)或噴霧製程(spraying process)供應上述透 讎明材料。此外，波長轉換材料層18〇的形成也可在具有線 路170形成於其上的基底11〇上放置具有一個入口 的一個蓋子(cap) ’再將含磷光體的樹脂注入上述入口，接 著固化上述樹脂。 在這個實施例中，N型和P型半導體層13〇與150可 以彼此易位。而且，透明電極層16〇可以在露出N型半導 體層130之前形成。 同時’線路170也可使用一種空橋製程(air_bridge 23016-D-pif 201031036 p:=s)形成。圖η是適跡本發明之料㈣例的一種 形成上橋線路(air_bridge wirings)的方法的剖面圖。 參照圖11，在具有發光單元形成於其上的基底11〇 上供應一種光阻，再經由一道微影製程形 圖案，其暴露出-個發光單元100a(如圖5所示)的一層ν 型半導體層13G之-健_及與發光單元驗相鄰的另 一發光單元io〇b的一層透明電極層16〇之一部分。隨後， 形成-層第-金屬膜，以便使露出的N型半輕層13〇和 透明電極層_彼此電性連接。然後，在第—光阻圖案上 形成一個第二光阻圖案》第二光阻圖案具有多個開口 (openings) ’每一開口露出一個將有線路形成的區域，且透 過這些開口暴露出第-金屬膜。接著，在第二光阻圖案上 形成-層第二金屬膜。這層第二金屬膜是使用第—金屬膜 作為晶種(seed)形成的。之後，去除第一與第二光阻圖案， 以保留連接發光單元的線路17〇。 ' 然後，可在有線路170形成於其上的基底n〇上形成 一層波長轉換材料層。 圖12與圖13是依照本發明之另一實施例的發光元件 的剖面圖。 请參照圖12，與圖7所描述的有關，在一個基底11〇 上形成一層緩衝層120、一層ν型半導體層130、一層主 動層140和一層P型半導體層15〇。然後，在p型半導體 層150上形成定義出發光單元區域的罩幕圖案(mask patterns)210 〇 23016-D-pif 16 201031036 罩幕圖案2HH列如可由氧化石夕(smc〇n 〇χ_或氮化碎 ㈣coiinitride)形成。亦即，可在p型半導體層15〇上形成 由氧化石夕、氮化石夕或其相似者所製的一層罩幕層，再用微 影與钱刻製程來圖案化上述罩幕層，以使罩幕圖案21〇被 分別形成於各個發光單元區域上。 —接著，清參照圖13，以上述罩幕圖案21〇作為罩幕， 藉由道離子植入製程(i〇n impla⑽U〇n pr〇cess)注入離子 參 =0。、因此’罩幕圖案能避免離子被植人發光單元區 、’並因此將離子植人鄰近發光單元區域的半導體層。離 子可被植入P型半導體層150、主動層140、N型半導體層 130和緩衝層12〇。在此同時，為了能讓各個半導體層12〇 至150被反摻雜’可藉由調整Rp數次來將離子植入半導 體層中時’所述反掺雜是用來將一層導電半導體層轉 換成一層高，阻或絕緣半導體層。因此，在緩衝層120或 主動層U0疋-層絕緣層的情況下所述反掺雜可以被限 術生地貝行於N型和P型半導體層130與150上。並且， 為確保相鄰的發光單元之間電性絕緣（electrical insulation) ’可將離子植入基底的上部區域(卿⑽）。 上述離子例如可選自N、Q、Fe與V之中，並且於10 至10=00 KeV的離子植入能量範圍内以1〇15〜1〇22— 之劑量下植入離子。之後，移除罩幕圖 案 210。 如圖10所描述，露出N型半導體層ι3〇的一個區域、 形成層+透明電極層16〇,再形成線路170(如圖5或11所 ㈣。接著’在有線路17〇形成其上的基底110上形成-層 23016-D-pif 17 201031036 波長轉換材料層18〇。 依據本發明的這個實施例，因為是經由一道離子植入 製程形成一層隔離絕緣層2〇〇,並未蝕刻緩衝層12〇、\型 半導體層130、主動層140和P型半導體層15〇 ^ 避免因為飯刻製程所造成的傷害。201031036 VI. INSTRUCTIONS: This application is the original application No. 095148928, the application date is December 26, 2006, and the invention is entitled "Light-emitting element with isolation insulating layer separating each light-emitting unit from each other and its manufacturing method" Application. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a light emitting device having a plurality of light emitting cells on a single substrate, and more particularly to an isolation having a light emitting unit that can be isolated from each other. A light-emitting element of an isolating insulative layer and a method of manufacturing the above-described light-emitting element. [Prior Art] A light-emitting element that operates under high voltage and alternating current (AC power) has been developed for use in general illumination. Such a light-emitting element has been disclosed in Sakai et al., which is entitled to a light-emitting element having light-emitting elements, in 2004/023568 (Α1). Such a light-emitting element has a plurality of light-emitting diodes (hereinafter classified as light-emitting units) on a single substrate. The light-emitting units are connected to each other in series and in reverse by a metal line so as to be directly connected to a high voltage and alternating current power source. FIG. 1 to FIG. 3 are diagrams depicting a conventional light-emitting element having a plurality of light-emitting units. A cross-sectional view of the method, and Figure 4 is a plan view of Figure 2. Please refer to the figure 丨 'on a whole surface of a sapphire substrate 1 形成 a buffer layer 2 〇, a layer of N-type semiconductor 23016-D-pif 4 201031036 layer 3 〇, layer active Layer 40 and a layer of P-type semiconductor layer 5 are. + Next, the above p ^, the conductor layer 50, the active layer 40, the N-type semiconductor layer 3 and the buffer layer are patterned using a lithography and etching process to separate the plurality of light-emitting unit regions from each other (Ught-emitting cell regions). ). Then, the p-type semiconductor layer % and the active layer are partially engraved to expose the N-type semiconductor layer 3 如 as shown by the broken line portion. Therefore, as shown in Fig. 4, no part of the N-type semiconductor layer 3G is exposed and a light-emitting unit electrically isolated by the trench is formed on the substrate. Referring to Fig. 3' again, a transparent electrode layer 60 is formed on the P-type semiconductor layer 5?. The transparent electrode layer 60 of a certain light-emitting unit is connected to the exposed N-type semiconductor layer 3 of another light-emitting unit adjacent thereto via a conductive wiring 70. w provides a series of light-emitting single-turn arrays on the substrate 10 via the above-described conductive lines' and is connected in anti-parallel with each other to provide a light-emitting element that can be operated under an alternating current power source. φ "However" because the p-type semiconductor layer 50, the active layer 4, the N-type semiconductor layer 30 and the buffer layer 20 are patterned in the method of fabricating the light-emitting elements, deep trenches are formed between the light-emitting units. Therefore, it is easy to leave particles in the trench, and the process of forming the lines connecting the light-emitting units to each other is difficult. Due to the relationship of the particles, current leakage occurs between the light-emitting units. It will reduce the luminous efficiency and cause component failure. At the same time, 'Because GaN-based light emitting devices emit short-wavelength light, such as blue or ultraviolet light, 23016-D-pif 5 201031036 is required. The mixed light 'such as white light is realized by converting the wavelength of the light emitted by the light-emitting element so that the light-emitting element can be used for general illumination. In particular, it is required to have a wavelength conversion at a chip level. The light-emitting element of the material layer simplifies the packaging process. [Technical Problem] The present invention provides a light-emitting element, Having a plurality of light emitting cells on a single substrate and to avoid leak current between light emitting cells. The present invention provides a light-emitting element' that is easy to form a line in which ten light-emitting units are connected to each other. The present invention provides a light-emitting element that emits light on a wafer plane. "Technical Solution" A light-emitting element has been proposed in the present month, and has a plurality of light-emitting (10)-layer insulating layers which can be isolated from each other, and a method of manufacturing a light-emitting element. The light emission includes a substrate and a plurality of light emitting units formed on the bottom of the substrate. The optical sheet 70 includes a lower semiconductor layer, a semiconductor layer located in a lower semiconductor layer, and a lower semiconductor layer and an upper rotating layer. In addition, there is also a "layered edge layer" between the light-emitting units = upper light-emitting unit. Moreover, there are a number of lines that are electrically connected to each other, which can provide elements that avoid particles remaining therein, and thus prevent the first generation of electricity between the first and the second. Furthermore, the area axis of the Β 填 填 填 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 The above-described isolation insulating layer has almost the same height as the light-emitting unit. That is, the isolation insulating layer has a top surface which is almost the same as the upper semiconductor layer = top surface. Therefore, the lines formed on the upper cast layer and the hidden layer can be easily formed. In one embodiment of the invention, the isolating insulating layer is formed of a layer of insulating layer and is made of, for example, Si 2 or SOG. In one embodiment of the invention, the isolation insulating layer has a structure in which a plurality of semiconductor layers are stacked, which are counterdoped by a plurality of ion implantation processes. In addition, each of the doped and doped layers is implanted into the semiconductor layer by implanting at least two ions selected from the group consisting of N, 0' Fe and V at a dose of 1015 to 1022 i〇ns/cm 2 . And formed. At the same time, transparent electrode layers can be disposed on the respective upper semiconductor layers of the light emitting unit. At this time, each line is electrically connected to the upper semiconductor layer through the above transparent electrode layer. In an embodiment of the invention, the light-emitting element further comprises a layer of a wavelength conversion material layer containing phosphors. The wavelength conversion material layer covers the light emitting unit and the isolation insulating layer. Therefore, a light-emitting element capable of realizing light mixing such as white light on a wafer plane is provided. The present invention further provides a method of fabricating a light-emitting element comprising forming a lower semiconductor layer, an active layer and an upper semiconductor layer on a substrate. Then, a layer of isolation insulating layer is formed to isolate a plurality of light-emitting sheets 23016-D-pif 7 201031036 ^ domains from each other. A portion of the lower layer is then exposed in the corresponding light emitting cell region to form a plurality of light emitting cells. Thereafter, the lines are electrically illuminated from each other. Each line connects the lower conductor layer of one of the light-emitting units and the upper semiconductor layer of the other (four) other-light-emitting unit. The i transparent electrode layer may be formed in the upper half of each of the light emitting units before forming the above wiring. A transparent electrode layer on the upper semiconductor layer is used to uniformly distribute current (current fl〇w). Package: In the embodiment, the above-mentioned isolation insulating layer is formed into a body layer to form the above-mentioned light-emitting unit J and the following: the step of inserting the Sit into the above-mentioned trench includes the formation of the trench except for the above 4=: The CMp process can be used to include the above-mentioned isolation insulating layer, and the formation of the above-mentioned isolation insulating layer is also ρ::, the upper layer forms a number of curtain patterns - k rns) & Then, the mask is used to: implant the mask in the upper semiconductor layer and the lower semiconductor layer; the main ion is introduced, and the mask pattern is removed. The lower semiconductor layer, the upper rotating layer and the active layer are back-doped with a group selected from the group consisting of N, 0, and F#v. Therefore, the isolation insulating layer can be formed by the above ion implantation process without etching the buffer layer, the lower semiconductor layer, the active layer and the upper semiconductor layer.曰 23〇16-D-pif 8 201031036, after forming the above-mentioned lines, may also include forming a layer of wavelength converting material covering the light-emitting unit and Png away from the insulating layer. This layer of wavelength converting material contains phosphor. The above-mentioned wavelength conversion material layer can be formed by first providing a cap having an inlet on the substrate having the light-emitting unit and the isolation insulating layer formed thereon, and then injecting through the above-mentioned inlet A phosphor-containing resin, followed by curing the above-described injected resin. Another # ′′ wavelength conversion material layer can be formed by covering the substrate with a layer of a resin layer and then curing the above gelatinous layer. Further, the wavelength converting material layer can also be formed by supplying a resin and a _ sized phosphors on a substrate by using a spraying process. 7 "Beneficial Effectiveness" Hair: A light-emitting element is provided in which an insulating layer is formed between the light-emitting layers to avoid leakage current between the single-substrate. Moreover, the above-mentioned isolation insulating layer can also promote the wiring of the above-mentioned light-emitting units to be electrically connected to each other by the lines. At the same time, a light-emitting unit and a layer of phosphor-containing j-switching material are formed on the isolation insulating layer, so that a light-emitting element which is flat on a wafer can be provided. The color change is to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, and to be better, the Wei _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The -D-pif 201031036 column embodiment is provided for illustrative purposes only, so that those skilled in the art to which the invention pertains can fully understand the spirit of the invention. Therefore, the present invention is not limited to the following embodiments, but may be embodied in other forms. In the drawings, the width, length, thickness, and the same elements of the elements may be exaggerated for convenience of explanation. Identical component symbols represent the same components throughout the specification and drawings. 5 and 6 are cross-sectional views of a light emitting device having an isolating insulative layer capable of isolating a plurality of light emitting cells from each other, in accordance with an embodiment of the present invention, respectively. With a floor plan. Referring to Figures 5 and 6, a plurality of light-emitting units i 〇〇 a and i 〇〇 b are formed on a substrate 110. Each of the light-emitting units 1a and 1B includes a layer of the N-type semiconductor layer 130, an active layer 140 formed on the portion of the n-type semiconductor layer 130, and a p-type semiconductor layer 150 formed on the active layer HO. Further, buffer layers 120 are inserted between the substrate no and the individual light-emitting units 1a, 1B. Although the buffer layers 120 are shown isolated from each other in FIG. 5, the present invention is not limited thereto. That is, in some cases, when the buffer layer is a high-resistance layer or an insulating layer, the buffer layers 120 may be continuous with each other. Moreover, a transparent electrode layer 160 may be formed on the P-type semiconductor layer 150. At the same time, the area between the light-emitting units 1a and 1B is filled with a layer of isolation insulating layer 200 to isolate adjacent light-emitting units from each other. The isolation insulating layer 200 may be formed to have almost the same height as the light-emitting units 100a and 100b. 23016-D-pif 10 201031036 In addition, a plurality of wirings 170' are formed on the light-emitting unit and the isolation insulating layer 200 to electrically connect the light-emitting units 4 to one line 170 to connect the N-type semiconductor layers of the light-emitting units 100b. 13〇 and the transparent electrode layer 160 of the other light emitting unit 100a adjacent to the light emitting unit 100b to electrically connect the light emitting units to each other. Further, a layer of wavelength conversion material layer 180 may be coated on the light emitting units 100a, 100b and the isolation insulating layer 200. The layer of wavelength converting material 18 〇 contains phosphors such that at least a portion of the light emitted from the light emitting unit can be converted to a wavelength. Therefore, light having various wavelengths and mixed light such as white light can be realized on a wafer plane. At this time, the substrate 110 may be an insulating or conductor substrate. In the case where the substrate 110 is a conductor substrate, the buffer layer 120 or other insulating layer (not shown) is used to electrically insulate the substrate 110 and the light-emitting units 100a and 100b. Furthermore, the buffer layer 120 is used to avoid defects caused by lattice mismatch between the substrate 110 and the N-type semiconductor layer 130. The N-type semiconductor layer 130 is a semiconductor layer doped with N-type impurities. The N-type semiconductor layer may be a GaN-based compound semiconductor layer, but the present invention is not limited thereto. That is, a plurality of semiconductor layers can be used. Moreover, the N-type semiconductor layer 130 may also include an N-type clad layer. On the other hand, the P-type semiconductor layer 150 is a semiconductor layer doped with a P-type impurity. The P-type semiconductor layer may be a gallium nitride-based compound semiconductor layer, but the present invention 23016-D-pif 201031036 is not limited thereto. In other words, a variety of semiconductor layers can be used. Further, the 'p-type semiconductor layer 150' may also include a p-type cladding layer. Each of the N-type and p-type semiconductor layers 130 and 150 may be formed as a multilayer film (at least two layers). In the case where the N-type and P-type semiconductor layers are formed by vaporizing the graft compound semiconductor layer, bismuth (Si) and magnesium (Mg) impurities may be used, respectively. However, the invention is not limited thereto. That is, a variety of impurities can be used. The active layer 140 can be a single quantum well structure having a single quantum well layer or a multiple quantum well structure in which the quantum well layer and the buffer layer are repeatedly formed. At the same time, the wavelength of the emitted light changes depending on the kind of material constituting the active layer. Each buffer layer and well layer may be formed of AlJriyGanyN (〇Sx+ySl). At the same time, the buffer layer may be formed of a material having a larger band gap than the well layer. Although each of the buffer layer and the well layer may not be doped with impurities, the present invention is not limited thereto. That is, impurities may be doped into each buffer layer and the well layer. The use of the transparent electrode layer 160 allows current spreading on the P-type semiconductor layer 150. Indium tin oxide (ITO) or nickel/gold can be used as the transparent electrode layer. The isolating insulating layer 200 is then electrically insulated from each other to form the light emitting cells 100a and 100b on the substrate U, and also to prevent particle residue in the region between the light emitting cells i〇〇a and 100b. In some embodiments of the invention, the isolating insulating layer 200 is formed from a layer of transparent insulating layer, such as a Si 2 film or a spin on glass (SOG). 23016-D-pif 12 201031036 In other embodiments of the present invention, the isolation insulating layer 200 may have a structure in which a plurality of semiconductor layers are stacked by counter doping (counter doped by a number & ion implantation process) )of. In other words, the isolation insulating layer 200 may have a structure in which the buffer layer 120, the N-type semiconductor layer 130, the active layer 140, and the P formed on the substrate 110 are converted into a high resistance layer or an insulating layer. The semiconductor layer 15 is formed, and the above layers are implanted with opposite doping ions (counter doping. • The line 170 is formed by electrically connecting the above-described light-emitting units 100a and 100b electrically isolated from each other. At this time, each line 17 The crucible is formed of a metal material such as silver (Ag), copper (Cu), aluminum (A1), tungsten (w) or titanium (Ti), but the present invention is not limited thereto. That is, the wiring may be used as a polycrystalline crucible. A semiconductor material is formed. Although the N-type and p-type semiconductor layers 130 and 150 have been respectively disposed at the lower and upper portions of the light-emitting element in the above-described embodiments of the present invention, the present invention is not limited thereto. In other words, P The type and N-type semiconductor layers 150 and 130 may also be disposed at the lower and upper portions of the light-emitting element, respectively. ❿ Figures 7 to 10 are cross-sectional views showing a method of fabricating a light-emitting element according to an embodiment of the present invention. On a substrate 110 A semiconductor layer 130, an active layer 14A and a p-type semiconductor layer 15 are formed thereon. The substrate 110 may be an Al2〇3, Sic, ZnO, Si, GaAs, GaP, LiAl2〇3, BN, AIN or GaN substrate. The substrate may be an insulating or conductor substrate. Further, each of the N-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 150 may be formed by metalorganic chemical vapor deposition (M0CVD) or molecules 23016-D-pif 13 201031036. ^ Crystal (dirty) process to form, for example, nitridation in the n-type semiconductor layer no formation of the π thousand conductor 丨m buffer layer m, for example, can be a =; layer buffer layer. Such as (10), Α 1 Ν or The nitrided group 111 compound semiconductor is formed by patterning using a lithography and etching process to form a == semiconductor layer, an active layer and an upper semiconductor layer to form a trench 155 that is separated from the plurality of light emitting cell regions. As a result, It can also be domaind together with the above layers. At the same time, the 'buffer layer - the same as the one shown in FIG. 9 'the trench 155 is insulated by a layer of insulating layer 200 4 , the insulating layer can be a transparent insulating material, such as Si〇2 or !SGG 〇f uses SQG to fill the ditch In the case of the above, the SOG can be spin-coated at a speed of 5 to 60 seconds. Therefore, SOG = uniformly applied to the substrate 11G and filled in the trench 155. ® at 1 〇 3 The SOG is cured by 〇0 C for about 20 to 200 seconds to form a layer of S 〇 G film. The coating process and the step of solidifying the SOG can be repeated. Therefore, holes (v〇ids) can be avoided in the trench 155. Further, the G film is formed not only in the trench 155 but also in the p-type semiconductor. Therefore, the SOG film formed on the P-type semiconductor layer 150 can be removed using a cmp process or a full-surface process. Subsequently, referring to Fig. 10, a portion of the P-type semiconductor layer 15A and the active layer 14A in each of the marks are removed by using a lithography and etching process to expose the N-type semiconductor layer 130 of the county. Therefore, 23016-D-pif 201031036 is formed on the substrate 110 with a plurality of light-emitting units separated from each other by the isolation insulating layer 2GG. Next, a -layer transparent electrode layer 160 is formed on the P-type semiconductor layer 150. A transparent electrode layer 16A made of ITO or Ni/Au can be formed using a lift-off process. 4 - then 'forming a line 17 用来 (as shown in Fig. No) for connecting the light-emitting unit to electrically connect the light-emitting unit. Line 17 can be formed by a step-covering process (steP-cover process). That is, a photoresist layer is formed on the light-emitting element and the isolation insulating layer 200 to expose a region where the light-emitting unit and the isolation insulating layer 2GG will form a line. Thereafter, a conductive material is deposited using a mineral or deposition process, and the photoresist layer is removed. As a result, a line 17 for connecting the light-emitting units 100a and 1b is formed. "Next, a phosphor-containing wavelength conversion material layer 180 is formed on the substrate on which the line Π0 is formed (as shown in FIG. 5). The above wavelength converting material=layer 180 may cover the light emitting unit by supplying a phosphor-containing transparent material such as epoxy resin or silicone resin. It may be molded by a molding or A spray processing process supplies the above-described transparent material. Further, the wavelength conversion material layer 18 is formed by placing a cap having an inlet on the substrate 11 having the line 170 formed thereon. A phosphor-containing resin is injected into the above-mentioned inlet, followed by curing of the above resin. In this embodiment, the N-type and P-type semiconductor layers 13 and 150 may be translocated to each other. Moreover, the transparent electrode layer 16 may expose the N-type semiconductor. Layer 130 is formed before. At the same time, 'line 170 can also be formed using an empty bridge process (air_bridge 23016-D-pif 201031036 p:=s). Figure η is an example of the material of the invention (4) forming an upper bridge line (air_br A cross-sectional view of the method of idge wirings. Referring to Fig. 11, a photoresist is supplied on a substrate 11 having a light-emitting unit formed thereon, and then exposed to a light-emitting unit 100a via a lithography process pattern (e.g. Figure 5 shows a portion of a layer of the v-type semiconductor layer 13G and a portion of the transparent electrode layer 16 of another light-emitting unit io〇b adjacent to the light-emitting unit. Subsequently, a layer-first metal film is formed. So that the exposed N-type semi-light layer 13 and the transparent electrode layer are electrically connected to each other. Then, a second photoresist pattern is formed on the first photoresist pattern. The second photoresist pattern has a plurality of openings (openings) Each opening exposes a region where a line will be formed, and the first metal film is exposed through the openings. Then, a second metal film is formed on the second photoresist pattern. This second metal film is used. The first metal film is formed as a seed. Thereafter, the first and second photoresist patterns are removed to retain the line 17A connected to the light emitting unit. ' Then, the substrate n on which the line 170 is formed may be Forming a layer of wavelength conversion material on the crucible Figure 12 and Figure 13 are cross-sectional views of a light-emitting element in accordance with another embodiment of the present invention. Referring to Figure 12, in relation to Figure 7, a buffer layer 120, a layer is formed on a substrate 11A. A ν-type semiconductor layer 130, an active layer 140, and a P-type semiconductor layer 15A. Then, mask patterns 210 〇23016-D-pif 16 defining a region of the illuminating unit are formed on the p-type semiconductor layer 150. 201031036 The mask pattern 2HH column can be formed by oxidized stone (smc〇n 〇χ_ or nitrided (four) coiinitride). That is, a mask layer made of oxidized stone, nitrite or the like may be formed on the p-type semiconductor layer 15 ,, and the mask layer may be patterned by a lithography and etching process to The mask patterns 21 are formed on the respective light emitting unit regions, respectively. - Next, referring to Fig. 13, the mask pattern 21 is used as a mask, and the ion reference =0 is implanted by the ion implantation process (i〇n impla(10)U〇n pr〇cess). Thus, the 'mask pattern prevents ions from being implanted into the light-emitting unit region,' and thus ionizes the semiconductor layer adjacent to the light-emitting unit region. The ions may be implanted into the P-type semiconductor layer 150, the active layer 140, the N-type semiconductor layer 130, and the buffer layer 12A. At the same time, in order to enable the respective semiconductor layers 12 to 150 to be counter-doped 'the ions can be implanted into the semiconductor layer by adjusting Rp several times', the anti-doping is used to convert a layer of conductive semiconductor layers. A layer of high, resistive or insulating semiconductor layer. Therefore, the back doping may be limited to the N-type and P-type semiconductor layers 130 and 150 in the case of the buffer layer 120 or the active layer U0 疋-layer insulating layer. Also, ions may be implanted into the upper region of the substrate (clear (10)) in order to ensure electrical insulation between adjacent light-emitting units. The above ions may be selected, for example, from N, Q, Fe, and V, and implant ions at a dose of 1 〇 15 〜 1 〇 22 于 in an ion implantation energy range of 10 to 10 = 00 KeV. After that, the mask pattern 210 is removed. As shown in FIG. 10, a region of the N-type semiconductor layer ι3 露出 is exposed, a layer + a transparent electrode layer 16 形成 is formed, and a line 170 is formed (as shown in FIG. 5 or 11 (4). Then, 'the line 17 is formed thereon. A layer 23016-D-pif 17 201031036 wavelength conversion material layer 18 is formed on the substrate 110. According to this embodiment of the invention, since an isolation insulating layer 2 is formed through an ion implantation process, the buffer layer is not etched. The 12 〇, \-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 15 〇 ^ avoid damage caused by the cooking process.
同時，在本發明的上述各實施例中，於]^型 130以及/或是透明電極f 16〇上可形成多個電極ς (electrode pads)(未繪示），再將線路17〇連接到 【圖式簡單朗】 圖1至圖3是描繪習知的一種製造具有多個 之發光元件的方法的剖面圖。 圖4是圖2的平面圖，以描繪習知製造具有發光 之發光元件的方法。 翁個依照本發明之一實施例的一種具有能彼此隔离 數個發光^的—層隔離絕緣層之發光元件的剖面圖。 照本發明之上述實施例的-種具有能彼此内Meanwhile, in the above embodiments of the present invention, a plurality of electrode pads (not shown) may be formed on the pattern 130 and/or the transparent electrode f 16 , and the line 17 is connected to BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 3 are cross-sectional views depicting a conventional method of fabricating a plurality of light-emitting elements. Figure 4 is a plan view of Figure 2 illustrating a conventional method of fabricating a light-emitting element having illumination. A cross-sectional view of a light-emitting element having a plurality of layers of insulating insulating layers capable of isolating each other in accordance with an embodiment of the present invention. The above-described embodiments of the present invention have the ability to
發光單元的一層隔離絕緣層之發光元件的平面圖t 圖7至圖1〇是依照本發明之一實施例的一種製造每 光元件的方法的剖面圖。 圖11是適用於本發明之某些實施例的一種形成空木 線路的方法的剖面圖。 圖12與圖13是依照本發明之另一實施例的發光元丰 的剖面圖。 【主要元件符號說明】 23〇l6-D、pif 18 201031036 10、110 :基底 20、120 :緩衝層 30、130 ·· N型半導體層 40、140 :主動層 50、150 : P型半導體層 60、160 :透明電極層 70、170 :線路A plan view of a light-emitting element of an insulating layer of a light-emitting unit. Fig. 7 to Fig. 1A are cross-sectional views showing a method of manufacturing each light element in accordance with an embodiment of the present invention. Figure 11 is a cross-sectional view of a method of forming a void wood line suitable for use in certain embodiments of the present invention. 12 and 13 are cross-sectional views of a luminescent element in accordance with another embodiment of the present invention. [Description of Main Components] 23〇l6-D, pif 18 201031036 10, 110: Substrate 20, 120: Buffer Layer 30, 130 · N-type Semiconductor Layer 40, 140: Active Layer 50, 150: P-type Semiconductor Layer 60 , 160: transparent electrode layer 70, 170: line
100a、100b :發光單元 155 :溝渠 180 :波長轉換材料層 200 :隔離絕緣層 210 :罩幕圖案 230 :離子100a, 100b: light-emitting unit 155: trench 180: wavelength conversion material layer 200: isolation insulating layer 210: mask pattern 230: ion
23016-D-pif 1923016-D-pif 19