201027629 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體元件之製作方法，尤指一種可 有效抑制通道效應（channeling effect)之半導體元件之製作方 法。 ❹ 【先前技術】 金氧半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor，以下簡稱為MOSFET)係為半導體技 術領域中普遍用來執行積體電路所需功能的典型元件。請參 閱第1圖，第1圖係為一習知之MOSFET之剖面示意圖。 簡單地說，MOSFET之製作係於基底1〇〇上形成一介電層 102與一未摻雜之多晶矽(polysilicon)層104，然後圖案化上 述兩膜層而形成一閘極結構106。接下來以閘極結構106為 遮罩，於閘極結構106兩側之基底1〇〇内分別形成一輕摻雜 汲極(lightly doped drain，以下簡稱為LDD) 110。隨後於閘 極結構106之侧壁形成一側壁子in;最後利用閘極結構1〇6 與側壁子112為遮罩，於侧壁子112兩侧之基底1〇〇内分別 形成一源極/汲極120。 4 201027629 請繼續參閱第1圖。一般在形成作為閘極導電層的多晶 矽層104時，係於約62〇°C之環境溫度中形成具有柱狀結構 (column structure)的多晶石夕層1〇4，如第]圖所乔’多晶石夕 層104中的線條代表晶粒邊界(grain boundary)。如前所述’ 由於在離子佈植源極/汲極12〇時係利用閘極結構106與側壁 子112作為遮罩，因此若在佈植時該等離子沿著某特定的佈 植角度進入多晶石夕層1 〇4，將會沿著多晶石夕層1 〇4内柱狀結 〇 構的晶格邊界前進，使離子的植入距離超過預期的深度’導 致植入離子在深度控制上的困難，即所謂的通道效應 (channeling effect)。由於通道效應的影響，離子甚至會穿透 多晶矽層104與介電層1〇2，破壞介電層102的品質，降低 其穩定性而造成可靠性的問題。更嚴重的是，通道效應會造 成MOSFET臨界電壓的飄移，甚至造成元件無法關閉而使 電路失效。 另外，習知技術中常發生閘極結構106的多晶矽層1〇4 在反轉階段(inversion)在多晶石夕層104鄰近介電層102的區 域產生載子(carrier)空乏的現象，即發生閘極的空乏效應 (depletion effect)，使得有效閘極電容（effect gate capacitance) 降低的問題。因此業界亦有以降低閘極結構106之高度，即 降低多晶矽層104之厚度的方法來降低空乏效應的發生。而 隨著製程技術不斷的進步，閘極線寬縮小至90奈米（nm)以 下時，閘極結構106的高度，即多晶矽層104的厚度也需隨 5 201027629 之降低以避免工乏效應的發生然而這卻使得上逃穿 的影響更加顯著。 &欵應 此外’在其他的習知技術中，多晶石夕層1〇4亦有在 620°C的環境溫度成長的情形，此時長成的多騎層於 有更大的明粒及更明顯的桂狀結構，使得通道效應益、 顯。上述的產时要求及製程條件在在增加了通道效應 ❿情形’且增加了製程控制上的困難度，此如何在有限的 程範圍内，與不再提升製程控制的困難的前提下，使、製 MOSFET的閘極工程能同時有效地抑制空乏效應與通道 應，實為一值得關注之問題。 * 【發明内容】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device capable of effectively suppressing a channeling effect. ❹ [Prior Art] Metal-Oxide-Semiconductor Field-Effect Transistor (hereinafter referred to as MOSFET) is a typical component commonly used in semiconductor technology to perform the functions required for integrated circuits. Please refer to Fig. 1. Fig. 1 is a schematic cross-sectional view of a conventional MOSFET. Briefly, the MOSFET is formed by forming a dielectric layer 102 and an undoped polysilicon layer 104 on the substrate 1 and then patterning the two layers to form a gate structure 106. Next, a gate structure 106 is used as a mask, and a lightly doped drain (LDD) 110 is formed in the substrate 1 两侧 on both sides of the gate structure 106. Then, a sidewall spacer is formed on the sidewall of the gate structure 106; finally, the gate structure 1〇6 and the sidewall spacer 112 are used as a mask, and a source is formed in the substrate 1〇〇 on both sides of the sidewall 112. Bungee 120. 4 201027629 Please continue to refer to Figure 1. Generally, when the polysilicon layer 104 as a gate conductive layer is formed, a polycrystalline stone layer 1〇4 having a column structure is formed at an ambient temperature of about 62 ° C, as described in FIG. The lines in the polycrystalline layer 104 represent grain boundaries. As described above, since the gate structure 106 and the sidewall sub-112 are used as masks when the source/drain 12 离子 is implanted, the plasma enters a certain implantation angle at the time of implantation. The spar layer 1 〇4 will advance along the lattice boundary of the columnar structure of the polycrystalline slab layer 1 〇4, so that the implantation distance of the ions exceeds the expected depth', resulting in the depth control of the implanted ions. The difficulty is the so-called channeling effect. Due to the effect of the channel effect, the ions may even penetrate the polysilicon layer 104 and the dielectric layer 1〇2, destroying the quality of the dielectric layer 102, reducing its stability and causing reliability problems. More seriously, the channel effect can cause the MOSFET's critical voltage to drift, and even cause the component to fail to turn off and the circuit to fail. In addition, in the prior art, the polysilicon layer 1〇4 of the gate structure 106 often occurs in the inversion in the region of the polycrystalline layer 104 adjacent to the dielectric layer 102, causing carrier depletion, ie, occurs. The depletion effect of the gate causes a problem of reducing the effective gate capacitance. Therefore, the industry has also reduced the thickness of the gate structure 106, i.e., the thickness of the polysilicon layer 104, to reduce the occurrence of depletion effects. With the continuous advancement of process technology, when the gate line width is reduced to less than 90 nanometers (nm), the height of the gate structure 106, that is, the thickness of the polysilicon layer 104, is also required to be reduced with 5 201027629 to avoid the lack of work. However, this has made the impact of the escape more significant. In addition, in other conventional techniques, the polycrystalline stone layer 1〇4 also grows at an ambient temperature of 620 ° C, at which time the multi-layered layer has a larger clear grain. And the more obvious laurel-like structure makes the channel effect beneficial. The above-mentioned production time requirements and process conditions are increasing the channel effect ' situation and increasing the difficulty of process control. How can this be within a limited range and without the difficulty of improving process control? The gate engineering of the MOSFET can effectively suppress the depletion effect and the channel response at the same time, which is a problem worthy of attention. * [Summary of the Invention]
因此，本發明之一目的係在於提供一種可同時抑制空 效應與穿透效應之半導體元件之製作方法。 根據本發明所提供之申請專利範圍，係提供一種半導體 裝置之製作方法’該方法首先提供—基底，且該基底上形成 有-多晶梦層與—絕緣層。接下來圖案化該多晶梦層與該絕 緣層，以於該基底上形成至少一閘極結構。之後，依序於該 閘極結構兩侧之該基底内分別形成一輕摻雜汲極(ldd)，並 於該閘極結構之側壁形成一側壁子。形成侧壁子之後，係於 6 201027629 該閘極結構之一頂部與該侧壁子兩側之該基底上分別形成 一阻擋層（barrier layer)。最後於該侧壁子兩側被該阻擋層覆 蓋之該基底内分別形成一源極/汲極。 根據本發明所提供之製作半導體元件之方法’係藉由形 成於閘極結構頂部表面之阻擋層在源極/汲極之離子佈植製 程中阻擋摻雜質進入多晶矽層，以避免摻雜質因通道效應沿 ® 著晶粒邊界到達多晶矽層與介電層的交界處，甚或穿透介電 層’破壞其品質而降低其穩定性及可靠性，以及造成臨界電 壓的飄移的問題。且由於阻擋層之設置，用來活化摻雜質以 形成源極/彡及極的RTP不必藉由降低熱預算以避免上述摻雜 質在RTP中擴散甚或穿透介電層的問題；故亦可額外避免因 降低熱預算而產生的空乏效應。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device which can suppress both a null effect and a penetration effect. According to the scope of the invention provided by the present invention, there is provided a method of fabricating a semiconductor device. The method first provides a substrate, and a polycrystalline dream layer and an insulating layer are formed on the substrate. The polycrystalline dream layer and the insulating layer are next patterned to form at least one gate structure on the substrate. Thereafter, a lightly doped drain (ldd) is formed in the substrate on both sides of the gate structure, and a sidewall is formed on the sidewall of the gate structure. After forming the sidewalls, a barrier layer is formed on the top of one of the gate structures and the substrate on both sides of the sidewalls, respectively, at 6 201027629. Finally, a source/drain is formed in the substrate covered by the barrier layer on both sides of the sidewall. The method for fabricating a semiconductor device according to the present invention is to block dopants from entering the polysilicon layer in the source/drain ion implantation process by a barrier layer formed on the top surface of the gate structure to avoid doping. Because of the channel effect along the grain boundary to the junction of the polysilicon layer and the dielectric layer, or even the penetrating dielectric layer 'destroys its quality, it reduces its stability and reliability, and causes the drift of the threshold voltage. And because the barrier layer is disposed, the RTP used to activate the dopant to form the source/germanium and the pole does not have to reduce the thermal budget to avoid the problem that the dopant is diffused or penetrates the dielectric layer in the RTP; The depletion effect caused by lowering the thermal budget can be additionally avoided.
【實施方式】 凊參閱第2圖至第5圖，第2圖至第5圖係為本發明所 k供之半導體裝置之製作方法之一第一較佳實施例之示意 圖。如第2圖所示，首先提供一基底200，基底200可為一 矽基底或矽覆絕緣(silicon-on-insulator，SOI)基底等。基底 200上係依序形成一介電層202與一多晶矽層204，介電層 202可由氧化物（oxide)、氮氧化物(oxy_nitride)等具有氧原子 或氮原子及其組合的介電材料所構成；而多晶矽層204則為 201027629 一在大於600°C，如720°C之環境中藉由化學氣相沈積 (chemical vapor deposition，以下簡稱為CVD)方法所形成之 膜層。此外，多晶矽層204係為一具有柱狀結構的膜層，第 2圖中多晶矽層204的線條即代表晶粒邊界。 請繼續參閱第2圖。圖案化多晶石夕層2〇4與介電層2〇2， 而於基底200上形成至少一如第2圖所示之閘極結構2〇6。 ❹接著在基底200上形成一襯墊層208，襯墊層208可為一厚 度介於50埃(angstrom)與400埃之間、由氧化矽構成之膜 層，然熟知該項技藝之人士應知襯墊層2〇8之厚度及材料係 不限於此。隨後，係利用一離子佈植製程(i〇n implamati〇n)， 以於閘極結構206兩側之基底2〇〇内分別形成一摻雜區（圖 未不）；隨後再藉由一快速熱處理製程(rapid thermal processing，以下簡稱為RTp)活化摻雜區中的摻雜質，而形 )成第2圖所示的輕摻雜没極（LDD)21〇。由於上述步驟與根 據不同型態的半導體元件所選用的接雜質係為熟習該項技 藝者與具通常知識者所熟知，故於此不多加贅述。 請參閱第3圖。待完成LDD 210之製作後，係於閘極結 構206之侧壁製作—側壁子212。侧壁子212之製作首先係 ;土底00上$成一單層或多層結構之膜層，而該膜層係^ 包含氧化砍、氮切、氮氧财或其他的介電材料。隨後再 進订-回蚀刻製程’利用襯墊層挪作為則停止層直接回 201027629 蝕刻該單層或多層結構之膜層，以得到如第3圖所示之側壁 子212，且閘極結構208頂部表面與基底200表面會殘餘有 部份的襯墊層208。熟習該項技藝者與具通常知識者均亦了 解，本實施例之侧壁子212也可為其他形狀、材料、結構層 之組合，並不以此為限。 請參閱第4圖。在形成侧壁子212之後，隨即係進行一 Φ 稀釋氟化氩(diluteHF，以下簡稱為DHF)清洗步驟，利用DHf 移除存留在閘極結構208頂部表面與基底200表面之襯墊層 208，以及移除閘極結構208頂部表面與基底200表面不必 要的顆粒或俱生氧化層（native oxide)。 請繼續參閱第4圖。在DHF清洗製程之後，係重新於閘 極結構206頂部之一表面與侧壁子212兩側基底202之表面 _ 分別形成一阻擋層（barrier layer) 218。阻擂層218係可藉由 實施CVD方法、氧電漿灰洗(plasma ash)方法、或過氧化氫 (H2〇2)自對準浸潰方法等所形成；其包含有氧化矽或氮氧化 矽等。而在本第一較佳實施例中，阻擋層218係一藉由氧電 漿灰洗(Plasma Ash)方法完成、厚度係介於8〜18埃，較佳厚 度約為13埃之氧化矽層。氧電漿灰洗方法之製程溫度介於 180°C-270°C，較佳約為250°C ;製程時間介於90秒-150秒， 較佳約為90秒。另外，在本第一較佳實施例的變化型態中， 亦可在氧電漿灰洗方法實施時注入氮氣，而形成由氮氧化矽 9 201027629 構成之阻擋層218。 212兩侧圖。接下來再利用一離子佈植製程於側壁子 - RTP、、舌作218内分別形成一摻雜區（圖未示）；並藉由 汲極220。#雜區中的換雜質’而形成第5圖所示的源極/ ❿a在本第一較佳實施例中，係藉由形成於閘極結構206頂 部表面之阻擋層218在源極/汲極220之離子佈植製程中阻擋 ，雜質進入多晶石夕層2G4，以避免摻雜f在因通道效應沿著 晶粒邊界到達多晶矽層204與介電層202的交界處，甚或穿 2介電層202，破壞介電層202的品質而降低其穩定性與可 靠性，以及造成臨界電壓的飄移等問題。且由於阻擋層218 降低了摻雜質進入多晶矽層2〇4的可能，因此用以活化摻雜 ❹質以形成源極/汲極220的RTP不必藉由降低熱預算以避免 上述摻雜質在RTP中擴散甚或穿透介電層202的問題；也因 此可額外避免因降低熱預算而產生的空乏效應。 請參閱第6圖至第1〇圖，第6圖至第10圖係為本發明 所提供之半導體裝置之製作方法之一第二較佳實施例之示 意圖。如第6圖所示，首先提供一基底300，基底300可為 一矽基底或矽覆絕緣(SOI)基底等。如前所述，基底300上係 包含一由氧化物、氮氧化物等具有氧原子或氮原子及其組合 201027629 的介電材料所構成的介電層302’與一在大於600°C，如720°C 之環境中藉由CVD方法所形成之多晶矽層304。多晶矽層 304係為一具有柱狀結構的膜層，第6圖中多晶矽層304的 線條即代表晶粒邊界。隨後係圖案化多晶矽層304與絕緣層 302，而於基底300上形成至少一閘極結構306。 請繼續參閱第6圖。接著在基底300上形成一襯塾層 ❹ 308 ’襯墊層308可為一厚度介於50埃與400埃之間、由氧 化矽構成之臈層，然熟知該項技藝之人士應知襯墊層3〇8之 厚度及材料係不限於此。隨後，係利用一離子佈植製程，以 於閘極結構306兩側之基底300内分別形成一摻雜區（圖未 示）；再藉由一 RTP活化摻雜區中的摻雜質，而形成第6圖 所示的LDD 310。如前所述，由於上述步驟與根據不同型熊 的半導體元件所選用的摻雜質係為熟習該項技藝者與具通“ _ 常知識者所熟知，故於此亦不多加贅述。 請參閱第7圖。待完成LDD 310之製作後，係於閘極結 構306之側壁製作側壁子312。側壁子312之製作首先係^ 基底300上形成一單層或多層結構之膜層，而該膜層係可^ 含氧化>5夕、氮化石夕、氮氧化石夕或其他的介電材料。隨後進广 一回餘刻製程，利用襯墊層通作為#刻停止層直接回飾= 該單層或多層結構之膜層，以得到如第7圖所示之側璧子· 312且間極結構3〇6頂部纟面與基底耀表面會殘餘有部 11 201027629 份的襯墊層308。同樣地，本實施例之側壁子312也可為其 他形狀、材料、結構層之組合，並不以此為限。 請參閱第8圖與第9圖。接下來再進行一蝕刻製程，以 於側壁子312兩侧之基底300内分別形成一凹槽314。待凹 槽314形成之後，係先進行一預清洗(pre-clean)製程，接著 再進行一烘烤(baking)製程，利用約750°C至950°C的溫度去 ❿除殘留於凹槽314表面的氧化物，並修補原本粗糙的凹槽 314表面。隨後進行一選擇性蟲晶成長(selective epitaxial growth，以下簡稱為SEG)製程，而如第9圖所示於凹槽314 内分別形成一遙晶層316，蟲晶層316則依半導體元件電性 之要求可分別包含有鍺化矽（SiGe)或碳化矽（Sic)。在本第二 較佳實施例中，係藉由SEG技術，並利用磊晶層的晶格常 數(lattice constant)比矽大此一特性，使磊晶層產生結構上應 • 變而形成應變矽’並帶動通道區部分之單晶矽之晶格與帶結 構(band structure)發生改變’造成載子移動性增加，並提升 半導體元件的載子遷移速度。 請參閱第9圖。在進行SEG製程形成磊晶層316之後， 係進行一 DHF清洗步驟，利用DHF移除閘極結構3〇6頂部 表面及基底300表面不必要的顆教或俱生氧化層。而在dhf 清洗製程之後’係於閘極結構306頂部之表面與蟲晶層316 之一表面分別形成一阻擋層318。如前所述，阻'撞層3\8係 12 201027629 可藉由實施CVD方法、氳啻將如 方法等形成;其包含有氧化方法、或過氧化氫浸潰 實施例中，阻播二=—夕等。在本第二較佳 μ入认。 Μ—藉由乳電漿灰洗方法完成、厚 ❹ =Γ〜18埃之氧化石夕層。議灰洗方法之製程參數 係第—較佳實施例；而在本第二較佳實施例中，較佳製 程溫度約為25G°C，較佳製程時間約為9〇秒，阻擒層318之 厚度約為13埃。在本第二較佳實施例的變化型態中，亦可 在氧電漿域方法實_注人氮氣，㈣成由氮氧化 之阻擋層318。 明參閱第1G圖。隨後再利用—離子佈植製程於蟲晶層 316内分別形成—摻雜區（圖未示）；並藉由-RTP活化摻雜 區中的掺雜質’而形成第1()圖所示的源極/汲極32〇。’ 在本第二較佳實施例中，形成於閘極結構306頂部表面 之阻擋層318在離子佈植製料係阻擋#雜質進人多晶石夕層 304，故可避免摻雜質因通道效應沿著晶粒邊界到達多晶砂 層304與介電層302的交界處，甚或穿透介電層3〇2，而降 低其穩定性及可靠性，以及造成閘減界電壓飄移的問題。 另外，用以活化摻雜質以形成源極/汲極^❹的^卩不必藉 由降低熱預算以避免上述摻雜質在RTp中擴散甚或穿透介 電層302的問題；故亦可額外避免因降低熱預算而產生的空 乏效應。 1 13 201027629 此外，請參閲第11圖，第11圖係為第一較佳實施例與 第一較佳實施例之一變化型態之示意圖。在本第一較佳實施 例與第二較佳實施例中，更可包含一離子佈植步驟5〇〇，進 行於形成多晶矽層204/304之後，該離子佈植步驟使用之離 子包含有鍺、磷、氧、或氮等離子。該等摻雜的離子會撞擊 具有柱狀結構的矽晶格，甚至於多晶矽層204/304中形成一 ❹層资亂的非結晶結構，而得以緩解後續作為源極/汲極而植入 的摻雜質的通道效應。 綜上所述’根據本發明所提供之製作半導體元件之方 法’係藉由形成於閘極結構頂部表面之阻擋層在源極/汲極之 離子佈植製程中阻擋摻雜質進入多晶矽層，以避免摻雜質因 通道效應沿著晶粒邊界迅速到達多晶矽層與介電層的交界 备處’甚或穿透介電層’破壞其品質而降低其穩定性及可靠 性，以及造成臨界電壓的飄移的問題。且由於阻檔層降低了 摻雜質貫穿多晶矽層的可能，因此用以活化摻雜質以形成源 極/汲極的RTP不必藉由降低熱預算以避免多晶矽層内的摻 雜質在RTP中擴散甚或穿透介電層的問題；也因此可額外避 免因降低熱預算而產生的空乏效應。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 201027629 【圖式簡單說明】 第1圖係為一習知之MOSFET之剖面示意圖。 第2圖至第5圖係為本發明所提供之半導體裝置之製作 方法之一第一較佳實施例之示意圖。 第6圖至第10圖係為本發明所提供之半導體裝置之製作 φ 方法之一第二較佳實施例之示意圖。 第11圖係為第一較佳實施例與第二較佳實施例之一變化 型態之示意圖。 【主要元件符號說明】 100、200、300 基底 102 ' 202 > 302 介電層 ® 104、204、304 多晶矽層 106、206、306 閘極結構 208 、 308 襯墊層 110、210、310 輕摻雜沒極 112 ' 212 > 312 侧壁子 314 凹槽 316 遙晶層 218 、 318 阻擋層 15 201027629 120、220、320 源極/汲極 500 離子佈植步驟[Embodiment] Referring to Figs. 2 to 5, Figs. 2 to 5 are schematic views showing a first preferred embodiment of a method of fabricating a semiconductor device according to the present invention. As shown in Fig. 2, a substrate 200 is first provided. The substrate 200 can be a germanium substrate or a silicon-on-insulator (SOI) substrate. A dielectric layer 202 and a polysilicon layer 204 are sequentially formed on the substrate 200. The dielectric layer 202 may be made of a dielectric material having an oxygen atom or a nitrogen atom and a combination thereof, such as an oxide or an oxy-nitride. The polycrystalline germanium layer 204 is a film layer formed by a chemical vapor deposition (hereinafter referred to as CVD) method in an environment of more than 600 ° C, such as 720 ° C. Further, the polycrystalline germanium layer 204 is a film layer having a columnar structure, and the line of the polycrystalline germanium layer 204 in Fig. 2 represents a grain boundary. Please continue to see Figure 2. The polysilicon layer 2〇4 and the dielectric layer 2〇2 are patterned, and at least one gate structure 2〇6 as shown in FIG. 2 is formed on the substrate 200. Then, a liner layer 208 is formed on the substrate 200. The liner layer 208 can be a film layer composed of yttrium oxide having a thickness between 50 angstroms and 400 angstroms, and those skilled in the art should The thickness and material of the liner layer 2〇8 are not limited thereto. Subsequently, an ion implantation process (i〇n implamati〇n) is used to form a doped region in the substrate 2〇〇 on both sides of the gate structure 206 (Fig. 9); The heat treatment process (rapid thermal processing, hereinafter referred to as RTp) activates the doping in the doped region, and forms the lightly doped (LDD) 21 第 shown in FIG. 2 . Since the above steps and the impurity used in the selection of semiconductor elements according to different types are well known to those skilled in the art, they will not be described here. Please refer to Figure 3. After the fabrication of the LDD 210 is completed, a sidewall spacer 212 is fabricated on the sidewall of the gate structure 206. The sidewall 212 is fabricated first; the soil layer 00 is formed into a single layer or a multi-layered film layer, and the film layer comprises oxidized chopped, nitrogen cut, nitrogen oxide or other dielectric material. Then, the re-etching process is performed by using the pad layer as the stop layer directly back to 201027629 to etch the film layer of the single layer or the multilayer structure to obtain the sidewall spacer 212 as shown in FIG. 3, and the gate structure 208 A portion of the liner layer 208 remains on the top surface and the surface of the substrate 200. It is also known to those skilled in the art and those skilled in the art that the side wall 212 of this embodiment can also be a combination of other shapes, materials, and structural layers, and is not limited thereto. Please refer to Figure 4. After the sidewall spacer 212 is formed, a Φ-dilution fluorinated argon (Dilute HF, hereinafter abbreviated as DHF) cleaning step is performed, and the pad layer 208 remaining on the top surface of the gate structure 208 and the surface of the substrate 200 is removed by using DHf. And removing unwanted particles or native oxide from the top surface of the gate structure 208 and the surface of the substrate 200. Please continue to see Figure 4. After the DHF cleaning process, a barrier layer 218 is formed on the surface of one of the tops of the gate structure 206 and the surface of the substrate 202 on both sides of the sidewall 212. The barrier layer 218 can be formed by performing a CVD method, an oxygen plasma ash method, or a hydrogen peroxide (H 2 〇 2) self-aligned immersion method, etc.; Hey. In the first preferred embodiment, the barrier layer 218 is formed by a plasma ash method, and has a thickness of 8 to 18 angstroms, preferably about 13 angstroms. . The oxygen plasma ash washing process has a process temperature of from 180 ° C to 270 ° C, preferably about 250 ° C, and a process time of from 90 seconds to 150 seconds, preferably about 90 seconds. Further, in a variation of the first preferred embodiment, nitrogen gas may be injected during the oxygen plasma ash washing method to form a barrier layer 218 composed of yttrium oxynitride 9 201027629. 212 sides of the map. Next, an ion implantation process is used to form a doped region (not shown) in the sidewall sub-RTP, and the tongue 218, respectively, and by the drain 220. The source/❿a shown in FIG. 5 is formed by replacing the impurity in the impurity region. In the first preferred embodiment, the barrier layer 218 formed on the top surface of the gate structure 206 is at the source/deuterium. In the ion implantation process of the pole 220, the impurity enters the polycrystalline layer 2G4 to avoid doping f at the boundary of the polycrystalline germanium layer 204 and the dielectric layer 202 along the grain boundary due to the channel effect, or even the second layer. The electrical layer 202 destroys the quality of the dielectric layer 202 to reduce its stability and reliability, as well as causing problems such as drift of the threshold voltage. And since the barrier layer 218 reduces the possibility of doping into the polysilicon layer 2〇4, the RTP used to activate the doped enamel to form the source/drain 220 does not have to reduce the thermal budget to avoid the above dopants. The problem of diffusing or even penetrating the dielectric layer 202 in the RTP; therefore, it is possible to additionally avoid the depletion effect caused by lowering the thermal budget. Referring to Figures 6 through 1 , FIGS. 6 through 10 are schematic views of a second preferred embodiment of a method of fabricating a semiconductor device provided by the present invention. As shown in Fig. 6, a substrate 300 is first provided, and the substrate 300 may be a germanium substrate or a silicon-on-insulator (SOI) substrate or the like. As described above, the substrate 300 comprises a dielectric layer 302' composed of a dielectric material having an oxygen atom or a nitrogen atom, and a combination thereof, 201027629, such as an oxide, an oxynitride, and the like, at a temperature greater than 600 ° C, such as A polysilicon layer 304 formed by a CVD method in an environment of 720 °C. The polycrystalline germanium layer 304 is a film layer having a columnar structure, and the line of the polycrystalline germanium layer 304 in Fig. 6 represents a grain boundary. Subsequently, the polysilicon layer 304 and the insulating layer 302 are patterned, and at least one gate structure 306 is formed on the substrate 300. Please continue to see Figure 6. Next, a liner layer 308 is formed on the substrate 300. The liner layer 308 can be a layer of ruthenium oxide having a thickness between 50 angstroms and 400 angstroms, and those skilled in the art should be aware of the liner. The thickness and material of the layer 3〇8 are not limited thereto. Subsequently, an ion implantation process is used to form a doped region (not shown) in the substrate 300 on both sides of the gate structure 306; and the dopant in the doped region is activated by an RTP. The LDD 310 shown in Fig. 6 is formed. As mentioned above, since the above steps and the doping system selected for the semiconductor components of different types of bears are well known to those skilled in the art, they are not well known here. Figure 7. After the LDD 310 is completed, the sidewalls 312 are formed on the sidewalls of the gate structure 306. The sidewalls 312 are formed by first forming a single or multi-layered film layer on the substrate 300. The layer system can contain oxidized >5 eve, nitrite, nitrous oxide or other dielectric materials. Then, the process is repeated, and the liner layer is used as the #刻止层 directly backing = The film layer of the single layer or the multilayer structure is obtained to obtain the side rafter 312 as shown in Fig. 7 and the top layer and the base glare surface of the interpole structure 3 〇6 are left with the lining layer 308 of the portion 11 201027629 parts. Similarly, the side wall 312 of this embodiment may also be a combination of other shapes, materials, and structural layers, and is not limited thereto. Please refer to FIG. 8 and FIG. 9. Next, an etching process is performed to A groove 314 is formed in each of the bases 300 on both sides of the side wall 312. The groove 31 is to be formed. After the formation of 4, a pre-clean process is performed, followed by a baking process, and the temperature remaining on the surface of the groove 314 is removed by using a temperature of about 750 ° C to 950 ° C. And repairing the surface of the original rough groove 314. Subsequently, a selective epitaxial growth (SEG) process is performed, and a crystal layer is formed in the groove 314 as shown in FIG. 316, the worm layer 316 may contain bismuth telluride (SiGe) or tantalum carbide (Sic) according to the electrical requirements of the semiconductor device. In the second preferred embodiment, the SEG technology is utilized, and the ray is utilized. The lattice constant of the crystal layer is larger than that of the germanium, so that the epitaxial layer is formed into a crystal lattice and band structure which is structurally deformed to form a strain 矽' and drives a portion of the channel region. The change has caused the carrier mobility to increase and the carrier migration speed of the semiconductor device to be improved. Please refer to Fig. 9. After the SEG process is performed to form the epitaxial layer 316, a DHF cleaning step is performed to remove the gate using DHF. Pole structure 3〇6 top surface and base 300 surface unnecessary teaching or oxide layer. After the dhf cleaning process, the surface of the top of the gate structure 306 and the surface of the crystal layer 316 form a barrier layer 318. 'Bump layer 3\8 series 12 201027629 can be formed by a CVD method, a method such as a method, etc.; it includes an oxidation method, or a hydrogen peroxide impregnation embodiment, and the second is blocked. The second preferred μ is recognized. Μ - The oxidized stone layer is completed by a milk-electric ash washing method and thick ❹ = Γ 18 angstroms. The process parameters of the graywashing method are the preferred embodiment; and in the second preferred embodiment, the preferred process temperature is about 25 G ° C, and the preferred process time is about 9 sec., the barrier layer 318 The thickness is about 13 angstroms. In a variation of the second preferred embodiment, it is also possible to use a nitrogen gas in the oxygen plasma field method and (4) a barrier layer 318 which is oxidized by nitrogen. See Figure 1G for details. Then, an ion implantation process is used to form a doped region (not shown) in the insect crystal layer 316; and the doping property in the doped region is activated by -RTP to form the first () image. Source/drain 32 〇. In the second preferred embodiment, the barrier layer 318 formed on the top surface of the gate structure 306 blocks the impurity into the polycrystalline layer 304 in the ion implantation system, thereby avoiding the doping channel. The effect reaches the boundary between the polycrystalline sand layer 304 and the dielectric layer 302 along the grain boundary, or even penetrates the dielectric layer 3〇2, thereby reducing the stability and reliability thereof, and causing the problem of gate drop voltage drift. In addition, the method for activating the dopant to form the source/drain electrode does not need to reduce the thermal budget to avoid the problem that the dopant diffuses in the RTp or penetrates the dielectric layer 302; Avoid the effects of depletion due to lowering the thermal budget. 1 13 201027629 In addition, please refer to FIG. 11 , which is a schematic diagram showing a variation of the first preferred embodiment and the first preferred embodiment. In the first preferred embodiment and the second preferred embodiment, an ion implantation step 5 is further included, and after the formation of the polysilicon layer 204/304, the ions used in the ion implantation step comprise germanium. , phosphorus, oxygen, or nitrogen plasma. The doped ions collide with the germanium lattice having a columnar structure, and even form a layer of disordered amorphous structure in the polycrystalline germanium layer 204/304, thereby alleviating subsequent implantation as a source/drain. Doping channel effect. In summary, the method for fabricating a semiconductor device according to the present invention blocks the doping into the polysilicon layer in the source/drain ion implantation process by a barrier layer formed on the top surface of the gate structure. In order to avoid the doping due to the channel effect, the boundary between the polycrystalline germanium layer and the dielectric layer can be quickly reached along the grain boundary, or even the dielectric layer can destroy its quality and reduce its stability and reliability, as well as the threshold voltage. The problem of drifting. And since the barrier layer reduces the possibility of doping through the polysilicon layer, the RTP used to activate the dopant to form the source/drain does not have to reduce the thermal budget to avoid doping in the polysilicon layer in the RTP. Diffusion or even penetration of the dielectric layer; therefore, it can additionally avoid the depletion effect caused by lowering the thermal budget. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. 201027629 [Simple description of the diagram] Figure 1 is a schematic cross-sectional view of a conventional MOSFET. 2 to 5 are schematic views showing a first preferred embodiment of a method of fabricating a semiconductor device provided by the present invention. 6 to 10 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor device according to the present invention. Figure 11 is a schematic view showing a variation of one of the first preferred embodiment and the second preferred embodiment. [Major component symbol description] 100, 200, 300 substrate 102 '202 > 302 dielectric layer 104, 204, 304 polysilicon layer 106, 206, 306 gate structure 208, 308 pad layer 110, 210, 310 lightly doped Heterogeneous 112 '212 > 312 sidewall 314 groove 316 tele-crystal layer 218, 318 barrier layer 15 201027629 120, 220, 320 source / drain 500 ion implantation step
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