201027621 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種製作堆疊薄膜的方法，尤指一種採用 搭配硬遮罩及兩段式蝕刻製程來製作堆疊薄膜的方法。 【先前技術】 藝 非揮發性記憶體裝置具有不因電源供應中斷而造成儲存 資料遣失的特性，因此被廣泛使用。現今廣泛使用的非揮發 性記憶體裝置包含有唯讀記憶體(read-only-memory， ROM)、可程式化唯讀記憶體(programmable-read-only memory, PROM)、可抹除及可程式化唯讀記憶體 (erasable-programmable-read-only memory, EPROM)以及電 Ο 子式可抹除可程式化唯讀記憶體 (electrically-erasable-programmable-read-only memory, eeprom)。其中，電子式可抹除可程式化唯讀記憶體相較於 其他非揮發性記憶體不同之處在於他們可利用電子來進行 程式化及抹除操作。 目前對EEPROM裝置中產品研發的方向均集中在增加程 式化的速度、降低進行程式化與讀取時的電壓、延長資料保 201027621 * 存的時間、減少記憶體單元的抹除時間以及縮小記憶體元件 的尺寸。此外，習知快閃（Flash)記憶體陣列（array)多係使用 一種由雙層多晶矽堆疊所形成的閘極（DualpQly Sigate)， 且在此閘極結構中多晶矽通常會以介電材料作區隔，元件操 作時將電子由基板注入底層的多晶矽中達到儲存資料(data) 的功能。然而，此由雙層多晶梦閘極所形成的記憶體陣列由 於只能儲存單一位元的資料，故較不利於提昇記憶體容量。 ❹ 因此另一種衍生的快閃記憶體使用矽··氧化物-氮化物_氧化 物-石夕（SONOS)作為資料儲存單元即因應而生，而且可以作到 一個電晶體(transistor)同時儲存二個位元的功能，如此可以 達到縮小元件尺寸及提升記憶體的容量。 需注意的是，習之在製作上述SONOS記憶體的氧化物_ 氮化物-氧化物(ΟΝΟ)結構時通常會直接以一圖案化光阻層 作為遮罩來進行蝕刻製程，以形成所需的〇Ν〇堆疊圖案。 ❹ 由於0Ν0結構最上層的氧化層具有較差的附著性(ρ00Ι· adhesion) ’在餘刻ΟΝΟ堆疊薄膜時通常會在緊貼圖案化光 阻層的最上層氧化層部位形成底切(undercut)現象，進而使影 響整個記憶體元件的運作。因此，如何改良目前的製程來預 防SONOS記憶體結構中產生底切問題即為目前一重要課 題。 【發明内容】 201027621 因此本發明之主要目的是提供一種製作堆疊薄膜的方 法，以改良上述習知在製作SONOS記憶體時容易因堆叠薄 膜中的氧化層附著力不佳而產生底切的問題。 本發明主要揭露一種製作堆疊薄膜的方法。首先提供— 半導體基底’然後形成一堆疊薄膜於半導體基底上，且堆疊 ❿ 薄膜包含複數個介電層。接著覆蓋一硬遮罩於堆疊薄膜上， 並去除部分硬遮罩及堆疊薄膜最底層介電層以上的所有介 電層中未被硬遮罩蓋住的部分，隨後再去除堆疊薄膜中最底 層的介電層。 " ❹ 本發明另揭露-種製作積體電路的方法。首先提供一半 導體基底’該半導體基底上定義有—記憶體區與—邏輯區。 然後形成-堆疊薄膜於半導體基底上之記憶體區及邏輯 區’且堆㈣膜包含複數個介電層。接著硬料於 1憶體區及邏輯區之堆㈣膜表面、部分去除記憶體區之硬 2及堆叠薄膜最底層介電層以上之所有介電層中未被硬 ^罩蓋住的部分以及完全去除邏輯區之硬遮罩及堆疊薄模 =底層介電層以上之所有介電層、部分去除記憶體區之堆叠 =最底層之介電層及完全去除邏輯區之堆叠薄膜最底層 電晶體於邏輯 之介電層、去除記憶體區之硬遮罩以及形成一 區0 201027621 【實施方式】 請參照第1圖至第5圖，第1圖至第5圖為本發明較佳 實施例製作一圖案化堆疊薄膜之示意圖。如第1圖所示，首 先提供一半導體基底12，例如一由矽、砷化鎵、矽覆絕緣 (silicon on insulator，SOI)層、蟲晶層、石夕鍺層或其他半導體 _ 基底材料所構成的基底。然後沈積一堆疊薄膜14於半導體 基底12上。其中，堆疊薄膜14可由複數層材料層所構成， 且各材料層可包含各種介電材料，例如氧化物、氮化物、氮 氧化物、金屬氧化物、或上述組合。在本實施例中，堆疊薄 膜14較佳選自由氧化層-氣化層_氧化層（〇xide_nitride 〇xide， ΟΝΟ)所組成的三層結構。但堆疊薄臈14並不限於三層且每 一層之材料可不與其他層的材料重覆。其中，〇Ν〇堆疊薄 膜主要包含一最底層氧化層16、一氮化層18設於氧化層16 ❹ 上以及另一氧化層20覆蓋在氮化層18上’且此三層堆叠薄 膜的厚度較佳為約100至300埃’較佳地為18〇埃。接著沈 積一由氮化矽層所構成的硬遮罩22在堆疊薄膜14上，並對 硬遮罩22與堆疊薄膜14進行一圖案轉移製程，例如先形成 一圖案化光阻層24於硬遮罩22上。 然後如第2圖所示，進行一蝕刻製程，利用圖案化光阻 層24當作蚀刻遮罩部分去除硬遮罩22與堆疊薄膜14之上 201027621 兩層的氧化層20與氮化層18中未被硬遮罩蓋住的部分，並 暴露出堆疊賴u底部的部分氧化層16。在本實施例中， 上述去除部分硬遮罩22及堆疊薄臈氧化層2〇與氮化層18 的钱刻製程較佳採用乾_，例如—電⑽刻製程。另外， 圖案化光阻層24可依照所需曝光元件的大小來挑選適合的 光阻材料。本發明的圖案化光阻層24較佳選自深紫外線 (deepultraviolet，DUV)光阻材料，但不偈限於此又可依製 ❹程需求選擇適用们65奈米波長的以狀光阻材料，此皆屬 本發明所涵蓋的範圍。另外應注意，若堆叠薄膜14為三層 以上之介電材料所構成’則此_步驟可去除部分硬遮罩Μ 與最底層介電材料層以上的所有介電材料層中未被硬遮罩 22蓋住的部分。 接著如第3圖所示’利用圖案化光阻層μ當作遮罩再進 ❿行-姓刻製程，以部分去除堆疊薄膜14底部的氧化層“並 暴露出半導體基底12。本實施例去除部分氧化層16的餘刻 製程較佳剌-祕職程，且祕刻製財_刻溶液較 佳採用由HF與戰F依不同比例混合而成的氧化物钱刻緩 衝液(Buffer oxidation物叫B0E)。雖然亦可採用乾式餘刻 製程例如電漿則製程來去除部分氧化層16，但祕刻製程 較不會損傷被氧化層16所覆蓋之基底，可保持基底之完整 性與電性品質。另外應注意，若堆疊薄膜14為三層以上之 介電材料所構成’則此蝕刻步驟可去除部分最底層介電材料 8 201027621 層。 如第4圖所示，進行另一蝕刻製程，利用由硫酸與過氧 化氫合物（sulfuric acid-hydrogen peroxide mixture, SPM)所 組成的蝕刻劑來去除硬遮罩22上的圖案化光阻層24。然後 如第5圖所不，進行另一蝕刻步驟，再利用硫酸與過氧化氫 混合物所構成的蝕刻劑來去除堆疊薄膜14表面的硬遮罩 ❹ 22。需注意岐’本實施例雖以兩:欠餘刻步驟來分別去除圈 案化光阻層24與硬遮罩22，但不侷限這個作法，又可在一 次餘刻製財以硫酸與過氧化氫混合物所構成的餘刻劑來 同時去除㈣化総層Μ與硬遮罩22，此錢也屬本發明 所涵蓋的範圍。另外需注意的是，上述由去除堆叠薄膜Μ 底層的氧化層16至去除硬遮罩22為止(例如第3圖至第$ 圖）的製程又可以現場(in_situ)進行的方式來達成，例如，去 ❹除底部氧化層16、去除圖案化絲層24及錯硬遮罩22 的步驟係於同—侧機台中進行，尤其去除底部氧化層16 槽中進行而去除圖案化轨層24與去除硬遮罩Μ 在另一關槽中完成。或者，去除底部氧化層16、去除 化光阻層24及去除硬遮罩22的步驟雖於同 進 行，但三步驟皆於同-機台中的不同_槽中進行。至= 疋成本發明較佳實施例之一圖案化之〇n〇堆疊薄膜結構。 •依據本發明之另一實施例，上述完成的⑽〇堆疊薄膜即 201027621 可接著整合一般MOS電晶體製程，而製作出一 s〇NOS記憶 體結構。此也屬本發明所涵蓋的範圍。請接著參照第6圖至 第Π圖，第6圖至第13圖為本發明另一實施例整合一 SONOS記憶體與一金氧半導體(MOS)電晶體之製程示意圖。 如第6圖所示，先提供一半導體基底32，其上定義有一 記憶體區46與一邏輯區48,且半導體基底32可由矽、坤化 _ 鎵、梦覆絕緣層、蠢晶層、珍鍺層或其他半導體基底材料所 構成的基底。然後同時沈積一堆疊薄膜34於半導體基底32 上的記憶體區46與邏輯區48。其中，堆疊薄膜34可由複數 層材料層所構成，且各材料層可包含各種介電材料，例如氧 化物、氮化物、氮氧化物、金屬氧化物、或上述組合。在本 實施例中’堆疊薄膜34較佳選自由氧化層-氮化層_氧化層 (oxide-nitride-oxide，ΟΝΟ)所組成的三層結構。其中，〇N〇 堆疊薄膜主要包含一最底層氧化層36、一氮化層38設於氧 化層36上以及另一氧化層40覆蓋在氮化層38上，且此三 層堆疊薄膜的厚度較佳為約1〇〇至300埃，較佳地為18〇埃。 但堆疊薄膜34並不限於三層且每一層之材料可不與其他層 的材料重覆。接著沈積一由氮化矽層所構成的硬遮罩42並 覆蓋記憶體區46與邏輯區48的堆疊薄膜34，然後再形成一 圖案化光阻層44於記憶體區46的硬遮罩上42。 如第7圖所示’進行一餘刻製程，利用記憶體區46的圖 201027621 案化光阻層44當作蝕刻遮罩部分去除記憶體區46的硬遮罩 42與堆疊薄膜34上兩層的氧化層4〇與氮化層％中未被硬 遮罩42蓋住的部分，並完全去除邏輯區48的硬遮罩42與 堆疊薄膜34上兩層的氧化層4〇與氮化層％。換句話說，記 ，體區46的堆疊薄臈34在經過上述餘刻製程後仍具有底層 氧化層36及設於氧化層36上的圖案化硬遮罩42、氧化層 40及氮化層38，邏輯區48則僅剩未餘刻的底層氧化層36。 〇 在本實施例中，上述去除硬遮罩42及氧化層40與氮化層38 的飯刻製程較佳採用乾蚀刻’例如—電漿钱刻製程。此外， 圖案化光阻層44可依照所需曝光元件的大小來挑選適合的 光阻材料。在本發明中，圖案化光阻層44較佳選自深紫外 線(deepultraviolet，DUV)光阻材料，但不偈限於此又可依 製程需求選擇適用於365奈米波長的Mine《阻材料，此皆 屬本發明所涵蓋的範m卜紐t，若堆疊薄膜34為三 ❹層以上之介電材料所構成，則此蝕刻步驟可去除部分硬遮罩 42與最底層介電材料層以上的所有介電材料層中未被硬遮 罩42蓋住的部分。 如第8圖所示’進行另—㈣製程，利用圖案化光阻層 44當作遮罩再進行—餘刻製程，以部分去除記憶體區私堆 疊薄膜34底層的氧化層36及邏輯區犯所剩餘的氧化層 %’並暴露出記憶體146的部分半導體基底32與邏輯區伯 的整個半㈣基底32。本實補絲氧化層％ _刻製程 201027621 較佳採用一濕蝕刻製程，且濕蝕刻製程中的蝕刻溶液較佳採 用由HF與ΝΗβ依不同比例混合而成的氧化物蝕刻緩衝液 (Buffer oxidation etchant，ΒΟΕ)。雖然亦可採用乾式蝕刻製 程 例如電漿蝕刻製程來部分去除記憶體區46堆疊薄膜34底層 的氧化層36及邏輯區48所剩餘的氧化層36,但濕蝕刻製程 較不會損傷被氧化層36所覆蓋之基底，可保持基底之完整 性與電性品質，確保隨後於邏輯區48中所形成之閘極氧化 層的品質。另外應注意，若堆疊薄膜34為三層以上之介電 材料所構成，則此蝕刻步驟可部分去除記憶體區46堆疊薄 膜的最底層材料層及邏輯區48所剩餘的最底層材料層。201027621 VI. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a stacked film, and more particularly to a method for fabricating a stacked film by using a hard mask and a two-stage etching process. [Prior Art] The non-volatile memory device is widely used because it has a characteristic that the stored data is not lost due to power supply interruption. Non-volatile memory devices widely used today include read-only-memory (ROM), programmable-read-only memory (PROM), erasable and programmable Erasable-programmable-read-only memory (EPROM) and electrically-erasable-programmable-read-only memory (eeprom). Among them, electronically erasable programmable read-only memory differs from other non-volatile memories in that they can use electronics for stylization and erasing operations. At present, the direction of product development in EEPROM devices is focused on increasing the speed of stylization, reducing the voltage during programming and reading, extending the data retention time, reducing the memory era erasing time and reducing the memory. The size of the component. In addition, conventional flash memory arrays use a gate (DualpQly Sigate) formed by a stack of two-layer polysilicon, and in this gate structure, polysilicon is usually treated with a dielectric material. Separately, when the component is operated, electrons are injected from the substrate into the underlying polysilicon to achieve the function of storing data. However, the memory array formed by the double-layer polycrystalline dream gate is relatively unfavorable for increasing the memory capacity because it can store only a single bit of data. ❹ Therefore, another derivative flash memory is produced by using 矽··oxide-nitride-oxide-SONOS as a data storage unit, and can be stored as a transistor at the same time. The function of one bit can reduce the size of the component and increase the capacity of the memory. It should be noted that in the fabrication of the oxide-nitride-oxide structure of the above SONOS memory, the etching process is usually performed directly with a patterned photoresist layer as a mask to form the desired etching process. 〇Ν〇 Stacking pattern. ❹ Since the topmost oxide layer of the 0Ν0 structure has poor adhesion (ρ00Ι·adhesion), the undercut phenomenon is usually formed in the uppermost oxide layer close to the patterned photoresist layer when the film is stacked. , in turn, affecting the operation of the entire memory component. Therefore, how to improve the current process to prevent the undercut problem in the SONOS memory structure is an important topic at present. SUMMARY OF THE INVENTION 201027621 Accordingly, it is a primary object of the present invention to provide a method of fabricating a stacked film to improve the above-described problem of undercutting due to poor adhesion of an oxide layer in a stacked film when fabricating a SONOS memory. The present invention primarily discloses a method of making a stacked film. First, a semiconductor substrate is provided and then a stacked film is formed on the semiconductor substrate, and the stacked germanium film comprises a plurality of dielectric layers. Then covering a hard mask on the stacked film, and removing portions of all the dielectric layers above the bottommost dielectric layer of the hard mask and the stacked film that are not covered by the hard mask, and then removing the bottom layer of the stacked film Dielectric layer. " ❹ The present invention further discloses a method of fabricating an integrated circuit. First, a half conductor substrate is provided. The memory substrate defines a memory region and a logic region. The memory region and logic region of the stacked film on the semiconductor substrate are then formed and the stack (tetra) film comprises a plurality of dielectric layers. Then, it is hard to be used in the stack of the memory region and the logic region (4), the hard surface of the memory region, and the portion of the dielectric layer above the lowermost dielectric layer of the stacked film that are not covered by the hard mask. Completely remove the hard mask of the logic region and stack thin mode = all dielectric layers above the underlying dielectric layer, partially remove the memory region stack = the bottommost dielectric layer and the topmost transistor of the stacked film that completely removes the logic region The dielectric layer of the logic, the hard mask for removing the memory region, and the formation of a region 0 201027621 [Embodiment] Please refer to FIGS. 1 to 5, and FIGS. 1 to 5 are produced according to a preferred embodiment of the present invention. A schematic diagram of a patterned stacked film. As shown in FIG. 1, a semiconductor substrate 12 is first provided, such as a germanium, gallium arsenide, silicon on insulator (SOI) layer, a worm layer, a lithograph layer, or other semiconductor materials. The base of the composition. A stacked film 14 is then deposited on the semiconductor substrate 12. The stacked film 14 may be composed of a plurality of layers of material, and each of the layers may comprise various dielectric materials such as oxides, nitrides, oxynitrides, metal oxides, or combinations thereof. In the present embodiment, the stacked film 14 is preferably selected from the three-layer structure consisting of an oxide layer-gasification layer_oxide layer (〇xide_nitride 〇xide, ΟΝΟ). However, the stacked thin crucibles 14 are not limited to three layers and the material of each layer may not overlap with the materials of the other layers. Wherein, the germanium-stacked film mainly comprises a bottommost oxide layer 16, a nitride layer 18 is disposed on the oxide layer 16 and another oxide layer 20 is overlying the nitride layer 18' and the thickness of the three-layer stacked film It is preferably about 100 to 300 angstroms, preferably 18 angstroms. Then, a hard mask 22 composed of a tantalum nitride layer is deposited on the stacked film 14, and a pattern transfer process is performed on the hard mask 22 and the stacked film 14, for example, a patterned photoresist layer 24 is formed on the hard mask. On the cover 22. Then, as shown in FIG. 2, an etching process is performed, and the patterned photoresist layer 24 is used as an etch mask portion to remove the hard mask 22 and the stacked film 14 over the two layers of the oxide layer 20 and the nitride layer 18 of 201027621. A portion that is not covered by the hard mask and exposes a portion of the oxide layer 16 at the bottom of the stack. In this embodiment, the process of removing a portion of the hard mask 22 and the stacked thin oxide layer 2 and the nitride layer 18 is preferably performed by a dry process, such as an electrical (10) process. Additionally, the patterned photoresist layer 24 can be selected to suit the desired photoresist material in accordance with the size of the desired exposure element. The patterned photoresist layer 24 of the present invention is preferably selected from a deep ultraviolet (DUV) photoresist material, but is not limited thereto, and may be selected to have a 65 nm wavelength-like photoresist material depending on the process requirements. This is within the scope of the invention. In addition, it should be noted that if the stacked film 14 is composed of three or more dielectric materials, then this step can remove part of the hard mask Μ and all the dielectric material layers above the bottommost dielectric material layer are not hard masked. 22 covered parts. Next, as shown in FIG. 3, 'the patterned photoresist layer μ is used as a mask to perform the lithography process to partially remove the oxide layer at the bottom of the stacked film 14 and expose the semiconductor substrate 12. This embodiment removes The residual etching process of the partial oxidation layer 16 is better, and the secret engraving solution is preferably an oxide engraving buffer which is prepared by mixing HF and warfa F in different proportions. B0E). Although a dry engraving process such as a plasma process can also be used to remove the partial oxide layer 16, the secret engraving process does not damage the substrate covered by the oxide layer 16, thereby maintaining the integrity and electrical quality of the substrate. In addition, it should be noted that if the stacked film 14 is composed of three or more dielectric materials, the etching step may remove a portion of the bottommost dielectric material 8 201027621 layer. As shown in FIG. 4, another etching process is performed to utilize The patterned photoresist layer 24 on the hard mask 22 is removed by an etchant consisting of sulfuric acid-hydrogen peroxide mixture (SPM). Then, as shown in FIG. 5, another etching is performed. Step, reuse An etchant composed of a mixture of an acid and hydrogen peroxide to remove the hard mask ❹ 22 on the surface of the stacked film 14. It should be noted that the present embodiment removes the circled photoresist layer 24 by a two-step process. Hard mask 22, but not limited to this method, but also in a spare time to make a balance of sulfuric acid and hydrogen peroxide mixture to simultaneously remove (four) bismuth layer and hard mask 22, this money is also The scope covered by the present invention. It should be noted that the above process of removing the oxide layer 16 of the stacked film 底层 underlayer to removing the hard mask 22 (for example, Fig. 3 to Fig. 0) can be performed in situ (in_situ). To achieve, for example, the steps of removing the bottom oxide layer 16, removing the patterned silk layer 24, and the faulty hard mask 22 are performed in the same side machine, especially in the bottom oxide layer 16 to remove the pattern. The chemical layer 24 is removed from the hard mask Μ in another trench. Alternatively, the steps of removing the bottom oxide layer 16, removing the photoresist layer 24, and removing the hard mask 22 are performed in the same manner, but the three steps are all performed. In the same _ slot in the same machine. To = 疋According to another embodiment of the present invention, the completed (10) stacked thin film, 201027621, can be integrated into a general MOS transistor process to produce a 〇 〇 NOS memory structure. This is also within the scope of the present invention. Please refer to FIG. 6 to FIG. 13 , and FIG. 6 to FIG. 13 are another embodiment of the present invention, integrating a SONOS memory and a gold. Schematic diagram of a process of an oxy-semiconductor (MOS) transistor. As shown in FIG. 6, a semiconductor substrate 32 is provided, on which a memory region 46 and a logic region 48 are defined, and the semiconductor substrate 32 can be made of 矽, 坤化_GaN a substrate composed of an insulating layer, a stray layer, a layer of enamel or other semiconductor substrate material. A stacked film 34 is then deposited simultaneously on the memory region 46 and logic region 48 on the semiconductor substrate 32. The stacked film 34 may be composed of a plurality of layers of material, and each of the layers may comprise various dielectric materials such as oxides, nitrides, oxynitrides, metal oxides, or combinations thereof. In the present embodiment, the stacked film 34 is preferably selected from a three-layer structure composed of an oxide-nitride-oxide. The 〇N〇 stacked film mainly comprises a bottommost oxide layer 36, a nitride layer 38 is disposed on the oxide layer 36, and another oxide layer 40 is overlaid on the nitride layer 38, and the thickness of the three layers of the stacked film is relatively thin. Preferably, it is from about 1 to 300 angstroms, preferably 18 angstroms. However, the stacked film 34 is not limited to three layers and the material of each layer may not overlap with the materials of the other layers. Then, a hard mask 42 composed of a tantalum nitride layer is deposited and covers the stacked film 34 of the memory region 46 and the logic region 48, and then a patterned photoresist layer 44 is formed on the hard mask of the memory region 46. 42. As shown in FIG. 7 'to perform a process of engraving, the photoresist layer 44 of the memory region 46 is used as an etch mask portion to remove the hard mask 42 of the memory region 46 and the two layers of the stacked film 34. The oxide layer 4 〇 and the portion of the nitride layer % that is not covered by the hard mask 42 and completely removes the hard mask 42 of the logic region 48 and the oxide layer 4 and the nitride layer of the two layers on the stacked film 34 . In other words, the stacked thin layer 34 of the body region 46 has the underlying oxide layer 36 and the patterned hard mask 42, oxide layer 40 and nitride layer 38 disposed on the oxide layer 36 after the above-described residual process. The logic region 48 leaves only the underlying oxide layer 36. In the present embodiment, the above-described process of removing the hard mask 42 and the oxide layer 40 and the nitride layer 38 is preferably performed by dry etching, for example, a plasma etching process. In addition, the patterned photoresist layer 44 can be selected to suit the desired photoresist material in accordance with the size of the desired exposure element. In the present invention, the patterned photoresist layer 44 is preferably selected from a deep ultraviolet (DUV) photoresist material, but is not limited thereto, and may be selected for a 365 nm wavelength Mine resistance material according to process requirements. All of them are covered by the present invention. If the stacked film 34 is composed of a dielectric material of more than three layers, the etching step can remove all of the hard mask 42 and the uppermost dielectric material layer. The portion of the dielectric material layer that is not covered by the hard mask 42. As shown in Fig. 8, 'the other-(four) process is performed, using the patterned photoresist layer 44 as a mask and then performing a process to partially remove the oxide layer 36 and the logic region of the bottom layer of the memory stack 34. The remaining oxide layer %' exposes a portion of the semiconductor substrate 32 of the memory 146 and the entire half (four) substrate 32 of the logic region. The present invention is preferably a wet etching process, and the etching solution in the wet etching process is preferably an oxide etching buffer (Buffer oxidation etchant) which is prepared by mixing HF and ΝΗβ in different proportions. , ΒΟΕ). Although the dry etching process, such as the plasma etching process, may also be used to partially remove the oxide layer 36 of the underlying film 34 of the memory region 46 and the oxide layer 36 remaining in the logic region 48, the wet etching process does not damage the oxide layer 36. The substrate being covered maintains the integrity and electrical quality of the substrate, ensuring the quality of the gate oxide layer subsequently formed in logic region 48. It should also be noted that if the stacked film 34 is composed of three or more layers of dielectric material, the etching step partially removes the bottommost material layer of the memory film 46 and the bottommost material layer remaining in the logic region 48.
如第9圖所示，先進行另一蝕刻製程，利用由硫酸與過 氧化氫混合物（sulfuric acid-hydrogen peroxide mixture，SpM) 所組成的蝕刻劑來去除記憶體區46的圖案化光阻層44。然 後如第10圖所示，進行另一蝕刻步驟，再利用硫酸與過氧 化氫混合物所構成的蝕刻劑來去除記憶體區46堆疊薄臈％ 表面的硬遮罩42。如同上述之實施例，本實施例雖以兩次蝕 刻步驟分別去除圖案化光阻層44與硬遮罩42，但不侷限這 個作法，又可在一次蝕刻製程中以硫酸與過氧化氫混合物所 構成的触刻劑來同時去除圖案化光阻層44與硬遮罩42，此 作法也屬本發明所涵蓋的範圍。另外需注意的是’上述由去 除堆疊薄膜34底層的氧化層36至去除硬遮罩42為止（例如 第7圖至第9圖）的製程又可以現場(in_situ)進行的方式來達 12 201027621 成，例如，去除底部氧化層36、去除圖案化光阻層44及去 除硬遮罩42的步驟係於同一餘刻機台中進行，尤其去除底 部氧化層36在一蝕刻槽中進行而去除圖案化光阻層44與去 除硬遮罩42在另-_槽中完成。或者，去除底部氧化層 36、去除圖案化光阻層44及去除硬遮罩42的步驟雖於同一 蝕刻機台中進行，但三步驟皆於同一機台中的不同蝕刻样 進行。 ㈢As shown in FIG. 9, another etching process is performed to remove the patterned photoresist layer 44 of the memory region 46 by using an etchant composed of a sulfuric acid-hydrogen peroxide mixture (SpM). . Then, as shown in Fig. 10, another etching step is performed, and an etchant composed of a mixture of sulfuric acid and hydrogen peroxide is used to remove the hard mask 42 on the surface of the memory region 46. As in the above embodiment, although the patterned photoresist layer 44 and the hard mask 42 are respectively removed by two etching steps, the method is not limited, and a mixture of sulfuric acid and hydrogen peroxide can be used in an etching process. The etchant is formed to simultaneously remove the patterned photoresist layer 44 from the hard mask 42, which is also within the scope of the present invention. It should also be noted that the above process of removing the oxide layer 36 from the bottom layer of the stacked film 34 to the removal of the hard mask 42 (for example, Figures 7 to 9) can be performed in the field (in_situ) to reach 12 201027621. For example, the steps of removing the bottom oxide layer 36, removing the patterned photoresist layer 44, and removing the hard mask 42 are performed in the same chamber, and in particular, the bottom oxide layer 36 is removed in an etching bath to remove the patterned light. The resist layer 44 and the removal of the hard mask 42 are completed in another trench. Alternatively, the steps of removing the bottom oxide layer 36, removing the patterned photoresist layer 44, and removing the hard mask 42 are performed in the same etching machine, but the three steps are performed on different etching samples in the same machine. (3)
如第11圖所示’依序形成一閘極氧化層5〇與一多晶矽層 52並覆蓋記憶體區46的圖案化堆疊薄膜34及記憶體區46 與邏輯區48的半導體基底32。在本實施例中，多晶矽層52 的厚度係介於1300至2500埃，較佳為175〇埃。另需注意 的是，若未使用沈積方式形成閘極氧化層5〇而是利用埶氧 化法形成閘極氧化層5〇時’由於熱氧化法只會消耗單晶石夕 或多晶碎而產生氧化層，堆㈣膜34上方與侧壁並不會為 閘極氧化層5G所覆蓋，此作法也屬本發明所涵蓋的範圍。 圖 第2圖所示，進行一微影暨餘刻製程，例如先形成一 圖案化光阻層（圖未示)在記憶體區#及邏輯區Μ，並利用 案化光阻層當作遮罩進行—崎製程，去除部分記憶體區 IZtZ52' 50 34 ^ 2 r層m部分邏輯區48的多晶石夕層52與間極氧 化層50。此触刻製程較佳暴露出記憶體區46的部分氣化發 13 201027621 層38並同時於邏輯區48形成一由圖案化多晶矽層&與閘 極氧化層50所構成的閘極電極。 如第13圖所示，進行一側壁子製程，例如先沈積一氧化 矽層或氮化矽層在半導體基底32上並以回蝕刻方式去除部 分氧化矽層或氮化矽層，以於記憶體區46的圖案化多晶矽 層52、閘極氧化層5〇以及氧化層4〇侧壁以及邏輯區牦 ❹ 雜電極㈣分卿成—㈣子56。然後制用記憶體區 46的侧壁子56#作遮罩進行另刻製程，以去除氧化 4〇y的部分氮化層38及氧化層36。隨後可依照產品需求於 邏輯區48的半導體基底32 +形成輕推雜源極/没極（圖未示 與源極/没極區域（圖未示），並選擇性在記憶體區Μ同時 成相對應的輕_源極極與祕/祕區域，以於記 區46形成一 S〇N〇S記憶體以及於邏輯區48形成- _ 電晶體。 其中，製作輕摻雜源極沒極與源極/汲極區域的作法可依 循-般製作廳電晶體的製程來完成。例如，可先利用： 壁子56㈣=树—__子雑製程，以 56兩側的半導體基底&中八 千 後形成-主側壁子（圖未^㈣成—輕掺雜源極/沒極。然 子當作遮罩進行-重摻雜壁子56周圍並利用主侧壁 域。其中’側壁子56 ^佈植製程以形成源極/汲極區 、 輕摻雜源極/汲極、主側壁子以及源 201027621 極/汲極區域的製程順序可依製程需求 屬本發明所涵蓋的範圍。最後可再進行或調整’此皆 例如先覆蓋一層間介電層於記憶體區屬内連線製程’ 層^複數個連接閑極電極與記憶體的接觸指塞於層間介電 參 Ο 綜上所述，本發明主要在蝕刻一堆疊 遮罩在堆疊薄膜表面，缺德以雨俨彳 、則覆蓋一硬 的堆聂an 、Μ財縣形成所需 隹且圖案。以本發明所揭露的製作方式為例，第 要去除部㈣硬料及堆㈣麟底相切所有介/ :而第二次_則去除堆#薄膜最底層的部分介電層。由 可的氮切硬遮罩具有較佳_著力，本發明 氮化石夕硬遮罩及上述的兩段式餘刻製程絲刻堆叠 圖案時，如此即可避錢時於堆疊薄膜中產生底切現象。 以上所述僅為本㈣之較佳實施例，凡依本發明申請專 &圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 為本發明較佳實施例製作一圖案化堆疊薄膜 第1圖至第5 之示意圖。 圖至第13圖為本發明另-實施例整合-SONOS記憶體 15 201027621 與一互補式金氧半導體(CMOS)電晶體之製程示意圖。 【主要元件符號說明】 12 半導體基底 14 堆疊薄膜 16 氧化層 18 氮化層 20 氧化層 22 硬遮罩 24 圖案化光阻層 32 半導體基底 34 堆疊薄膜 36 氧化層 38 氮化層 40 氧化層 42 硬遮罩 44 圖案化光阻層 46 記憶體區 48 邏輯區 50 閘極氧化層 52 多晶矽層 56 侧壁子 ❹ 16As shown in Fig. 11, a gate oxide layer 5 and a polysilicon layer 52 are sequentially formed and cover the patterned stacked film 34 of the memory region 46 and the memory region 46 and the semiconductor substrate 32 of the logic region 48. In the present embodiment, the thickness of the polysilicon layer 52 is between 1300 and 2500 angstroms, preferably 175 angstroms. It should also be noted that if the gate oxide layer 5 is not formed by deposition, but the gate oxide layer 5 is formed by the ruthenium oxidation method, 'the thermal oxidation method only consumes single crystal or polycrystalline grains. The oxide layer, the top (4) of the film 34 and the sidewalls are not covered by the gate oxide layer 5G, and this is also within the scope of the present invention. As shown in Fig. 2, a lithography and engraving process is performed, for example, a patterned photoresist layer (not shown) is formed in the memory region # and the logic region, and the photoresist layer is used as a mask. The mask is subjected to a process of removing the memory layer IZtZ52' 50 34 ^ 2 r layer m portion of the logic region 48 of the polycrystalline layer 52 and the interpole oxide layer 50. The etch process preferably exposes a portion of the gasification of the memory region 46 and simultaneously forms a gate electrode of the patterned polysilicon layer & and the gate oxide layer 50 in the logic region 48. As shown in FIG. 13, a sidewall process is performed, for example, depositing a hafnium oxide layer or a tantalum nitride layer on the semiconductor substrate 32 and removing a portion of the hafnium oxide layer or the tantalum nitride layer by etching back to the memory. The patterned polysilicon layer 52 of the region 46, the gate oxide layer 5 and the sidewalls of the oxide layer 4, and the logic region doped electrodes (4) are divided into - (four) sub-56. Then, the sidewall spacer 56# of the memory region 46 is used as a mask for an additional process to remove the partially nitrided layer 38 and the oxide layer 36 which are oxidized. Then, according to the product requirements, the semiconductor substrate 32 + of the logic region 48 can be formed into a light-pushing source/no-pole (not shown in the source/no-polar region (not shown), and selectively formed in the memory region simultaneously. Corresponding light source and secret/secret regions, forming a S〇N〇S memory in the recording area 46 and forming a —_ transistor in the logic region 48. Among them, the lightly doped source and the source are fabricated. The pole/bungee region can be done in accordance with the process of fabricating the hall crystal. For example, it can be used first: wall 56 (four) = tree - __ sub-process, with 56 semiconductor substrates on both sides & After the formation - the main sidewall (Fig. not ^ (4) into - lightly doped source / no pole. However, as a mask - heavy doping around the wall 56 and utilize the main sidewall domain. Where 'wall side 56 ^ The process sequence of the implantation process to form the source/drain regions, the lightly doped source/drain electrodes, the main sidewalls, and the source 201027621 pole/drain regions may be within the scope of the present invention depending on the process requirements. Perform or adjust 'this is for example, first covering an inter-layer dielectric layer in the memory region to interconnect the process' layer The contact between the connection of the idle electrode and the memory refers to the inter-layer dielectric Ο. In summary, the present invention mainly etches a stack of masks on the surface of the stacked film, and the rain is covered with a hard pile. An Μ, Μ 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县The bottommost portion of the dielectric layer. The hard mask can be cut by the nitrogen, and the nitrite hard mask of the present invention and the two-stage process of the above-mentioned two-step process are stacked to avoid money. The undercut phenomenon occurs in the stacked film. The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the application according to the present invention are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 13 is a schematic view showing a patterned stacked film according to a preferred embodiment of the present invention. FIG. 13 to FIG. 13 are another embodiment of the present invention. The integrated-SONOS memory 15 201027621 and a complementary Process diagram of metal oxide semiconductor (CMOS) transistor [Main component symbol description] 12 semiconductor substrate 14 stacked film 16 oxide layer 18 nitride layer 20 oxide layer 22 hard mask 24 patterned photoresist layer 32 semiconductor substrate 34 stacked film 36 oxide layer 38 nitride layer 40 oxide layer 42 Hard mask 44 patterned photoresist layer 46 memory region 48 logic region 50 gate oxide layer polysilicon layer 56 sidewall spacer 16