201025427 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種氮化（nitrify)方法，特別是指一種 金氧半場效電晶體（metal-oxide-semiconductor field effect transistor;簡稱 MOSFET)之閘極 介電層的氮化方法。 【先前技術】 為因應近十年來可搆帶型（portable)數位電子產品的需 # 求，電子零組件（如，MOSFET)於元件尺寸上則需微型化以 滿足前述需求。隨著MOSFET元件尺寸的微縮，其於結構 上與電性上的改變則分別有閘極長度之縮短與偏壓的降 低。因此’閘極介電層（gate dielectric layer)就需要不斷地 變薄以達到MOSFET之閘極對通道的調控性。然而，呈電 容結構之MOSFET在閘極介電層薄化後所面臨的問題，最 常見者則是因介電層之介電常數（k值）的不足而使得閘極介 電層無法抵擋電子穿遂效應（tunneiing effect)，並導致元件 • 的崩潰。 為解決前述電子穿遂效應所衍生的問題，唯有訴諸高k 介電材料（如，金屬氧化物）。大部分的金屬氧化物和矽基板 間並沒有相容的接面；此外，大氣中的氧和雜質容易往下 ㈣至其接面處並於其接面處產生—低k值的金屬梦化物 H述之金屬⑦化物所衍生㈣題，収因其内部存在 有大量的斷鍵與缺陷而導致熱載子效應顯著、漏電流嚴重 與元件電性不佳等問題。因此，目前常見的解決方法，則 3 201025427 是藉由氮化介電層的方式來降低金屬氧化物介電層内部的 斷鍵與缺陷。 對閘極介電層施予氮化處理雖然可防止複晶矽（p〇lySi) 閘極中的載子（carriers)和外來的氧原子等雜質的侵入並降低 接面的形成’亦可降低因熱載子效應所導致的電性衰退之 風險。然而，由於在近年來的奈米級元件製程中，閘極介 電層的厚度越來越薄，經過氮化處理之後，容易使得氮原 子接近矽基板表面，並於金屬氮氧化層本體上帶有大量的 缺陷。因此，當載子接近矽基板表面時，載子遷移率 (mobility)將因矽基板表面處所產生的載子庫倫散射（c〇lunin scatter)而衰退，並使得整體元件的驅動電流值下降。為避 免氮離子於氮化處理後過度地靠近矽基板表面，將氮離子 侷限於閘極介電層的上方是必要的課題。以現階段的氮化 處理，則可見有熱氮化或高能量電流離子佈植（i〇n implantation)之氮化等方法。 一般的熱氮化法主要是透過熱能在長時間下的驅動以 將氮原子摻雜入閘極氧化層中。此種長時間在高溫環境下 實施的熱氮化處理，容易於矽基板表面成長低k值的接 面。此低k值的接面不僅增加了等效氧化物層的厚度 (effective oxide thickness，簡稱 EOT);此外，接面的結構 過於鬆散，亦使得元件操作時容易產生崩潰的問題。 另’採用快速熱退火（rapid thermal annealing，簡稱 RTA)雖然可以降低前述低k值接面的問題。然而，RT 法於閘極金屬氧化層中形成高濃度的摻雜，其抑制雜質擴 201025427 散至矽基板表面的貢獻度亦有限。前述RTA相關技術文 獻，可見 Renee Nieh 等人於 APPLIED PHYSICS LETTER, Vol. 81, No. 9，P 1663〜1665 所揭露的 Evaluation of silicon surface nitridation effects on ultra-thin Zr〇2 gate dielectrics 文章。 此外，電流離子佈植之氮化處理，主要是使用高能量 將氮離子注入金屬氧化物介電層中。其雖然可於金屬氧化 物中摻雜高濃度的氮離子。然而，使用高能量的摻雜，不 φ 僅過度地損傷介電層；此外，亦容易使得所摻雜的氮離子 穿過介電層並擴散至矽本體，導致元件可靠度大幅地下 降。 經上述說明可知，對MOSFET之閘極介電層施予高濃 度的氮離子佈植，同時，亦需將氮離子維持在介電層表面 以避免元件性能因氮離子擴散至半導體基板表面而受到影 響，是當前開發MOSFET相關領域者所待克服的課題。 【發明内容】 φ 因此，本發明之目的，即在提供一種金氧半場效電 晶體之閘極介電層的氮化方法。 於是，本發明金氧半場效電晶體之閘極介電層 的氮化方法，該金氧半場效電晶體是形成於一半導體 基板上，該方法包含以下步驟： (a) 於該半導體基板上形成一含有Hf、A1與Ο的閘極 介電層； (b) 於該閘極介電層上形成一閘極； 201025427 (C)於該半導體基板形成相間隔設置的一源極 一汲極（drain); (d) 實施含氮電漿離子佈植（piasma immersj〇n i〇n implantation，簡稱 pm);及 (e) 實施退火處理以完成氮化。 本發明之功效在於，可對M0SFET之閘極介電層提供 高濃度的氮離子佈植，同時，亦可將氮離子維持在介電層 表面’藉以避免元件性能因氮離子擴散至半導體基板表面 而受到影響。 【實施方式】 <發明詳細說明> 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例與五個具體例的詳細 說明中，將可清楚的呈現。 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中，類似的元件是以相同的編號來表示。 參閱圖1、圖2與圖3，本發明金氧半場效電晶體 之閘極介電層的氮化方法之一較佳實施例，該金 氧半場效電晶體是形成於一半導體基板2上，該方法包含 以下步驟： (a) 於該半導體基板2上形成一含有jjf、Al與Ο的閘 極介電層3 ; (b) 於該閘極介電層3上形成—閘極4 ; (c) 於該半導體基板2形成相間隔設置的一源極5與一 201025427 一及極6 ; (d) 實施含氮電漿離子佈植；及 (e) 實施退火處理以完成氮化。 本發明該步驟（d)不限於實施該步驟（a)之前或實施該步 驟（a)之後’在本發明一具體例中，該步驟（d)是在該步驟（匕) 之後實施。 適用於本發明該步驟（a)之閘極介電層3是HfxAly〇⑽_x_ y’以原子百分比計，l〇<x<15; 15<y<20;適用於本發 • 明該步驟（a)的半導體基板2是選自矽（Si)基板、鍺（Ge)基板 或前述基板之合金，且前述基板之合金以原子百分比計， 鍺含量是小於90 at%。 較佳地，於該步驟（a)〜(e)之後更包含一步驟（e)，，該步 驟（e)’是形成一保護層7以覆蓋該源極5、汲極6、閘極4 與半導體基板2,並形成複數分別供該源極5、汲極6及閘 極4與外界一電源電性連接的接點插塞（c〇ntact plug)8。 較佳地，對一被引入一射頻真空系統9之反應腔體91 鲁 内的含氮氣體分子團92提供一射頻功率，以使該含氮氣體 分子團92形成一含氮電漿93,且該含氮電漿93是經由該 射頻真空系統9的一負偏壓被引導至該半導體基板2，進而 完成該步驟（d)之含氮電漿離子佈植。在本發明該較佳實施 例中’是由一.射頻供應器（R.F. P〇Wer SUpply)94所提供的射 頻功率以預先形成電漿，並透過設置於該射頻真空系統9 的天線（antenna)95將該預先形成的電將引至該反應腔體91 中；同時，所導入的含氮氣體分子團92因該射頻功率而被 7 201025427 解離為含氮電漿93。 此處值得一提的是，當該射頻功率過低時，不僅不易 點燃電漿，且須延長操作時間；反之，當該射頻功率過高 時，則會使得該反應腔體91的溫度上升，致使所佈植的離 子在元件中持續地向該半導體基板2的方向擴散。因此， 更佳地，該射頻功率是介於15〇 w〜6〇〇 w之間；該反應腔 體的工作壓力是介於！ mTorr〜〇」mT〇rr之間；該含氛氣體 刀子團的抓量是介於24 seem〜240 seem之間；該步驟（句 的實施時間是介於1分鐘〜2〇分鐘之間。 又值得一提的疋，當佈植能量過小時，該步驟（d)所實 施的含氮電漿離子佈植之濃度將不足，無法有效地氮化該 閘極介電層3;反之’當佈植能量過高時，該步驟⑷所產生 的含氮電漿離子將過度地進入該半導體基板2並損空元 件，以使得載子遷移率下降。因此，更佳地，該負偏壓是 一脈衝型之負偏壓，且該負偏壓是介於丨κν〜ι〇 κν之間 (即’佈植能量是介於！ KeV〜10 KeV之間)；脈衝條件是 介於Η) Μ〜1GG 之間。在本發明該較佳實施射，該脈 衝型負偏壓是由該射頻真空系統9的_脈衝波產生器（puke generator)96 所產生。 此外，當退火時間過長時，含氮離子將因其擴散距離 的增加而被引進該半導體基板2;反之，當退火時間不足或 退火溫度過低時，會使得含氮離子無法有效地與該問極介 電層3 i生鍵、结。因此，更佳地，該步驟⑷之退火溫度是 介於75〇°C〜95代之間；該步驟⑷之退火時間是介於5 201025427 sec〜90 sec之間。 又更佳地，該射頻功率是介於250 W〜450 W之間；該 反應腔體的工作壓力是介於0.8 mTorr〜0.4 mTorr之間；該 含氮氣體分子團的流量是介於30 seem〜150 seem之間；該 步驟（d)的實施時間是介於1分鐘〜15分鐘之間；該負偏壓 是介於1·5 KV〜7.5 KV之間（即，佈植能量是介於1.5 KeV 〜7.5 KeV之間）；該步驟（e)之退火溫度是介於800°C ~ 900 °C之間。 φ 〈具體例> 參閱圖1~圖3，本發明金氧半場效電晶體之閘極 介電層的氮化方法之一具體例 1，是簡單地說 明於下。 首先，利用 Hf[OC(CH3)3]2[OC(CH3)2CH2OCH3]2[以下 簡稱 Hf(OtBu)2(mmp)2]與 Al[OCH(CH3)2]3[以下簡稱 Al(0-i-Pr)3]作為反應氣體源，並透過有機金屬化學氣相沉積法 (metal-organic chemical vapor deposition，簡稱 MOCVD)於 • 該半導體基板2上形成該閘極介電層3;在本發明該具體例 1中，該半導體基板2是一 P型矽基板；Hf(OtBu)2(mmp)2 與Al(0-i-Pr)3的氣體流量比是1 : 1 ;該閘極介電層3是厚 度約2 nm的Hf14Al18068。接著，於該閘極介電層3上形成 該閘極4 ;在本發明該具體例1中，該閘極4是一厚度約 50 nm 的 TaN。 將上述形成有TaN的半導體基板2放置於該射頻真空 系統9的反應腔體91中。於該反應腔體91内引入流量約 201025427 84 SCCm的N2，且自該射頻供應器％提供約期w的射頻 功率以維持該反應腔趙91的工㈣力為Q6 mw並完成 該pm技術。此外，對完成該Pm技術的半導體基板2施予 快速熱敎以完減化處理。在本發明該具_】中偏 壓為-2.5KV(即，佈植能量為25KeV);佈植時間為$分 鐘；脈衝條件之高電位（·2·5 KV)與低電位V)分別為10 μ8 與l〇ms，退火溫度與退火時間分別為85代與％咖。 進一步地，於該半導體基板2並位於該間極介電層3 與間極4的兩側佈植As離子以形成該源極$魏極6。最 後，於該半導趙基板2上形成該保護層7並形成該等分別 =閉極4、源極5與汲極6與外界電源電性連接的接點插 塞8。在本發㈣具體们巾，該金氧半場效電晶體是- n 型 MOSFET。 本發明金氧半場祕發 的氮 ’大致上相同於該具體例 佈植時間為1 0分鐘。 晶體之閘極介電層的氮 大致上相同於該具體例 佈植時間為1 5分鐘。 電晶體之閘極介電層的氮 ’大致上相同於該具體例 偏壓為-3·5 KV(即，佈植 電晶體之閘極介電層的氮 嘴效電日日體之閘極介電 化方法之一具體例2 1。其不同處是在於， 〇 本發明金氧半場效電 化方法之一具體例3 1。 其不同處是在於， 本發明金氧半場效 化方法之一具體例4 2。 其不同處是在於， 能量為3.5KeV)。 本發明金氧半場效 10 201025427 化方法之一具體例 5 ’大致上相同於該具體例 2。其不同處是在於，偏壓為-5.0 KV(即，佈植 能量為5.0KeV)。 本發明該等具體例是簡單地整理於下列表 1 ·中。 表1· 具體例 佈植時間（min) 佈植能量（KeV) 偏壓（KV) 1 5 2.5 -2.5 2 10 2.5 -2.5 3 15 2.5 -2.5 4 10 3.5 -3.5 5 10 5.0 -5.0 <比較例> 用來與本發明該等具體例相比較的一比較例， 大致上相同於該等具體例。其不同處是在於， 該比較例是未實施有該步驟（d)。 <分析數據> 參閱圖4 ,由平帶電壓（flat_band v〇Uage，簡稱Vfb)差 參 對佈植時間的分析曲線圖顯示可知，該比較例在_2 V〜2 v 的分析條件下所取得的約高達7 2 mV。反觀與本發明 該具體例1〜3在相同的分析條件下所取得的^作可自67 mV下降至5.3 mV。經前述說明可知，分別實施過〇、卜 10、15力鐘的ΡΠΙ技術並配合退火處理的m〇sfet之遲滞 現象m約ι·9 mV[即’ a2 _ 5 3) mv = i 9岡。其遲 滯現象減緩的原因主要是在於，未經實施pm技術之開極介 電層（即’ ΗΜ10材料）本身因内部鍵結不完全而存在有大量 11 201025427 的空缺（vacancy) 〇 當外加正電壓時，半導體基板内的電子將受正電場的 吸引而移動至閘極介電層内並被空缺捕捉（trap);當外加負 電壓時，則原本陷於空缺的電子將受到負電場的影響而被 釋放（de-trap)出來。因此，ΡΠ技術之處理有助於缺陷的修 補；此外，隨著ΡΙΠ技術之處理時間的增加，遲滯現象減緩 的幅度越大。 參閱圖5，由△ V fb對佈植能量之分析曲線圖顯示可 知，本發明該具體例2、4〜5在相同的分析條件下所取得的 △ Vfb分別為5.7 mV、6.3 mV與6· 1 mV。雖然隨著佈植能 量的增加，其遲滯現象將因閘極介電層内部所產生的些許 損傷而稍微地提昇；然而，與未實施ΡΠΙ技術的該比較例相 比較之下，其遲滯現象仍獲得大幅的改善。 本發明是採用福勒一諾德漢電子穿隧模型（Fowler-Nordheim electron tunneling, model)之 F-N 應力（F-N stress) 測試來分析該比較例與本發明該等具體例之信賴性（stress induced leakage current ;簡稱 SILC)。 參閱圖6，由漏電流（leakage current)比值對應力時間之 分析曲線圖顯示可知，該比較例在閘極電壓（VG)為-0.31 V 的分析條件下，對其閘極介電層施予25分鐘（即，1500秒） 之-14 MV/cm的定電場所取得之漏電流比值已趨近0.60。反 觀與本發明該具體例1〜3在相同的分析條件下所取得的漏 電流比值是維持在0.15〜0.20之間。201025427 VI. Description of the Invention: [Technical Field] The present invention relates to a nitrify method, and more particularly to a metal-oxide-semiconductor field effect transistor (MOSFET) A method of nitriding a gate dielectric layer. [Prior Art] In response to the demand for portable digital products in the past decade, electronic components (e.g., MOSFETs) need to be miniaturized in terms of component sizes to meet the aforementioned requirements. As the size of the MOSFET component is reduced, its structural and electrical changes have a shortened gate length and a reduced bias voltage, respectively. Therefore, the gate dielectric layer needs to be continuously thinned to achieve the gate-to-channel regulation of the MOSFET. However, the problem faced by the MOSFET with a capacitor structure after the gate dielectric layer is thinned is that the gate dielectric layer cannot resist the electron due to the dielectric constant (k value) of the dielectric layer. The tunneling effect and the collapse of the component. In order to solve the problems caused by the aforementioned electron-piercing effect, only high-k dielectric materials (such as metal oxides) are resorted to. Most of the metal oxides and tantalum substrates do not have compatible joints; in addition, the oxygen and impurities in the atmosphere are easy to go down (4) to their junctions and at their junctions - low-k metal dreams The problem of (4) derived from the metal 7 compound described in H is due to the existence of a large number of broken bonds and defects in the interior, resulting in significant hot carrier effect, serious leakage current and poor electrical properties of the device. Therefore, the current common solution is to reduce the bond and defects inside the metal oxide dielectric layer by nitride dielectric layer. The nitriding treatment of the gate dielectric layer can prevent the intrusion of impurities such as carriers and external oxygen atoms in the gate of the p〇lySi gate and reduce the formation of the junction. The risk of electrical decline due to the hot carrier effect. However, in the nano-scale device process in recent years, the thickness of the gate dielectric layer is getting thinner and thinner. After the nitriding treatment, the nitrogen atom is easily brought close to the surface of the germanium substrate and is carried on the body of the metal oxynitride layer. There are a lot of defects. Therefore, when the carrier is close to the surface of the substrate, the carrier mobility will be degraded by the carrier cunning scattering generated at the surface of the substrate, and the driving current value of the entire element is lowered. In order to prevent nitrogen ions from being excessively close to the surface of the germanium substrate after the nitriding treatment, it is necessary to limit the nitrogen ions to the upper side of the gate dielectric layer. At the current stage of nitriding treatment, there are methods such as thermal nitriding or nitriding of high energy current ion implantation. The general thermal nitridation method is mainly to drive nitrogen atoms into the gate oxide layer by driving heat for a long time. Such a thermal nitriding treatment which is carried out in a high temperature environment for a long period of time is easy to grow a low-k junction on the surface of the ruthenium substrate. This low-k junction not only increases the thickness of the equivalent oxide layer (EOT); in addition, the structure of the junction is too loose, which also makes the component susceptible to collapse during operation. Another use of rapid thermal annealing (RTA) can reduce the aforementioned problem of low-k junctions. However, the RT method forms a high concentration of doping in the gate metal oxide layer, and its contribution to suppressing the diffusion of the impurity to the surface of the germanium substrate is also limited. For the aforementioned RTA related technical literature, the evaluation of silicon surface nitridation effects on ultra-thin Zr〇2 gate dielectrics disclosed by Renee Nieh et al. in APPLIED PHYSICS LETTER, Vol. 81, No. 9, P 1663~1665. In addition, the nitriding treatment of current ion implantation mainly uses high energy to implant nitrogen ions into the metal oxide dielectric layer. It can be doped with a high concentration of nitrogen ions in the metal oxide. However, with high energy doping, φ only excessively damages the dielectric layer; in addition, it is easy to cause the doped nitrogen ions to pass through the dielectric layer and diffuse to the ruthenium body, resulting in a significant drop in component reliability. According to the above description, a high concentration of nitrogen ion implantation is applied to the gate dielectric layer of the MOSFET, and nitrogen ions are also required to be maintained on the surface of the dielectric layer to avoid component performance due to diffusion of nitrogen ions onto the surface of the semiconductor substrate. The impact is a problem to be overcome in the current development of MOSFET-related fields. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a method of nitriding a gate dielectric layer of a metal oxide half field effect transistor. Therefore, in the nitriding method of the gate dielectric layer of the MOS field-effect transistor of the present invention, the MOS field-effect transistor is formed on a semiconductor substrate, and the method comprises the following steps: (a) on the semiconductor substrate Forming a gate dielectric layer containing Hf, A1, and germanium; (b) forming a gate on the gate dielectric layer; 201025427 (C) forming a source-drainage spaced apart from the semiconductor substrate (drain); (d) performing a nitrogen-containing plasma ion implantation (piasma immersj〇ni〇n implantation, referred to as pm); and (e) performing an annealing treatment to complete the nitridation. The invention has the advantages of providing high concentration of nitrogen ion implantation to the gate dielectric layer of the MOSFET, and also maintaining nitrogen ions on the surface of the dielectric layer to avoid component performance due to diffusion of nitrogen ions onto the surface of the semiconductor substrate. And affected. [Embodiment] <Detailed Description of the Invention> The foregoing and other technical contents, features and effects of the present invention will be apparent from the following detailed description of a preferred embodiment and five specific examples. Presentation. Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 1 , FIG. 2 and FIG. 3 , a preferred embodiment of a method for nitriding a gate dielectric layer of a gold oxide half field effect transistor is formed on a semiconductor substrate 2 . The method comprises the steps of: (a) forming a gate dielectric layer 3 containing jjf, Al and germanium on the semiconductor substrate 2; (b) forming a gate 4 on the gate dielectric layer 3; (c) forming a source 5 and a 201025427 one and a pole 6 spaced apart from each other on the semiconductor substrate 2; (d) performing nitrogen-containing plasma ion implantation; and (e) performing an annealing treatment to complete nitridation. This step (d) of the present invention is not limited to the implementation of the step (a) or after the step (a) is carried out. In a specific example of the present invention, the step (d) is carried out after the step (匕). The gate dielectric layer 3 suitable for the step (a) of the present invention is HfxAly〇(10)_x_y' in atomic percent, l〇<x<15;15<y<20; is applicable to the present invention. The semiconductor substrate 2 of a) is an alloy selected from the group consisting of a bismuth (Si) substrate, a germanium (Ge) substrate, or the above-described substrate, and the alloy of the above substrate has an yttrium content of less than 90 at%. Preferably, after the steps (a) to (e), a step (e) is further included, wherein the step (e) of forming a protective layer 7 covers the source 5, the drain 6 and the gate 4 And a semiconductor plug 2, and a plurality of contact plugs 8 for electrically connecting the source 5, the drain 6 and the gate 4 to a power source of the outside. Preferably, a nitrogen-containing gas molecular group 92 introduced into the reaction chamber 91 of the RF vacuum system 9 is supplied with a radio frequency power to cause the nitrogen-containing gas molecule group 92 to form a nitrogen-containing plasma 93, and The nitrogen-containing plasma 93 is guided to the semiconductor substrate 2 via a negative bias of the RF vacuum system 9, thereby completing the nitrogen-containing plasma ion implantation of the step (d). In the preferred embodiment of the invention, the RF power provided by a RF P〇Wer SUpply 94 is pre-formed into plasma and transmitted through an antenna disposed in the RF vacuum system 9. The pre-formed electricity is introduced into the reaction chamber 91; at the same time, the introduced nitrogen-containing gas molecular group 92 is dissociated into the nitrogen-containing plasma 93 by the 7201025427 due to the RF power. It is worth mentioning here that when the RF power is too low, not only the plasma is not easily ignited, but also the operation time must be prolonged; conversely, when the RF power is too high, the temperature of the reaction chamber 91 is increased. The ions implanted are caused to continuously diffuse in the direction of the semiconductor substrate 2 in the element. Therefore, more preferably, the RF power is between 15 〇 w and 6 〇〇 w; the working pressure of the reaction chamber is between! mTorr~〇"mT〇rr; the grip of the gas-containing knife group is between 24 seem~240 seem; the step (the execution time of the sentence is between 1 minute and 2 minutes). It is worth mentioning that when the implantation energy is too small, the concentration of the nitrogen-containing plasma ion implantation performed in the step (d) will be insufficient, and the gate dielectric layer 3 cannot be effectively nitrided; When the planting energy is too high, the nitrogen-containing plasma ions generated in the step (4) will excessively enter the semiconductor substrate 2 and damage the element, so that the carrier mobility is lowered. Therefore, more preferably, the negative bias is one. Pulse type negative bias, and the negative bias is between 丨κν~ι〇κν (ie 'planting energy is between ! KeV~10 KeV); pulse condition is between Η) Μ~ Between 1GG. In the preferred embodiment of the invention, the pulsed negative bias is generated by a puke generator 96 of the RF vacuum system 9. In addition, when the annealing time is too long, the nitrogen-containing ions will be introduced into the semiconductor substrate 2 due to the increase of the diffusion distance; conversely, when the annealing time is insufficient or the annealing temperature is too low, the nitrogen-containing ions may not be effectively combined with the Ask the very dielectric layer 3 i to bond, knot. Therefore, more preferably, the annealing temperature of the step (4) is between 75 ° C and 95 passages; and the annealing time of the step (4) is between 5 201025427 sec and 90 sec. More preferably, the RF power is between 250 W and 450 W; the working pressure of the reaction chamber is between 0.8 mTorr and 0.4 mTorr; the flow rate of the nitrogen-containing molecular group is between 30 seem Between ~150 seem; the implementation time of step (d) is between 1 minute and 15 minutes; the negative bias is between 1.5 KV and 7.5 KV (ie, the implant energy is between 1.5 KeV ~ 7.5 KeV); the annealing temperature of step (e) is between 800 ° C ~ 900 ° C. φ <Specific Example> Referring to Figs. 1 to 3, a specific example 1 of the nitriding method of the gate dielectric layer of the MOS field-effect transistor of the present invention is briefly described below. First, Hf[OC(CH3)3]2[OC(CH3)2CH2OCH3]2 [hereinafter referred to as Hf(OtBu)2(mmp)2] and Al[OCH(CH3)2]3 [hereinafter referred to as Al(0-) i-Pr) 3] as a reaction gas source, and forming the gate dielectric layer 3 on the semiconductor substrate 2 by metal-organic chemical vapor deposition (MOCVD); in the present invention In the specific example 1, the semiconductor substrate 2 is a P-type germanium substrate; the gas flow ratio of Hf(OtBu) 2 (mmp) 2 to Al (0-i-Pr) 3 is 1:1; the gate dielectric Layer 3 is Hf14Al18068 having a thickness of about 2 nm. Next, the gate 4 is formed on the gate dielectric layer 3; in the specific example 1 of the present invention, the gate 4 is a TaN having a thickness of about 50 nm. The above-described TaN-forming semiconductor substrate 2 is placed in the reaction chamber 91 of the radio frequency vacuum system 9. N2 having a flow rate of about 201025427 84 SCCm is introduced into the reaction chamber 91, and the RF power of about the period w is supplied from the RF supply unit to maintain the reaction force of the reaction chamber (Q4) to Q6 mw and the pm technique is completed. Further, the semiconductor substrate 2 which has completed the Pm technique is subjected to rapid enthalpy to complete the reduction process. In the present invention, the bias voltage is -2.5 KV (ie, the implantation energy is 25 KeV); the implantation time is $ minutes; the high potential of the pulse condition (·2·5 KV) and the low potential V) are respectively 10 μ8 and l〇ms, annealing temperature and annealing time were 85 generations and % coffee, respectively. Further, As ions are implanted on the semiconductor substrate 2 on both sides of the interposer dielectric layer 3 and the interpole 4 to form the source $Wei pole 6. Finally, the protective layer 7 is formed on the semiconductor substrate 2 and the contact plugs 8 respectively forming the closed-pole 4, the source 5 and the drain 6 electrically connected to the external power source are formed. In the hair of the present invention, the metal oxide half field effect transistor is an -n type MOSFET. The nitrogen 's of the golden oxygen half-time secret of the present invention is substantially the same as the specific example. The implantation time is 10 minutes. The nitrogen of the gate dielectric layer of the crystal is substantially the same as the specific example. The implantation time is 15 minutes. The nitrogen of the gate dielectric layer of the transistor is substantially the same as the bias of the specific example of -3.5 KV (ie, the gate of the nitrogen gate of the gate dielectric of the implanted transistor) One of the dielectricization methods is a specific example of the invention. The difference is that one of the gold oxide half field effect electrowinning methods of the present invention is specific example 31. The difference is that one of the specific examples of the gold oxide half field effect method of the present invention is 4 2. The difference is that the energy is 3.5KeV). One of the specific examples 5 of the method of the present invention is substantially the same as the specific example 2. The difference is that the bias voltage is -5.0 KV (i.e., the implantation energy is 5.0 KeV). These specific examples of the present invention are simply organized in the following list. Table 1· Specific examples Planting time (min) Planting energy (KeV) Bias (KV) 1 5 2.5 -2.5 2 10 2.5 -2.5 3 15 2.5 -2.5 4 10 3.5 -3.5 5 10 5.0 -5.0 <Comparative EXAMPLES A comparative example for comparison with the specific examples of the present invention is substantially the same as the specific examples. The difference is that this comparative example is not implemented with this step (d). <Analytical data> Referring to Fig. 4, the analysis of the plating time by the flat-band voltage (flat_band v〇Uage, abbreviated as Vfb) parameter shows that the comparative example is under the analysis condition of _2 V~2 v The result is about 7 2 mV. In contrast, the results obtained by the specific examples 1 to 3 under the same analysis conditions can be reduced from 67 mV to 5.3 mV. According to the above description, the hysteresis phenomenon of m〇sfet with the enthalpy of the 〇, 卜10, and 15 钟, and the annealing treatment is about ι·9 mV [that is, ' a2 _ 5 3) mv = i 9 . The main reason for the slowing of the hysteresis is that the open dielectric layer (ie, 'ΗΜ10 material) without the implementation of pm technology itself has a large number of 11 201025427 vacancy due to incomplete internal bonding. When the electrons in the semiconductor substrate are attracted by the positive electric field, they move into the gate dielectric layer and are trapped by the vacancy. When a negative voltage is applied, the electrons that are originally vacant will be affected by the negative electric field. De-trap it out. Therefore, the treatment of ΡΠ technology contributes to the repair of defects; in addition, as the processing time of ΡΙΠ technology increases, the hysteresis slows down more. Referring to Fig. 5, the analysis of the planting energy by ΔV fb shows that the ΔVfb obtained by the specific examples 2 and 4 to 5 of the present invention under the same analysis conditions are 5.7 mV, 6.3 mV and 6·, respectively. 1 mV. Although the hysteresis will increase slightly with the slight damage generated inside the gate dielectric layer as the energy of the implant increases, however, the hysteresis is still compared with the comparative example without the technique. Great improvement. The invention adopts the FN stress test of Fowler-Nordheim electron tunneling (model) to analyze the reliability of the comparative example and the specific examples of the present invention (stress induced leakage). Current ; referred to as SILC). Referring to FIG. 6, the analysis of the leakage current ratio versus the stress time shows that the comparative example is applied to the gate dielectric layer under the analysis condition that the gate voltage (VG) is -0.31 V. The leakage current ratio of the 14 MV/cm power station at 25 minutes (ie, 1500 seconds) has approached 0.60. The leakage current ratio obtained under the same analysis conditions as in the specific examples 1 to 3 of the present invention was maintained at between 0.15 and 0.20.
經前述說明可知，分別實施過0、5、10、15分鐘的P 12 201025427 皿技術並配合退火處理的MOSFET之漏電流比值可自〇6〇 下降至0.20。其元件信賴性獲得改善的主要原因是在於， 未經實施pm技術之閘極介電層（即，HfA10材料）本身内部 存在有大量缺陷，自閘極注入的電子極為容易藉由閘極介 電層内部的缺陷穿越過閘極介電層（trap_assisted current)本 身，致使漏電流量增加。然而，本發明該具體例1〜3因實 施pm技術與退火處理而得以修補閘極介電層内部的缺陷； 因此，本發明該具體例1~3的元件信賴性獲得有效的改 善。 參閱圖7,由漏電流比值對應力時間之分析曲線圖顯示 可知，本發明該具體例2、4、5在相同的分析條件下所取 得的漏電流比值分別為〇· 15、0_30與趨進〇.7〇。顯見該具 體例2、4之元件彳§賴性因實施p瓜技術與退火處理而獲得 改善。該具體例5雖然因較高的佈植能量而於其閘極介電 層内部引入額外的缺陷’以使得元件在25分鐘的信賴性測 試後之漏電流量增加。然而，比對圖5可知，該具體例5 所顯示的遲滯現象已明顯減緩；因此，本發明該具趙例5 是足以供應低操作電壓條件的電子產品使用。 參閱圖8，由低掠角X射線繞射（grazing incident x ray diffraction;簡稱GIXD)分析數據圖顯示可知，本發明該具 體例1〜3之閘極的繞射訊號峰在經過實施p瓜技術與退火處 理後仍維持不變，顯見該步驟（d)〜(e)並不會破壞其閘極原有 的晶隔排列。 本發明將氮化處理放在該步驟（b)之後實施，並且使用 13 201025427 PDI技術作為離子佈植的實施手段。與前技術所提及之高能 量電流離子佈植相比較之下，不僅因較低的佈植能量而減 少摻雜所帶來的傷害；此外’亦可以使用相對氮離子漠度 的摻雜劑量來控制氮離子的分布深度。因此，本發明之氮 化方法可修補閘極介電層内部的缺陷以改善遲滯現象；此 外，亦降低雜質或載子朝向半導體基板擴散的機率以減少 基板界面所產生的載子庫倫散射等問題，有效地改善元件 的信賴性。 综上所述，本發明金氧半場效電晶體之閘極介❹ 電層的氮化方法，可對M0SFET之閘極介電層提供高 濃度的氮離子佈植，同時，亦可將氮離子維持在介電層表 面，藉以避免元件性能因t離子擴散至半導體基板表面而 受到影響’故確實能達成本發明之目的。 惟以上所述者’僅為本發明之較佳實施例與具體例而 已’當不能以此限定本發明實施之範圍’即大凡依本發明 申請專利範圍及發明說明内容所作之簡單的等效變化與修 飾，皆仍屬本發明專利涵蓋之範_。 【圖式簡單說明】 圖1是一 7L件流程示意圖’說明本發明金氧半場效 電晶趙之閘極介電展沾甚 罨層的氮化方法之一較佳實施 例； 圖2是一延續圖1 較佳實施例； 的元件流程示意圖 ’說明本發明該 圖3是一局部剖視示意圖 說明本發明該較佳實施例 14 201025427 於實施含氮電漿離子佈植時所使用的一射頻真空系統； 圖4是一平帶電壓差對佈植時間之曲線圖，說明一比 較例與本發明一具體例1〜3的遲滯現象； 圖5是一平帶電壓差對佈植能量之曲線圖，說明本發 明該具體例2與一具髏例4〜5的遲滯現象； 圖6疋一漏電流比值對應力時間之曲線圖，說明該比 較例與本發明該具體例1〜3的元件信賴性； 疋漏電流比值對應力時間之曲線圖，說明木發 _ 明該具趙例2、4〜5的元件信賴性；及 本發 圖 8 9 _ γ 疋~~ IGXD分析數據圖，說明該比較例與本發明該 具體例1〜3之一關权从曰助从址 閘極的晶體結構。 附件1 . na， •圃7之漏電流比值對應力時間曲線圖的彩色對 照圖式。 附件2 ·圖8之IGXD分析數據圖的彩色對照圖式。As can be seen from the above description, the leakage current ratio of the P 12 201025427 dish technology and the anneal-treated MOSFET which have been implemented for 0, 5, 10, and 15 minutes, respectively, can be reduced from 〇6〇 to 0.20. The main reason for the improvement in component reliability is that there is a large number of defects in the gate dielectric layer (ie, HfA10 material) that is not implemented by pm technology, and electrons injected from the gate are extremely easy to be dielectrically gated. The defect inside the layer passes through the trap_assisted current itself, causing an increase in the amount of leakage current. However, in the specific examples 1 to 3 of the present invention, defects in the gate dielectric layer were repaired by the pm technique and the annealing treatment; therefore, the reliability of the components of the specific examples 1 to 3 of the present invention was effectively improved. Referring to FIG. 7, the analysis of the leakage current ratio versus the stress time shows that the leakage current ratios of the specific examples 2, 4, and 5 of the present invention under the same analysis conditions are 〇·15, 0_30, and trend, respectively. 〇.7〇. It is apparent that the components of the specific examples 2 and 4 are improved by the implementation of the p-tech technique and the annealing treatment. This specific example 5 introduces additional defects in the interior of its gate dielectric layer due to higher implantation energy to increase the amount of leakage current of the device after the 25-minute reliability test. However, as can be seen from the comparison of Fig. 5, the hysteresis phenomenon shown in the specific example 5 has been remarkably slowed down; therefore, the present invention 5 is an electronic product which is sufficient for supplying a low operating voltage condition. Referring to FIG. 8, the data of the grazing incident x ray diffraction (GIXD) analysis data shows that the diffraction signal peak of the gate of the specific example 1 to 3 of the present invention is implemented by the p-technical technique. After the annealing treatment, it remains unchanged. It is obvious that the steps (d) to (e) do not destroy the original crystal arrangement of the gate. The present invention implements the nitriding treatment after this step (b) and uses the 13 201025427 PDI technique as an implementation means for ion implantation. Compared with the high-energy current ion implantation mentioned in the prior art, not only the damage caused by doping is reduced due to the lower implantation energy; in addition, the doping dose relative to the nitrogen ion inversion can also be used. To control the distribution depth of nitrogen ions. Therefore, the nitriding method of the present invention can repair defects inside the gate dielectric layer to improve hysteresis; in addition, the probability of diffusion of impurities or carriers toward the semiconductor substrate is reduced to reduce the problem of carrier coulomb scattering caused by the substrate interface. , effectively improve the reliability of components. In summary, the nitriding method of the gate dielectric layer of the MOS field-effect transistor of the present invention can provide a high concentration of nitrogen ion implantation to the gate dielectric layer of the MOSFET, and can also be a nitrogen ion. It is maintained on the surface of the dielectric layer to prevent the element performance from being affected by the diffusion of t ions onto the surface of the semiconductor substrate. Thus, the object of the present invention can be achieved. However, the above description is merely a preferred embodiment and a specific example of the present invention, and is not to be construed as limiting the scope of the invention. And the modifications are still covered by the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a 7L process diagram illustrating a preferred embodiment of a nitridation method for a gate dielectric layer of a MOS transistor of the present invention; FIG. 2 is a BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a component flow diagram illustrating the present invention. FIG. 3 is a partial cross-sectional view showing a radio frequency used in the implementation of the nitrogen-containing plasma ion implantation of the preferred embodiment 14 201025427 of the present invention. FIG. 4 is a graph of a flat band voltage difference versus implantation time, illustrating a hysteresis phenomenon of a comparative example and a specific example 1 to 3 of the present invention; FIG. 5 is a graph of a flat band voltage difference versus implant energy. The hysteresis phenomenon of the specific example 2 and the example 4 to 5 of the present invention will be described; FIG. 6 is a graph showing the leakage current ratio versus the stress time, and the component reliability of the comparative example and the specific example 1 to 3 of the present invention will be described. The graph of the leakage current ratio versus the stress time indicates that the wood is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Example and one of the specific examples 1 to 3 of the present invention From the help of the gate structure of the gate. Annex 1. na, • 彩色7's leakage current ratio versus stress time plot for color contrast diagram. Annex 2 • Color comparison diagram of the IGXD analysis data plot of Figure 8.
15 201025427 【主要元件符號說明】 2 半導體基板 9 射頻真空系統 3 閘極介電層 91 反應腔體 4 閘極 92 含氮氣體分子團 5 源極 93 含氮電漿 6 汲極 94 射頻供應器 7 保護層 95 天線 8 接點插塞 96 脈衝波產生器15 201025427 [Description of main components] 2 Semiconductor substrate 9 RF vacuum system 3 Gate dielectric layer 91 Reaction chamber 4 Gate 92 Nitrogen-containing molecular group 5 Source 93 Nitrogen-containing plasma 6 Bungee 94 RF supply 7 Protective layer 95 Antenna 8 Contact plug 96 Pulse wave generator
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