201024995 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種測試裝置，且特別是有關於一種模 擬多個儲存裝置的測試裝置及其測試方法。 【先前技術】201024995 VI. Description of the Invention: [Technical Field] The present invention relates to a test apparatus, and more particularly to a test apparatus for simulating a plurality of storage apparatuses and a test method therefor. [Prior Art]
在電腦裝置的主機板生產過程中，為測試主機板的串 列儲存介面（Serial Advanced Technology Attachment， SATA)硬碟連接器功能是否正常’會使用諸多設備及耗 材對主機板的SATA硬碟連接器進行測試。 如圖1所示，主機板1〇1設置有四個SATA硬碟連接 器102a〜102d。在測試SATA硬碟連接器i〇2a〜i〇2d時， 需要連接4個SATA硬碟i〇3a〜i〇3d至主機板101的 SATA硬碟連接器i〇2a〜102d。 當然，主機板101還連接有測試時必要的元件，比如 CPU、記憶體、硬碟等運行測試程式必需的元件。 然而’目前的測試方法有諸多缺點。例如： ’ SATA硬碟的連接關頻繁插拔磨損而 的難硬碟，如此將大幅提高測2成 ^ ^_|插拔_中’ SATA硬_碰撞而 致硬碟損壞。（3)SΑΤΑ實體硬碟盔讲人拼 虚, 硬碟知介®，若突⑽電或 ^在強磁％中易造成磁道損壞’而不易修復。（4)在測^ 時，主機板有多少個SATA連 试 逆獲器，就需要用多少個實體 4 201024995 硬碟’而每一個實體硬碟都會 連接11，則會使得測試K要 間來進仃，且需講買多個SATA 而要較大的空 本。 磲，進而提高測試成 【發明内容】 試装置及其測 兮方t發，供一種模擬多個儲存震置的測 忒方法，此夠解決上述問題。 本發明提供-麵擬多倾存 測試電腦裝置的多個第一儲存 2 i裝置，用以 該些第—儲存裝置連接器發出多取電腦裝置透過 置，以模擬對該些儲存裝置的多個存取曰令至測試裝 及測試存取區段。多個第:儲存用控制單元以 第-儲存裝置連接器，且接收該也d用以輕接該些 元分別祕該些第二儲存裳置連接器。°控制單 指令的存取操作I m存取區段執行該些第一存取 本發明也提供一種測試方法， ，，裝置連接器，置的多 ?:器發出多個第一存取指令，；:館= 夕個存取區段執行-存取操作。測試方震置的 第-存取指令；以及響應該些第.接收該些 模擬該些存取區段的職存取區段執行^第 201024995 的存取操作 記有益效果為：採用記髓來提供—存取區段， 目於硬碟有讀寫速度快的特點，因此本發明的測 佳、i’L。此外，記憶體相較於硬碟，其體積*、抗振性 佳 '不易#壞’故可降低生朗試成本。 作詳細說明 ❹ _ 易僧為ϊΐϋ之上述和其他目的、特徵和優點能更明顯 特舉較佳實施例，並配合所附圖式， 如下。 【實施方式】 圖2所示為本發明較佳實施例的測試裝置的示意圖。 3〇〇 供的測試裝置期用以測試電腦裝置 鳩if 的多個第一儲存裝置連接器施, 理知上，在測試時，多個第一儲存裝置連接哭 =，3:應與多個相對應的儲存裝置相連接。在本實： 碟，卜本碟’較佳地，儲存裝置為襲硬 逹ΐϋ ίί11烏，鳩為SATA硬碟連接11，適於 二主機板3〇1所發出的_健可經由 ==硬硬碟碟連接轉送至與SATA硬碟連接器連接的 -储==器中;。=:::板301上除了設置有第 本声㈣之外’主機板301設置了中 、处7G PU)、記憶體、顯示卡等進行運行測試所需 6 201024995 ==此ί.ί機板3〇1還連接了電源供應器、顯示 、'、别述硬碟儲存有測試程式，以控制電腦 ^置30G發出存取指令與搭配測試裝置綱來判斷第一儲 存裝置連接器302a, 302b是否良好。在其他實施例中，測 ==存在主機板3〇1上的記憶體中，本發明並不 施^中，上述多個第一儲存裝置連接器施， 在此用以模擬多個儲存裝置，使得電腦L= ^忍為自己發出多個第—存取騎輯過第 接器3〇2a，302b送至至多_ 的多個存取區段來進行存取操 于夕個f存裝置 33〇〇2?3^ Ϊ 多個存取區執以模擬對該些儲存裝置的 實施例中，第—存取指令包括多個寫入指令或多 广指令也_ 也可為讀取操1 柄存取㈣可為寫入操作， 另外’每-個存取指令可以是對—雜定實 取位r每-個存取指令中亦具有;取位址子 位址與結束位址），使得儲存裝置（硬碟）的控 7 201024995 據上述存取指令的存取位址來對特定存取區段進行存取操 作。在本實施例中，為了方便說明，上述第一存取指令的 存取位址與特定實體儲存裝置的存取區段的位址稱之&第 一存取位址。 本實施例所提供的測試裝置200包括多個第二儲存裝 置連接器201a，201b、介面轉換單元2〇2、控制單元2〇$ 以及記憶體204。在本實施例中，控制單元2〇3與記憶體 ❿ 204整合在一可程式化邏輯閘陣列晶片（FpGA) 2〇5 ^， 在其他實施例中，控制單元203與記憶體204亦可為各別 獨立元件。此外，第二儲存裝置連接器2〇la, 2〇lb、介面 轉換單元202以及可程式化邏輯閘陣列晶片2〇5是設置在 同一張電路板206上。 上述多個第二儲存裝置連接器201a，201b用以耦接第 一儲存裝置連接器302a, 3〇2b，且能接收由電腦裝置3〇〇 所發出的-個或多個第一存取指令。第二儲存裝置連接器 • 201a，201b與第一儲存裝置連接器3〇2a，3〇2b之間可以利 用連接線（例如：SATA連接線（Cable))來予以輕接。 在本實施例令，第二儲存裝置連接器201a, 201b可八 別且同時地連接第一館存裝置連接器302a，鳩，以ς 檢測第一館存裝置連接器施，302b是否良好。在本實摊 例中，第二儲存裝置連接器2〇la，2_為SAm連接器， 在其他實施例中，苐二錯存裝置連接器2Qla，2紙亦 SAS連接器或其他儲存裝置的連接器。 μ 介面轉換單元202分別搞接第二儲存裝置連接器 201024995 201a，201b與控制單元203，控制單元203則分別耦接介 面轉換單元202與記憶體204。在本實施例中，記憶體 204為靜態隨機存取記憶體（sram)，在其他實施例中， 記憶體204亦可為非揮發性記憶體，但本發明並不對此加 以限制。記憶體204中具有一測試存取區段2041，且這 個測试存取區段2041可用來模擬至少一個儲存裝置中的 ❹ ❹ 一個或多個存取區段，其中測試存取區段2〇41具有一第 一存取位址。 上述介面轉換單元202用以接收來自於第二儲存裝置 連接器201a, 201b的多個第-存取指令，並用以將多個第 了存取指令轉換為多個第二存取指令，其中第一存取指令 ，串列介面指令（例如為：SATA介面指令），第二存^ 指令為並列介面指令（例如為：ATA介面指 ^施例中，介面轉換單元逝可以包括在控制單元2〇3 中’本發明對此並不加以限制。 ^制單元203用以響應電腦裝置3〇〇所發出 峨擬制試存取區段執行第—存取指令的存^ 4如上所述，電腦裝置_發出的第—存 疋實體儲存裝置（例如：硬碟）進 sI疋'特 =單元202雖然將第-存取指令轉換為面 但第-存取指令中的第-存取位址仍予以^留樣“， 控制單元203接收介面轉換單 取指令，且顺淺細令 201024995 位址至測試存取區段2〇41的第二存取位址 作。 果對測°式存取區奴2〇41執行存取操 3 :二的測試方法的流程圖。有_ ^驟S3G5中，電腦裝置遍執 ，的測試程式，且透過第-儲存裝置連接Ϊ 3= 出第一存取指令至測試裝置·。遷接器302a發 第-Si:中’介面轉換單元2°2用以接收來自於 弟一α存裝置連接器201a的笫一.人 取指令轉換為多個格式不同但内容相同心二存取指令。子 且將指令， 址，以對㈣^「第一存取位址映射至第二存取位 一測試=存取區段綱進行存取操作，例如：寫入 試裝晉2〇Λ 為讀取資料的第一存取指令至測 數攄雷Η«<壯’以讀取先前寫入於測試存取區段2041的 時所在讀取到數據之後，電腦裝置300會 致，χ則數據與先前㈣人的數據是否'"致，若一 貝!代表第-儲存褒置連接器施良好 ， 則代表第-儲钱置連料施良料能有問題。 201024995 似/、他帛儲存裝置連接器302b的测試與上述做法類 硬碟=理本供的測試裝置根據 ΓΓ:取=r(Map)到上述記憶體的特= ❿ 取區的儲存裝置連接器測試時對不同位址的存 動Ι Ϊ 對’實際上是對同―個特定存取區段進行 動作。藉此’本發明的職速度快，且 空間較小’無需購置過多的硬碟而可降低生產測試成=。、 =本發明已啸佳實施例揭露如上，然其並非 艮^林明’任何熟f此技藝者，在不脫離本發明之 :祀圍内’當可作些許之更動與潤飾，因此本發明之 敕圍當視後社t請專職圍所狀者鱗。 〜蔓 ❹ 11 201024995 【圖式簡單說明】 圖1所示為先前技術的測試裝置示意圖。 圖2所示為本發明較佳實施例的測試裝置的示意圖 圖3所示為本發明較佳實施例的測試方法的流程圖 【主要元件符號說明】 主機板 101 SATA硬碟連接器 102a, 102b, 102c, 102d SATA硬碟 103a, 103b, 103c, 103d 測試裝置 200 電腦裝置 300 φ 主機板 301 第一儲存裝置連接器 302a, 302b 第一儲存裝置連接器 201a, 201b 介面轉換單元 202 控制單元 203 記憶體 204 可程式化邏輯閘陣列晶片 205 201024995 電路板 206 測試存取區段 2041 步驟 S305, S310, S315, S320In the production process of the motherboard of the computer device, in order to test whether the Serial Advanced Technology Attachment (SATA) hard disk connector function of the motherboard is normal, the SATA hard disk connector of the motherboard will be used for many devices and consumables. carry out testing. As shown in Fig. 1, the motherboard 1〇1 is provided with four SATA hard disk connectors 102a to 102d. When testing the SATA hard disk connectors i〇2a to i〇2d, it is necessary to connect four SATA hard disks i〇3a to i〇3d to the SATA hard disk connectors i〇2a to 102d of the motherboard 101. Of course, the motherboard 101 is also connected with components necessary for testing, such as CPU, memory, hard disk, and the like necessary for running the test program. However, the current test method has a number of disadvantages. For example: ’ SATA hard disk connection is a hard disk that is frequently plugged and unplugged, which will greatly increase the damage of the hard disk caused by the SATA hard_collision. (3) SΑΤΑ entity hard disk helmet speaker fights virtual, hard disk Zhijie®, if the sudden (10) electricity or ^ in the strong magnetic % easy to cause track damage 'not easy to repair. (4) In the test, how many SATA test reversals on the motherboard, how many entities 4 201024995 hard disk need to be used, and each physical hard disk will be connected to 11, which will make the test K to come in Hey, and you need to buy more SATA and have a larger space.磲 进而 提高 提高 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 The present invention provides a plurality of first storage 2 i devices for the surface-to-multiple dumping test computer device, wherein the plurality of storage device connectors are configured to transmit a plurality of computer devices to simulate multiple storage devices. Access to the test and test access sections. The plurality of storage control units are connected to the first storage device connector, and the receiving terminal is configured to lightly connect the plurality of second storage skirt connectors. ° Controlling a single instruction access operation I m access section performing the first accesses The present invention also provides a test method, the device connector, the multi-processor: issuing a plurality of first access instructions, ;: Library = eve access segment execution-access operation. The first access instruction of the tester is set; and the access operation of the 201024995 is performed in response to the receiving of the access segments of the access segments. The beneficial effect is: using the memory The providing-access section has the characteristics of fast reading and writing speed of the hard disk, and therefore the measurement of the present invention is good, i'L. In addition, compared with the hard disk, the memory has a good volume* and good vibration resistance, which is not easy to be 'bad', which can reduce the cost of the raw test. DETAILED DESCRIPTION OF THE INVENTION The above and other objects, features and advantages of the present invention will become more apparent. Embodiments Fig. 2 is a schematic view showing a test apparatus according to a preferred embodiment of the present invention. The test device period used to test the plurality of first storage device connectors of the computer device ,if, knowingly, during the test, the plurality of first storage devices are connected to cry =, 3: should be associated with multiple phases The corresponding storage devices are connected. In this: the dish, the cloth dish 'better, the storage device is hard 逹ΐϋ ίί11 鸠, SATA SATA hard disk connection 11, suitable for two motherboards 3 〇 1 issued by _ health can be == hard The hard disk connection is transferred to the -=== device connected to the SATA hard disk connector; =::: In addition to the first sound (four) on the board 301, the 'main board 301 is set to the middle and the 7G PU, the memory, the display card, etc. are required for the running test. 201024995 ==This ί. 3〇1 is also connected to the power supply, display, ', other hard disk storage test program, to control the computer ^ 30G issued access command and matching test device program to determine whether the first storage device connector 302a, 302b good. In other embodiments, the measurement == exists in the memory on the motherboard 3〇1, and the present invention is not implemented, and the plurality of first storage device connectors are used to simulate a plurality of storage devices. The computer L=^ is forced to issue a plurality of first-access riding series adapters 3〇2a, 302b to a plurality of access segments of at most _ to perform access operations on the evening storage device 33〇 〇2?3^ Ϊ In the embodiment in which the plurality of access areas are executed to simulate the storage devices, the first access instruction includes a plurality of write instructions or a multi-wide instruction, and may also be a read operation. Take (4) can be a write operation, in addition, 'every access instruction can be a pair of miscellaneous real bits r also have one per access instruction; take the address sub-address and end address), so that the storage Device (hard disk) control 7 201024995 Access operation to a specific access zone according to the access address of the above access instruction. In the present embodiment, for convenience of explanation, the access address of the first access instruction and the address of the access section of the specific physical storage device are referred to as & first access address. The test apparatus 200 provided in this embodiment includes a plurality of second storage device connectors 201a, 201b, an interface conversion unit 2, a control unit 2, and a memory 204. In this embodiment, the control unit 203 and the memory ❿ 204 are integrated in a programmable logic gate array (FpGA) 2〇5^. In other embodiments, the control unit 203 and the memory 204 may also be Separate components. Further, the second storage device connector 2〇1, 2〇1b, the interface conversion unit 202, and the programmable logic gate array chip 2〇5 are disposed on the same circuit board 206. The plurality of second storage device connectors 201a, 201b are configured to couple the first storage device connectors 302a, 3b, 2b, and can receive one or more first access commands issued by the computer device . The second storage device connector • 201a, 201b and the first storage device connector 3〇2a, 3〇2b can be connected by a connection cable (for example, a SATA cable). In this embodiment, the second storage device connectors 201a, 201b can be connected to the first storage device connector 302a at different times and simultaneously to detect whether the first storage device connector 302b is good. In this embodiment, the second storage device connector 2〇la, 2_ is an SAm connector. In other embodiments, the second storage device connector 2Qla, 2 paper is also a SAS connector or other storage device. Connector. The μ interface switching unit 202 respectively connects the second storage device connector 201024995 201a, 201b with the control unit 203, and the control unit 203 is coupled to the interface conversion unit 202 and the memory 204, respectively. In this embodiment, the memory 204 is a static random access memory (sram). In other embodiments, the memory 204 may also be a non-volatile memory, but the invention is not limited thereto. The memory 204 has a test access section 2041, and the test access section 2041 can be used to simulate one or more access sections in at least one storage device, wherein the test access section 2〇 41 has a first access address. The interface conversion unit 202 is configured to receive a plurality of first access instructions from the second storage device connectors 201a, 201b, and to convert the plurality of first access instructions into a plurality of second access instructions, wherein the An access instruction, a serial interface instruction (for example, a SATA interface instruction), and a second storage instruction is a parallel interface instruction (for example, the ATA interface refers to the embodiment, the interface conversion unit may be included in the control unit 2〇) 3 in the present invention is not limited thereto. ^ The unit 203 is responsive to the computer device 3 〇〇 issued by the virtual test access section to execute the first access command memory 4 as described above, the computer device _ The issued first storage device (for example, a hard disk) enters the sI 疋 ' special = unit 202, although the first access command is converted into a face, but the first access address in the first access command is still ^ "Remaining sample", the control unit 203 receives the interface conversion single fetch instruction, and succinctly makes the 201024995 address to the second access address of the test access segment 2〇41. 〇41 Execute the flow chart of the access control 3: two test method. There is _ ^ In S3G5, the computer program passes the test program, and through the first storage device connection Ϊ 3 = the first access command to the test device. The mover 302a sends the -Si: medium interface conversion unit 2 ° 2 The command to receive the input from the brother-and-one device connector 201a is converted into a plurality of different format but the same content of the second access command. The instruction, the address, to the (four) ^ "first save The address is mapped to the second access bit. The test=access segment is used to perform the access operation, for example, the write test is performed. The first access command for reading the data is measured to the number of thunders «< After the data is read by reading the time previously written in the test access section 2041, the computer device 300 will cause the data and the data of the previous (four) person to be '" On behalf of the first-storage device connector, it is good to represent the first-storage device. 201024995 Similar to the test of the storage device connector 302b and the above-mentioned practice type hard disk=理本The test device is supplied according to ΓΓ: taking =r(Map) to the storage device of the special memory area of the above memory The storage of different addresses during the connector test Ι Ϊ 'actually acts on the same specific access section. By this, the invention has a fast job and a small space, so there is no need to purchase too much hard. The disc can reduce the production test to =., = the invention has been disclosed in the above example, but it is not 艮^林明's any skilled person, without departing from the invention: Some of the changes and retouchings, therefore, the scope of the present invention is to look after the full-scale surrounding the scales. ~ ❹ ❹ 11 201024995 [Simplified schematic] Figure 1 shows a schematic diagram of the prior art test device. 2 is a schematic view of a test apparatus according to a preferred embodiment of the present invention. FIG. 3 is a flow chart showing a test method according to a preferred embodiment of the present invention. [Main component symbol description] Motherboard 101 SATA hard disk connectors 102a, 102b , 102c, 102d SATA hard disk 103a, 103b, 103c, 103d test device 200 computer device 300 φ motherboard 301 first storage device connector 302a, 302b first storage device connector 201a, 201b interface conversion unit 202 control unit 203 memory Body 204 Programmable Logic Gate Array Chip 205 201024995 Circuit Board 206 Test Access Section 2041 Steps S305, S310, S315, S320
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