201024989 六、發明說明： 【發明所屬之技術領域】 本發明係涉及一種反應電源遮斷之電路裝置，特別 係指一種用以防止電腦電源突然中斷而產生重置或誤動 作現象的電路裴置及其方法。 【先前技術】201024989 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit device for interrupting a reactive power source, and more particularly to a circuit device for preventing a sudden interruption of a power supply of a computer and causing a reset or malfunction method. [Prior Art]
由於資訊科技的快速成長，電腦已成為人們經常使 用的工具之一。而在探討電腦電源時，我們可以了解目前 電腦中的電源管理電路大部分都已經是採用進階組態電 源管理介面（Advanced Configuration and Power Interface ’ ACPI)來做為電源管理標準，其主要是能將電 腦電源有效地分配傳送至系統元件，搭配硬體偵測主機板 溫度、風扇轉速和電源供應器的電壓等資訊，進而提供適 當的電源與主機工作頻率，來達到省電與效率並存的目 標。 而ACPI的特色在於，其是用瞬間軟體電源開關來控 制電源:t源供應器的開關按㉞並不連接到電源供應器本 身，而是連制主機板上。電源供應^無法啟動電腦的電 源，而是直接由主機板控制，而大部分是配合Ατχ (Advanced Technology Extended)電源系統一起使用。這 使電腦供舰麵，㈣電腦處_完全電源的睡眠 關機、鍵盤開機、網路喚醒等功能 設計即在m供應輯加提 =用的 也就是-般所謂的輔助電壓，:二 =: 態下’電源供應器也會持續 4 201024989 板0 ^ 承上所述，在ACPI控制器的設計上，也就 ::為=電源控制(Dual p_r c〇ntr〇〗)的原理，以在電;、 ^ f運作狀態時，能將電源供應ϋ所提供的運作電壓 控制供電給主機板上的相關晶片及周= 制將待命電壓(5伏特)轉換成為系統電|，以提 === 板上的相關晶片及周邊設備控制器使用。Due to the rapid growth of information technology, computers have become one of the tools that people often use. When discussing the power supply of the computer, we can understand that most of the power management circuits in the current computer have adopted the Advanced Configuration and Power Interface 'ACPI' as the power management standard. The computer power supply is effectively distributed to the system components, and the hardware detects the temperature of the motherboard, the fan speed, and the voltage of the power supply to provide appropriate power and host operating frequency to achieve the goal of saving power and efficiency. . The ACPI is characterized by the use of a transient software power switch to control the power supply: t The source supply switch 34 is not connected to the power supply itself, but is connected to the motherboard. The power supply ^ cannot start the power of the computer, but is directly controlled by the motherboard, and most of them are used together with the Advanced Technology Extended power system. This makes the computer for the ship's surface, (4) computer _ full power sleep shutdown, keyboard boot, network wake-up and other functional design is added in the m supply = use is also known as the auxiliary voltage,: two =: state The next 'power supply will continue 4 201024989 board 0 ^ According to the above, in the design of the ACPI controller, also:: = power control (Dual p_r c〇ntr〇) principle, in the electricity; When the ^f is in the operating state, the operating voltage control provided by the power supply can be supplied to the relevant chip on the motherboard and the cycle voltage (5 volts) can be converted into the system power|to the === board Use of related wafers and peripheral controllers.
機在此—架構下’若是電腦系統的電源突然中 斷’例如電源供應器的電源線被拔掉時，由於運作電壓合 若ACPI控制器此時才再控制將待命電“ 換成為^電壓’將會因為將待命電壓轉換為系統電壓也 需要-段相’因而使得系統電壓會有瞬間落下再恢 情形’以形成陷_ip)的現象，進而可能會產生非必要 =iiRr)或誤動伽象，例如：基本以輸出系統 (BIOS)中的設定可能會產生重置。因此，針對此一問題， 便是目前值得加以探討及改善的地方。 【發明内容】 有鑑於此，本發明所要解決的技術問題在於，利用 能即時反應電源供應器之狀態的一電源確認信號來做為 反應電源遮斷之電路裝置進行切換及控制的判斷依據，: 在電源供應盗的運作電壓停止供應而電壓準位開始下降 之别，旎及日π控制轉換待命電壓來接替成為系統電壓，辨 以防止系統電壓瞬間會先產生電壓陷落(dip)的情形，然^ 才再隨待命電壓-起下降。進而贼電腦純在突然發生 電源中斷時，產生不必要的重置或誤動作之現象 為了解決上述問題，根據本發明所提出之一方案， 5 201024989 提供一種s由& ❿ 統，並且夂應電源遮斷之電路裝置，是應用於一電腦系 括：」門連接電腦系統的一電源供應器，該電路裝置包 開關單^關曰單元、一電壓轉換器及一控制電路單元。其中， 電腦系ί是接收電源供應器所提供的一運作電壓，並且在 之輸出，而處於一開機狀態時’進行導通以形成—系統電歷 電壓，並電壓轉換器是接收電源供應器所提供的一待命 作以轉撿且在電腦系統處於一休眠或關機狀態時，進行運 連接電壓命電壓來接替成為系統電壓。控制電路單元是 時，依據曹，，並且當電源供應器發生一電源遮斷現象 轉換器應11所產生的—電源確認信絲啟動電壓 案，II，決上述問題，根據本發明所提出之另一方 :2一種反應電源遮斷之方法，是應用於-雷腦系 =電=具有:今?广並且電源供應= 洗分站電壓待命電壓，而該方法之步驟包括：首 系统^電源供應11所產生的—電源確認信號來確％電腦 系統疋處於―開敵態，進關 二電肠 :的-系統電壓。而在判斷電源確認信電號= 由一控制電路單凡來控制轉換該待命電壓來夺藉 統電壓。進而才讓系統電壓及待命電壓得以同成為系 此，讓系統電壓在待命電壓尚未下降前，不、關閉。轉 下再恢復的陷落現象。 生電饜落 以上之概述與接下來的詳細說明及附圖，比Θ 能進一步說明本發明為達成預定目的所採取之皆是為了 及功效。而有關本發明的其他目的及優點，將式、手段 明及圖式中加以闞述。 ；後續的說 【貫施方式】 6 201024989 本發明是利用能即時反應電源供應器之狀態的一電 源確認信號來做為反應電源遮斷之電路裝置進行切換及 控制的判斷依據’以在電源供應器的運作電壓停止供應而 電壓準位開始下降之前，能及時控制轉換待命電壓來接替 成為系統電壓，藉以防止系統電壓於待命電壓尚未下降前 會產生瞬間電壓落下再恢復的陷落(dip)情形。 請參考第一圖，為本發明反應電源遮斷之電路裝置 的實施例方塊圖。如圖所示，本實施例是提供一種反應電 源遮斷之電路裝置10,其是應用於一電腦系統（圖未示）， 並且是設置於電腦系統的一主機板丨上，用以連接電腦系 統的一電源供應器2，並且輸出一系統電壓vduai (3 3伏 特)給主機板！上的-主機板晶片11(如：南橋^;)/至In this case, if the power supply of the computer system is suddenly disconnected, for example, if the power supply line of the power supply is unplugged, the ACPI controller will control the standby power to "change to ^ voltage". Because the conversion of the standby voltage to the system voltage also requires a - segment phase, thus causing the system voltage to fall and revert to the situation to form a trap _ip), which may result in non-necessary = iiRr) or misdirected gamma For example, the reset may be generated basically in the setting in the output system (BIOS). Therefore, for this problem, it is worth exploring and improving at present. [Invention] In view of this, the present invention is to be solved. The technical problem lies in the use of a power supply confirmation signal capable of reacting the state of the power supply as a basis for determining the switching and control of the circuit device for the reaction power supply interruption: the operation voltage of the power supply supply is stopped and the voltage level is stopped. Start to fall, 旎 and π control conversion standby voltage to replace the system voltage, to prevent the system voltage will first generate voltage In the case of a dip, the voltage is lowered again with the standby voltage. Further, the thief computer generates an unnecessary reset or malfunction when a power interruption occurs suddenly. In order to solve the above problem, the present invention is proposed. A scheme, 5 201024989 provides a circuit device for severing power supply and slamming power supply, which is applied to a computer system: "a power supply device for a door connection computer system, the circuit device package switch unit ^ The unit, a voltage converter and a control circuit unit. Wherein, the computer system ί is an operating voltage provided by the receiving power supply and is outputted, and when in a power-on state, 'conducting to form a system electrical calendar voltage, and the voltage converter is provided by the receiving power supply The standby voltage is turned on and when the computer system is in a sleep or shutdown state, the connection voltage is applied to replace the system voltage. The control circuit unit is based on Cao, and when the power supply has a power supply interruption phenomenon, the converter should generate 11 - the power supply confirmation wire start voltage case, II, to solve the above problem, according to the present invention One side: 2 A method of blocking the reaction power supply is applied to - Thunder brain system = electricity = has: today and wide power supply = washing station voltage standby voltage, and the steps of the method include: first system ^ power supply 11 The generated - power supply confirmation signal to confirm that the computer system is in the "open state", enter the second electro-intestine: - system voltage. In the judgment of the power supply confirmation signal number = by a control circuit to control the conversion of the standby voltage to capture the voltage. In turn, the system voltage and the standby voltage are the same, so that the system voltage is not turned off before the standby voltage has dropped. Turn down and then resume the fall. The following is a summary of the above and the detailed description and the accompanying drawings, which can further illustrate that the present invention is intended to achieve the intended purpose. Other objects and advantages of the present invention will be described in the following description. The following is a method of "switching and controlling the circuit device that is capable of reacting the power supply to the power supply." Before the operating voltage of the device stops supplying and the voltage level begins to drop, the switching standby voltage can be controlled in time to replace the system voltage, thereby preventing the system voltage from generating a dip in which the instantaneous voltage falls and then recovers before the standby voltage has dropped. Please refer to the first figure, which is a block diagram of an embodiment of a circuit device for interrupting a reactive power supply according to the present invention. As shown in the figure, the present embodiment provides a circuit device 10 for reactive power supply interruption, which is applied to a computer system (not shown) and is disposed on a motherboard of a computer system for connecting to a computer. A power supply 2 of the system, and outputs a system voltage vduai (3 3 volts) to the motherboard! On - motherboard chip 11 (eg: South Bridge ^;) / to
Extended)之電源供應器2， Vcc、一待命電壓vsb(5 PWR OK ° 少一周邊設備控制器12(如：網路晶片等）。其中，電源供 應器2可例如是為Ατχ規格（Advanced'Techn〇i〇gy ，用以能提供數種運作電壓Extended power supply 2, Vcc, a standby voltage vsb (5 PWR OK ° less peripheral controller 12 (eg, network chip, etc.). The power supply 2 can be, for example, Ατχ specification (Advanced' Techn〇i〇gy for providing several operating voltages
7 201024989 信號PWR—OK是在主機板！開機而電源供應器2被啟動 後，經過約10〜500ms的延遲，會從〇伏特轉變為5伏 特之電壓準位’以做為各個運作電壓Vee之輸出為正常 的指示信號。 電路裝置10包括：一開關單元1(H、一電壓轉換器 =2、一進階組態電源管理介面(ACn)1〇3及一控制電路 單元1〇〇其中，開關單元101是連接電源供應器2，用 來=運作電壓Vcc(3.3伏特），並且開關單元1〇1可例 ❿ 如疋採用一金屬氧化半導體場效電晶體(MOSFET)(圖未 示）來做為電壓輸出的開關。而電壓轉換器1〇2同樣是連 接電源供應器2，但用來接收待命電壓乂邮伏特），用 以在運作時將5伏特的待命電壓轉換為3 3伏特的待命電 壓。並且在本實施例的設計上，電壓轉換器1〇2除了是一 般接艾進卩白、组態電源管理介面的控制來進行啟動之 外，更會進一步依據控制電路單元104所輸出的低電壓準 位之控制信號來進行啟動運作。 進階組態電源管理介面103是連接開關單元101及 電壓轉換器102’用以在電源供應器2是正常接電下，依 據電腦系統的狀態來控制開關單元1〇1 <導通或者控制 電壓轉換器1〇2進行運作。具體來說，進階組態電源管理 介，。1〇3是依據主機板2上之南橋晶片所提供的一休眠控 號(如：SLP—S3)來判斷電腦系統的狀態，其中，當電 腦系統是處於一開機狀態時，SLP_S3信號是指示為高電 f準位’進階組態電源管理介面103是控制關閉電壓轉換 器，而僅控制開關單元101導通，以產生系統電壓 Vdual(3.3伏特)之輸出；而當電腦系統是處於休眠或關機 8 201024989 狀態時，SLP_S3信號是指示為低電壓準位，進階电能 源管理介面10 3會關閉開關單幻〇!，並且控制電壓g換 器ι〇2進行運作，以轉換待命電壓Vsb(3 3伏特)來接 成為系統賴術al(3.3伏特）。而此―設計㈣統電壓 Vdual即是所謂的雙重電壓之設計。 、控制電路單元104是連接電壓轉換HH)2,並且依據 電源供應器2所產生的電源確認信號pWR_〇K來、a 否輸出控制信號給電壓轉換器酸，用以做為電壓轉^ 1〇2轉換待命電壓Vsb(3.3伏特)的進—步^ _ 線二===== 壓Vsb(5伏特)會比運作 发衝冤路因此待命電 間。於是，本實施例便是藉由此—原3H)維持較長的時 信號PWR__〇K具有即時#%再依據電源確認 特性，以在電源供應器2發^=^ ^供電狀態的 電㈣換H H)2進行料f f _斷絲時，提早控制 換運作時的時間差防止因電顯換器搬進行轉 差而導致祕錢杨al(3.3伏特)瞬間 201024989 產生落下再恢復的陷落現象。 接下來’請在上述實施例所說明的架構之下，繼續 參考第二圖及第三圖，為本發明控制電路單元的一實施例 電路示意圖及運作時序圖。如第二圖所示，本實施例所提 供的控制電路單元104是採用電路元件佈線的態樣來設 计。控制電路單元104包括：一第一分壓電路1〇41、一 第二分壓電路1042、一第三分壓電路1〇43、一第一比較 器1044及一第二比較器1〇45。此外，為了能方便第三圖 的運作時序之說明，第二圖中的運作電壓Vcc是採用接 收電源供應器2的5伏特電壓之設計。 第一分壓電路1041是透過一電阻R1(1KQ)及一電阻 R2(1KD)來形成分壓設計。其中，電阻R1的一端是連接 待命電壓Vsb(5伏特）’而電阻R1的另一端是連接電阻 R2的一端，並且電阻R2的另一端是接地。 第二分壓電路1042是透過一電阻R3(ikQ)、一電阻 Κ4(1ΚΩ)及一二極體D1來形成分壓設計。其中，電阻 R3的一端疋連接待命電壓vsb(5伏特），而電阻R3的另 一端是連接電阻R4的一端，並且電阻R4的另一端是接 地。二極體D1的正端是連接於電阻R3及電阻R4的連接 點，也就疋第二分壓電路1042的分壓點，而二極體D1 的負端是連接電源確認信號pWR_〇K。 第二分壓電路1043是透過一電阻κ5(2ΚΩ)及一電阻 R6(1KD)來形成分壓設計。其中電阻R5的一端是連接待 命電壓Vsb(5伏特），而電阻R5的另一端是連接電阻R6 的一端，並且電阻R6的另一端是接地。 第一比較器1044的一正相輸入端(+)是連接運作電 201024989 壓Vcc(5伏特），並且再並聯連接一穩壓電容1〇46。而第 一比較器1044的一反相輸入端㈠是連接第一分壓電路 1041的分壓點。 第二比較器1045的正相輸入端(+)是連接第二分壓 電路1042的分壓點。而第二比較器1045的反相輸入端㈠ 是連接第一比較器1044的一輸出端及第三分壓電路1043 的分壓點。並且第二比較器1045的輪出端即是連接電壓 轉換器102，用以輸出一控制信號CS來控制電壓轉換器 蠢 102之運作。 而基於比較器的原理，當正相輸入端(+)的電壓高於 反相輸入端㈠的電壓時，比較器的輸出端會截止，相當 於輸出端開路(Open Drain)。而當反相輸入端㈠的電壓高 於正相輸入端(+)的電壓時，輸出端會形成飽和，也就是 輸出端會形成接地而連接低電壓準位。因此，請對照第二 圖之電路圖來繼續參考第三圖之運作時序說明，並且其大 致規劃成A〜E五個時間點來進行說明。 首先，當電腦系統是處於接電但尚未啟動的階段 時，也就是在時間點A之前：SLP__S3信號是處於低電壓 準位，第一比較器1044的反相輸入端㈠之電壓即是透過 第分壓電路1041而為2.5伏特，而第一比較器1〇44的 正相輸入端(+)之電壓則仍為〇伏特’因此第一比較器 1044之輸出端即是形成接地，進而讓第二比較器1〇45的 反相輸入端㈠之電壓即為〇伏特。而因為電源確認信號 PWR_0K此時仍為〇伏特之低電壓準位，因此第二分壓 電^ 1042中的二極體D1形成導通，而經由分壓原理之 汁异，第二比較器1045的正相輪入端(+)之電壓約為〇7 201024989 伏特。於是，第二比較器10457 201024989 Signal PWR-OK is on the motherboard! After the power supply 2 is turned on and the power supply 2 is turned on, after a delay of about 10 to 500 ms, the voltage level from 〇V to 5 volts is changed as the normal output signal for the output of each operating voltage Vee. The circuit device 10 includes: a switch unit 1 (H, a voltage converter = 2, an advanced configuration power management interface (ACn) 1〇3, and a control circuit unit 1 where the switch unit 101 is connected to a power supply The switch 2 is used for the operating voltage Vcc (3.3 volts), and the switching unit 1〇1 can be exemplified by a metal oxide semiconductor field effect transistor (MOSFET) (not shown) as a voltage output switch. The voltage converter 1〇2 is also connected to the power supply 2, but is used to receive the standby voltage, which is used to convert the standby voltage of 5 volts into a standby voltage of 33 volts during operation. And in the design of the embodiment, the voltage converter 1〇2 is further controlled according to the low voltage outputted by the control circuit unit 104, in addition to the general control of the Aijin white, the configuration of the power management interface for starting. The control signal of the level is used to start the operation. The advanced configuration power management interface 103 is connected to the switch unit 101 and the voltage converter 102' for controlling the switch unit 1〇1 < conduction or control voltage according to the state of the computer system when the power supply 2 is normally powered. The converter 1〇2 operates. Specifically, advanced configuration power management, . 1〇3 is based on a sleep control number (such as: SLP-S3) provided by the south bridge chip on the motherboard 2 to determine the state of the computer system. When the computer system is in a power-on state, the SLP_S3 signal is indicated as The high-power f-level 'advanced configuration power management interface 103 is a control-off voltage converter, and only controls the switching unit 101 to be turned on to generate an output of the system voltage Vdual (3.3 volts); and when the computer system is in sleep or shutdown 8 In the state of 201024989, the SLP_S3 signal is indicated as low voltage level, the advanced electric energy management interface 10 3 will turn off the switch single illusion!, and the control voltage g changer ι〇2 operates to convert the standby voltage Vsb (3 3 volts) is connected to become the system (3.3 volts). And this - design (four) system voltage Vdual is the so-called dual voltage design. The control circuit unit 104 is connected to the voltage conversion HH)2, and according to the power supply confirmation signal pWR_〇K generated by the power supply 2, a does not output a control signal to the voltage converter acid for use as a voltage turn ^1 〇2 conversion standby voltage Vsb (3.3 volts) into the step ^ _ line two ===== pressure Vsb (5 volts) will be compared to the operation of the rushing road so standby power. Therefore, in this embodiment, the longer time signal PWR__〇K is maintained by the original -3H), and the power is confirmed according to the power supply confirmation characteristic in the power supply 2 (4). When changing HH)2 to feed the material ff _ broken wire, the time difference between the early control and the change operation prevents the slip of the secret money Yang (3.3 volt) instantaneously and finally recovers due to the slip of the electric display. Next, please refer to the second and third figures in the architecture described in the above embodiments, which is a circuit diagram and an operation timing diagram of an embodiment of the control circuit unit of the present invention. As shown in the second figure, the control circuit unit 104 provided in this embodiment is designed using the wiring of circuit elements. The control circuit unit 104 includes a first voltage dividing circuit 1〇41, a second voltage dividing circuit 1042, a third voltage dividing circuit 1〇43, a first comparator 1044 and a second comparator 1. 〇45. Further, in order to facilitate the explanation of the operation timing of the third figure, the operating voltage Vcc in the second figure is designed to receive the voltage of 5 volts of the power supply 2. The first voltage dividing circuit 1041 is formed by a resistor R1 (1KQ) and a resistor R2 (1KD) to form a voltage dividing design. Wherein, one end of the resistor R1 is connected to the standby voltage Vsb (5 volts)' and the other end of the resistor R1 is one end connected to the resistor R2, and the other end of the resistor R2 is grounded. The second voltage dividing circuit 1042 is formed by a resistor R3 (ikQ), a resistor Κ4 (1 Ω), and a diode D1 to form a voltage dividing design. Wherein, one end of the resistor R3 is connected to the standby voltage vsb (5 volts), and the other end of the resistor R3 is one end connected to the resistor R4, and the other end of the resistor R4 is grounded. The positive terminal of the diode D1 is connected to the connection point of the resistor R3 and the resistor R4, that is, the voltage dividing point of the second voltage dividing circuit 1042, and the negative terminal of the diode D1 is connected to the power supply confirmation signal pWR_〇. K. The second voltage dividing circuit 1043 is formed by a resistor κ5 (2 ΩΩ) and a resistor R6 (1KD) to form a voltage dividing design. One end of the resistor R5 is connected to the standby voltage Vsb (5 volts), and the other end of the resistor R5 is one end connected to the resistor R6, and the other end of the resistor R6 is grounded. A positive phase input terminal (+) of the first comparator 1044 is connected to the operating power 201024989 voltage Vcc (5 volts), and is further connected in parallel with a voltage stabilizing capacitor 1 〇 46. An inverting input terminal (1) of the first comparator 1044 is a voltage dividing point connected to the first voltage dividing circuit 1041. The non-inverting input terminal (+) of the second comparator 1045 is a voltage dividing point that is connected to the second voltage dividing circuit 1042. The inverting input terminal (1) of the second comparator 1045 is connected to an output terminal of the first comparator 1044 and a voltage dividing point of the third voltage dividing circuit 1043. And the rounded end of the second comparator 1045 is connected to the voltage converter 102 for outputting a control signal CS to control the operation of the voltage converter stupid 102. Based on the principle of the comparator, when the voltage of the positive phase input terminal (+) is higher than the voltage of the inverting input terminal (1), the output of the comparator is turned off, which is equivalent to the open circuit of the output terminal (Open Drain). When the voltage of the inverting input terminal (1) is higher than the voltage of the positive phase input terminal (+), the output terminal will form saturation, that is, the output terminal will form a ground and connect the low voltage level. Therefore, please refer to the circuit diagram of the second figure to continue to refer to the operation timing description of the third figure, and it is roughly planned to be A to E five time points for explanation. First, when the computer system is in the stage of power-on but not yet started, that is, before the time point A: the SLP__S3 signal is at the low voltage level, and the voltage of the inverting input terminal (1) of the first comparator 1044 is transmitted through the first The voltage dividing circuit 1041 is 2.5 volts, and the voltage of the positive phase input terminal (+) of the first comparator 1 〇 44 is still 〇 volts. Therefore, the output terminal of the first comparator 1044 is grounded, thereby allowing The voltage at the inverting input terminal (1) of the second comparator 1〇45 is 〇volt. Because the power supply confirmation signal PWR_0K is still at the low voltage level of the volts at this time, the diode D1 in the second partial piezoelectric device 1042 is turned on, and the second comparator 1045 is formed by the partial pressure principle. The voltage at the positive phase (+) is approximately 〇7 201024989 volts. Then, the second comparator 1045
.· Μ収·§·/小+啊役制機制。 ㈣盗刚5之輪—形成開路而連接 CS是維持一般 接著，當電腦系統啟動之後，位於時 信號轉而形成高電鮮位，第一比較器二 相輸入端(_)之電壓健_為2.5伏特，而第—比^ 1044的正相輸入端(+)則會接收運作電壓伏 因為穩壓電容1046的設計，而會緩緩地充電至5伏特、，' 其目的是使延遲_大於電賴絲2的電源確認信號 PWR_OK之延遲時間規格的最大值，藉以避開電源確認 信號PWR—OK在開機前，電源供應器2尚未到達高電麼 準位之時間，於是第一比較器1〇44的正相輸入端(+)之電 壓在穩壓電容1046尚未充電超過2.5伏特之前，第一比 較器1044之輸出端狀態會維持為接地。並且此時的電源 確認信號PWR_OK由於電源供應器2的延遲設計的關 係，因而尚未轉為5伏特之高電壓準位。於是，第二比較 器1045的正相輸入端⑴仍大於反相輸入端㈠之電壓，第 一比較裔1045之輸出端仍形成開路而使得控制信號匸g 維持為一般開機日守序的狀態’而不去影響原本的控制機 制。 耷經過時間點A後約10〜5 00ms的時間延遲後，即位 於時間點B上：電源確認信號PWR_OK會從〇伏特轉為 5伏特之高電壓準位，以代表電源供應器2的電源供應正 常。此時，在第一比較器1044的部分，由於穩壓電容1〇46 尚未充電超過2.5伏特，因此第一比較器1〇44的反相輸 入端(-)之電壓仍大第一比較器1044的正相輸入端(+)。而 12 201024989 在第二分壓電路1042中，由於電源確認信號PWR_〇k 已為5伏特之高電壓準位，二極體D1會形成不導通，於 是第二比較器1045的正相輸入端(+)之電壓即是透過電阻 R3及電阻R4之分壓而上升至2.5伏特。但是，在第二比 較器1045的部分，由於第二比較器1045的正相輸入端(+) 之電壓仍大於第二比較器1045的反相輸入端㈠之電壓， 因而第二比較器1045之輸出端仍形成開路而使得控制信 號CS仍維持為不去影響原本控制機制的狀態。.. Μ · § · / small + ah system. (4) The thief of the 5th round - the formation of an open circuit and the connection of the CS is maintained. Then, when the computer system is started, the signal is turned into a high-powered fresh position, and the voltage of the first comparator two-phase input terminal (_) is _ 2.5 volts, and the positive-phase input (+) of the first-to-1044 receives the operating voltage volt because of the design of the voltage-stabilizing capacitor 1046, which is slowly charged to 5 volts, 'the purpose is to make the delay _ greater than The maximum value of the delay time specification of the power supply confirmation signal PWR_OK of the electric wire 2, thereby avoiding the time when the power supply 2 has not reached the high power level before the power supply confirmation signal PWR_OK, so the first comparator 1 The voltage at the non-inverting input (+) of 〇44 maintains the output of the first comparator 1044 to ground until the stabilizing capacitor 1046 has not been charged more than 2.5 volts. Also, the power supply confirmation signal PWR_OK at this time has not been converted to a high voltage level of 5 volts due to the relationship of the delay design of the power supply 2. Therefore, the non-inverting input terminal (1) of the second comparator 1045 is still greater than the voltage of the inverting input terminal (1), and the output terminal of the first comparator 1045 still forms an open circuit so that the control signal 匸g is maintained in the normal state of the boot date. Without affecting the original control mechanism.耷 After a time delay of about 10~500 ms after time point A, that is, at time point B: the power supply confirmation signal PWR_OK will change from 〇VV to a high voltage level of 5 volts to represent the power supply of the power supply 2 normal. At this time, in the portion of the first comparator 1044, since the voltage stabilizing capacitor 1 〇 46 has not been charged more than 2.5 volts, the voltage of the inverting input terminal (-) of the first comparator 1 〇 44 is still larger than the first comparator 1044. Positive phase input (+). And 12 201024989 In the second voltage dividing circuit 1042, since the power supply confirmation signal PWR_〇k has been at a high voltage level of 5 volts, the diode D1 will form a non-conduction, so the positive phase input of the second comparator 1045 The voltage at the terminal (+) rises to 2.5 volts through the voltage division of the resistor R3 and the resistor R4. However, in the portion of the second comparator 1045, since the voltage of the non-inverting input terminal (+) of the second comparator 1045 is still greater than the voltage of the inverting input terminal (1) of the second comparator 1045, the second comparator 1045 The output still forms an open circuit so that the control signal CS remains unaffected to the state of the original control mechanism.
當穩壓電容1046充電超過2.5伏特時，也就是在時 間點C上.此時由於第一比較器1044的正相輸入端(+) 之電壓超過2.5伏特，而會大於第一比較器1〇44的反相 輸入端㈠之電壓’於是第一比較器1044之輸出端即轉變 為開路。於是，第二比較器1045的反相輸入端㈠隨即因 為第三分壓電路1043而具有約1.7伏特之電壓。但由於 第二比較器1045的正相輸入端(+)之電壓此時仍是大於第 二比較器1045的反相輸入端(_)之電壓，因此第二比較器 1045之輸出端仍形成開路，使得控制信號(：8仍維持不去 影響原本控制機制的狀態。 、而接下來’穩壓電容HM6會充電至5伏特電壓並加 以維持，並且在此狀態下，控制電路裝置1〇的第一比較 器1044及第二比較器1045之狀態也就維持不變。 當電源供應器2發生電源遮斷現象時，如 =皮拔掉，也就是在時間點D上：電源確認信號pwR 〇κ =立刻反應而由向電壓準節伏特)轉為低地位 特），此時運作電壓Vcc(5伏特)的電 在第一比較器1044方面，由於有韓厭φ &曰開始下降 有穩壓電容1046的關係， 13 201024989 因此第一比較器1044的正相輸入端(+)之電壓會緩緩地下 降，而第一比較器1044的反相輸入端㈠則仍會維持2.5 伏特，並且在穩壓電容1046的電壓下降超過2.5伏特之 前，第一比較器1044之輸出端的狀態不會改變，這使得 第二比較器1045的反相輸入端㈠之電壓維持在1.7伏 特。而另一方面，由於電源確認信號PWR一OK已轉變為 〇伏特之低電壓準位，因此第二分壓電路1042中的二極 體D1又得以形成導通，於是第二比較器1045的正相輪 入端(+)之電壓會瞬間下降至0.7伏特。如此一來，第二 比較器1045的反相輸入端㈠之電壓會大於第二比較器 1045的正相輸入端(+)，於是第二比較器1045之輸出端形 成接地，而輸出低電壓準位的控制信號CS給電壓轉換器 102，以達到在此時間點D即控制電壓轉換器102運作之 目的。 在經過時間點D之後，由於電腦系統已形成關機狀 態，因此SLP_S3信號會轉而形成低電壓準位。而先前提 過在電源供應器2的設計上，其所提供的待命電壓Vsb(5 伏特）會比運作電壓Vcc維持較長的時間，因此如第三圖 所示，運作電壓Vcc(5伏特）會比較先降至〇伏特。此外， 當進入時間點E時：即表示第一比較器1044所連接的穩 壓電容1046之電壓已先下降低於2.5伏特，於是第一比 較器1044的反相輸入端(-)之電壓會大於第一比較器1〇44 的正相輸入端(+)之電壓’使得第一比較器1044之輸出端 再次轉換為接地。如此一來’讓第二比較器1045的反相 輸入端㈠再次轉變為〇伏特，以讓控制電路單元1〇4中 第一比較器1044及第二比較器1045恢復為原本的狀態。 14 201024989 藉由本實施之電路及運作時序的說明，得以 出本發明是可以明確在運作電壓Vee開始下降時，即 過控制信號cs來啟動電壓轉換器102之運作。 知等到SLP一S3信號轉為低電壓準位時才來控制^壓轉換 裔102運作來得能及時啟動電壓轉換器1〇2，而 早的時間即可如第三圖中所示的時間差τ。藉以達到^ 控制轉換待命電壓Vsb(3.3伏特）來接替成為系統電壓 ❿ 特)之作用，防止因較晚起動電壓轉換器1〇2 且進订轉換運作時所需要的時間差而導致系統 VdUaK3.3伏特）瞬間產生落下再恢復的陷落現象。’ 當然’第二圖及第三圖之實施例僅為本發明之 電路f元104的其中之-電路實施態樣而已。而關於^制 的設計更可例如是設計為—具有循序i輯 類似上述實施例中第-比較器胸的功能，用以避= :啟動後’，乍電壓Vcc開始上升到電源確認信： PWR—OK為南電壓準位的時間（時間點b 時間不會影響控制信號CS的輸出。 。又 ，了，-步說明本發明的詳細運作過程，請同樣在 第-圖之實施例的架構下’參考第四圖，為本發明反岸電 源遮斷之方法的實❹。如圖所示，本實施例提供 =應電源遮斷之方法’其步驟包括：首先，將電腦系統 的電源供絲接電並開啟電源(剛），接著便可進行接收 運待命電壓及電源確認信號’而當判斷電源確認 號^低準位上制高電壓準㈣，得以確認電腦 糸統是處於一開機狀態（S403)。 15 201024989 此時，進階組態電源管 元之導通，用以讓運作電 ^面疋持續地控制開關單 階組態電源管理介面會隨#二’、統電壓（S405)。並且進 -休眠或關機狀態(S407)H仃判斷電腦系統是否進入 是例如接收到主機板上的忐& ’進階組態電源管理介面 來判斷是否進人=:=\所牛輪出的信號 果為是’則表，二電厂结 ::時:轉時二组態電源管理介二 運作=轉ίί命電壓來接替成為系統碰(s彻） 反之’右步驟(S407)的判斷結 路早兀來進糾斷電源確認信號是否產生變化 步驟卿陶斷結果為是，職示控制電路衫判= 源確ω是錢從高電壓準位下降到低電壓準位 判斷電源供應ϋ已發生—電_斷現象，而導致電源確= 化號產生變化。此時，控制電路單元會在運作電蜃開始下 ❿ 降之前，便進一步控制電壓轉換器之運作，以及時轉^待 命電壓來接替成為“電壓(S413)。進而才讓系統電壓與 待命電壓同時關閉（S415)。 〃 而若步驟(S411)的判斷結果為否，則表示目前電腦系 統仍處於開機運作狀態，並且電源供應器的接電也正常， 於是便重複執行步驟(S405)及其爾後之動作。 综上所述’本發明是利用能即時反應電源供應器之 狀態的電源確認信號來做為反應電源遮斷之電路裝置進 行切換及控制的判斷依據，以在電源供應器的運作電壓停 止供應而電壓準位開始下降之前，能及時控制轉換待命電 16 201024989 壓來接替成為系統電壓，#_止系統 落下再恢復的陷落情形。進而避免電腦系統生電壓 源中斷時’產生不必要的重置或誤動作之現大。'、、、'發生電 惟’以上所述’僅為本發明的具體實 明及圖式而已，並_錢制本發明 發明之領域内，可輕易思及之變化或 本案所界定之專利範圍。 山盖在以下 【圖式簡單說明】 第-圖係本發明反應職_之電路裝置的實 圖； 第二圖係本㈣控魏路單元的—實㈣電路示意圖； 第二圖係本發明控制電路單元的—實施例運作時序圖；及 ，四圖係本發明反應輯遮斷之方法施例流程圖。 【主要元件符號說明】 ❹ 1主機板 10電路裝置 101開關單元 102電壓轉換器 103進階組態電源管理介面 104控制電路單元 1041第一分壓電路 1042第二分壓電路 1043第三分壓電路 1044第一比較器 1045第二比較器 1046穩壓電容 17 201024989 11主機板晶片 12周邊設備控制器 2電源供應器 CS控制信號 D1二極體 PWR_OK電源確認信號 Rl，R2，R3，R4，R5，R6 電阻 Vcc運作電壓 Vdual系統電壓 ^ Vsb待命電壓 T時間差 S401〜S415流程圖步驟說明 18When the stabilizing capacitor 1046 charges more than 2.5 volts, that is, at the time point C. At this time, since the voltage of the positive phase input terminal (+) of the first comparator 1044 exceeds 2.5 volts, it is larger than the first comparator 1〇. The voltage at the inverting input (1) of 44 is then turned into an open circuit at the output of the first comparator 1044. Thus, the inverting input (i) of the second comparator 1045 then has a voltage of about 1.7 volts due to the third voltage divider circuit 1043. However, since the voltage of the non-inverting input terminal (+) of the second comparator 1045 is still greater than the voltage of the inverting input terminal (_) of the second comparator 1045, the output of the second comparator 1045 still forms an open circuit. , so that the control signal (: 8 still does not affect the state of the original control mechanism. Then the 'regulator capacitor HM6 will be charged to 5 volts and maintained, and in this state, the control circuit device 1 〇 The state of a comparator 1044 and the second comparator 1045 remains unchanged. When the power supply 2 is interrupted by power, such as = unplugged, that is, at time point D: power supply confirmation signal pwR 〇 κ = Immediate response to the transition from voltage to volts), at this time the operating voltage Vcc (5 volts) of electricity in the first comparator 1044, due to the Han φ φ & 曰 start to fall, there is a voltage regulator The relationship of the capacitor 1046, 13 201024989, therefore the voltage of the positive phase input terminal (+) of the first comparator 1044 will slowly drop, while the inverting input terminal (1) of the first comparator 1044 will still maintain 2.5 volts, and The voltage of the stabilizing capacitor 1046 drops by more than 2.5 Laid before, the state of the output terminal of the first comparator 1044 does not change, which makes the second comparator inverted input terminal 1045 is maintained at (i) of 1.7 volts. On the other hand, since the power supply confirmation signal PWR_OK has been converted to the low voltage level of the volts, the diode D1 in the second voltage dividing circuit 1042 is again turned on, and thus the positive of the second comparator 1045. The voltage at the phase (+) of the phase wheel drops instantaneously to 0.7 volts. In this way, the voltage of the inverting input terminal (1) of the second comparator 1045 is greater than the non-inverting input terminal (+) of the second comparator 1045, so that the output terminal of the second comparator 1045 forms a ground, and the output is low voltage. The bit control signal CS is applied to the voltage converter 102 to achieve the purpose of controlling the voltage converter 102 at this point in time D. After the time point D has elapsed, since the computer system has been turned off, the SLP_S3 signal will turn to a low voltage level. It has been previously mentioned that in the design of the power supply 2, the standby voltage Vsb (5 volts) provided is longer than the operating voltage Vcc, so as shown in the third figure, the operating voltage Vcc (5 volts) Will be compared to first volts. In addition, when entering the time point E: that means that the voltage of the voltage stabilizing capacitor 1046 connected to the first comparator 1044 has dropped below 2.5 volts first, so that the voltage of the inverting input terminal (-) of the first comparator 1044 will A voltage greater than the positive phase input terminal (+) of the first comparator 1〇44 causes the output of the first comparator 1044 to be converted to ground again. In this way, the inverting input terminal (1) of the second comparator 1045 is again turned into a volt volt to restore the first comparator 1044 and the second comparator 1045 of the control circuit unit 〇4 to the original state. 14 201024989 By the description of the circuit and operation timing of the present embodiment, it can be seen that the operation of the voltage converter 102 can be activated when the operating voltage Vee begins to decrease, that is, the control signal cs is activated. It is known that when the SLP-S3 signal is turned to the low voltage level, the voltage converter 1 is operated to start the voltage converter 1〇2 in time, and the early time can be as shown in the third figure. In order to achieve the control conversion standby voltage Vsb (3.3 volts) to take over the role of the system voltage, to prevent the time difference caused by the later start voltage converter 1 〇 2 and the order conversion operation, the system VdUaK3.3 Volt) instantly produces a falling phenomenon that falls and then recovers. The embodiment of the second and third figures is only the circuit implementation of the circuit f-element 104 of the present invention. The design of the control system can be, for example, designed to have a function similar to the first-comparator chest in the above embodiment, to avoid =: after starting, the voltage Vcc starts to rise to the power supply confirmation letter: PWR - OK is the time of the south voltage level (the time point b time does not affect the output of the control signal CS. Again, the - step illustrates the detailed operation of the present invention, please also under the architecture of the embodiment of the figure - 'Refer to the fourth figure, which is a method for the method of the reverse power supply interruption of the present invention. As shown in the figure, the present embodiment provides a method for the power supply interruption. The steps include: first, supplying power to the computer system. After the power is turned on and the power is turned on (just), then the standby voltage and the power supply confirmation signal can be received. When the power supply confirmation number is low, the high voltage level is determined (4), and it is confirmed that the computer system is in a power-on state ( S403). 15 201024989 At this point, the advanced configuration of the power supply unit is used to allow the operating circuit to continuously control the switch single-stage configuration power management interface to follow #二', the system voltage (S405). In-sleep or shutdown State (S407)H仃 to determine whether the computer system enters, for example, receives the 忐& 'Advanced configuration power management interface on the motherboard to determine whether the incoming signal =:=\ Table, the second power plant knot:: When: Turn to the second configuration power management interface 2 operation = transfer ίί voltage to take over as a system touch (s). Otherwise the right step (S407) judgments come early and correct If the power supply confirmation signal is changed, the result of the change is YES, the job control circuit is judged = the source ω is the money from the high voltage level to the low voltage level to judge that the power supply has occurred - the power_off phenomenon, As a result, the power supply does change. At this time, the control circuit unit further controls the operation of the voltage converter before the operation power starts to drop, and then the standby voltage is replaced to become the "voltage (S413). Then, the system voltage and the standby voltage are simultaneously turned off (S415). 〃 If the judgment result of the step (S411) is NO, it means that the current computer system is still in the startup state, and the power supply of the power supply is also normal, so Repeat Step (S405) and its subsequent actions. In summary, the present invention is based on the power supply confirmation signal capable of reacting the state of the power supply immediately, and is used as a basis for determining the switching and control of the circuit device for the reaction power supply interruption. Before the operating voltage of the power supply is stopped and the voltage level begins to drop, the standby standby power can be controlled in time to replace the system voltage, and the #_ system stops falling and then recovers. When the source is interrupted, 'unnecessary resetting or malfunctioning is generated. ',, 'Occurrence of electricity generation' is only for the specific embodiment and the drawings of the present invention, and the invention of the present invention is Within the field, changes can be easily considered or the scope of patents defined in this case. The mountain cover is as follows [a brief description of the drawings] The first picture is a real diagram of the circuit device of the present invention; the second picture is the schematic diagram of the (four) circuit of the control (W) control unit; the second picture is the control of the invention Circuit cell - embodiment operation timing diagram; and, four diagrams are flow diagrams of the method of the present invention. [Main component symbol description] ❹ 1 motherboard 10 circuit device 101 switching unit 102 voltage converter 103 advanced configuration power management interface 104 control circuit unit 1041 first voltage dividing circuit 1042 second voltage dividing circuit 1043 third point Voltage circuit 1044 first comparator 1045 second comparator 1046 voltage regulator capacitor 17 201024989 11 motherboard chip 12 peripheral device controller 2 power supply CS control signal D1 diode PWR_OK power supply confirmation signal Rl, R2, R3, R4 , R5, R6 resistance Vcc operating voltage Vdual system voltage ^ Vsb standby voltage T time difference S401 ~ S415 flowchart step description 18