201020714 六、發明說明： 【發明所屬之技術領域】 本發明係提供-種高效率細驅動電路及其棚方法，尤指一種藉 由脈衝電流源、來力口速負載P肩啟時間及提高電路效率之高效率輸出驅 動電路及其相關方法。 © 【先前技術】 輸出驅動電路常用於各式電子裝置中，主要用來推動負載。請參考 第1圖’第1圖為習知-輸出驅動電路1G之示。輸出驅動電路 10主要包含一準位轉換器102、 路106、一箝位電路1〇8、一輪 102、一定電流供應器104、一預置驅動電 一輸出級110。準位轉換器〗〇2用來根據一 時脈訊號CLK ’對-輸入訊號Sl進行電壓位準轉換，以產生一第一訊 ©號Si與-第二訊號Sz。定電流供應器1〇4用來提供一第一預定電流 Ϊ1。預置驅動電路106柄接於準位轉換器1()2及定電流供應器，用 來根據第-訊號、第二訊號I及第一預定電流心，產生一第一預驅 動訊號SP1及-第二預驅動訊號&以供驅動輸出級11〇。籍位電路 耗接於預置驅動電路1〇6與一接地端，用决阳制筮一魅。201020714 VI. Description of the Invention: [Technical Field] The present invention provides a high-efficiency fine driving circuit and a shed method thereof, and more particularly, a pulse current source, a force-to-port speed load P shoulder opening time, and an improved circuit High efficiency output drive circuit and related methods. © [Prior Art] Output drive circuits are commonly used in various electronic devices to drive loads. Please refer to Fig. 1 'Fig. 1 for the conventional-output drive circuit 1G. The output driving circuit 10 mainly includes a level converter 102, a path 106, a clamping circuit 1〇8, a wheel 102, a constant current supply 104, and a preset driving power-output stage 110. The level converter 〇2 is used for voltage level conversion of the input signal S1 according to a clock signal CLK' to generate a first signal, the number Si, and the second signal Sz. The constant current supply 1〇4 is used to provide a first predetermined current Ϊ1. The preset driving circuit 106 is connected to the level converter 1 () 2 and the constant current supply for generating a first pre-drive signal SP1 and based on the first signal, the second signal I and the first predetermined current center. The second pre-drive signal & for driving the output stage 11 〇. The home circuit is consumed by the preset drive circuit 1〇6 and a ground terminal, and is used to make a fascination.
机现S〇至一輸出端112。 201020714 ❹ 在切換式電源供應系統中，電源轉換積體電路晶片通常在其輸出端 外接-電晶體’以達成電源轉換之目的，而外接電晶體可視為一大型 電容性負載，輸出驅動電路便須具備足夠驅動能力，喊接驅動該外 接電晶體，並且須能快速開啟外接電晶體，以符合其開啟時間之規範， 避免影響到實際的應用。因此，輸出級110中之第一電晶體顧1即需 具備較大的驅動能力，且在整個晶片中佔有—定的比例，亦有較大之 等效電容性。械的，在軸電路部分也要有足夠之驅動能力來 驅動第-電晶體Mm，請繼續參考第i圖及第2圖，其中第 1圖中輸出驅動電路1G之—箝位電路訊號％及輸出驅動訊號s〇的時 序圖。定電流供應器！04提供第一預定電流W預置驅動電路1〇6, 使第-電晶體麵於時間點T2導通後，並於一定時間内驅動外接電 晶體開啟。然而，隨著所需鷄能力的增加，定電流供應器1〇4所提 供^電流必須相對的增大。另—方面，為了避免輸出驅動電路之電壓 過同而損害外接電晶體，如第j圖所示箝位電路⑽可進行限壓 處理如此為了使外接電晶體能迅速開啟而增大定電流供應器 1〇4之大小時，由於箝位電路⑽之限壓保護機制，當第一電晶體議 2後，定電流供應器104仍會對箝位電路108充電將輸出訊料 2升至高_賴㈣體，_啟財完，定電流供應器 1 曰04繼續對箝位電路⑽充電轉持箝位電路1G8之位準。當第-電 二體ΜΝ1閘極電壓超過預設之箱位位準時，多餘之電流會經籍位電路 八传因^導通至地，因此，定電流供應器104所供應之能量，有部 刀係因限壓賴湖即爾。換㈣，軸及電晶體開 201020714 啟時間之規’⑽卩造成㈣之敎，統之效率。 箝位電路之限壓保 簡β之’爲了加快開啟時間所增加之電流容易受 3隻的影響，而造成電路效率不佳。 【發明内容】 ❹相關因方t本發明之主要目的即在於提供一種高效率輸出驅動電路及其 本發明揭露一種高效率輸出驅動電路，包含有-準位轉換器，用來 根據-輸入訊號進行電壓位準轉換以產生複數個訊號；一輸出級，用 來根據複數個預驅動訊號產生一輸出驅動訊號至一輸出端；以及一預 置驅動電路’輕接於鱗位轉難與該輸出級，鋪置㈣電路包含 有第駄電流源’用來提供一第一預定電流；一第二預定電流源， ❹用來提供第一預定電流；一箝位電路，用來限制該複數個驅動訊號 ，其中個之-電壓值；以及複數個預置驅動器，雛於該準位轉換 器該第-預定電流源、該第二預定電流源及箝位電路，用來根據該 複數個峨、該第―預定電流及該第二職電流，產生該複數個預驅 動訊號至該輸出級。 本發明另揭露一種提升一輸出驅動電路效率之方法 ，該方法包含有 根據輸入訊號產生複數個訊號且產生一同步信號；根據該同步信號 產生-轉域並據以產生—第二預定電流·，祕該減娜號、一 201020714 第一預定電流及該第二預定電流產生複數個預驅動訊號；以及根據該 複數個預驅動訊號產生一輸出驅動訊號。 【實施方式】 ΟThe machine is now S to an output 112. 201020714 ❹ In the switched power supply system, the power conversion integrated circuit chip is usually externally connected to the transistor - transistor for the purpose of power conversion, and the external transistor can be regarded as a large capacitive load, and the output driver circuit must be It has sufficient driving capability to drive the external transistor and must be able to quickly turn on the external transistor to meet the specification of its turn-on time, so as not to affect the actual application. Therefore, the first transistor of the output stage 110 needs to have a large driving capability, and it occupies a certain ratio in the entire wafer, and also has a large equivalent capacitance. For the mechanical circuit, there must be sufficient driving capability in the shaft circuit to drive the first transistor Mm. Please refer to the i-th and the second diagram. In the first figure, the output driver circuit 1G-clamp circuit signal % and Output the timing diagram of the drive signal s〇. Constant current supply! 04 provides a first predetermined current W preset driving circuit 1〇6, so that the first transistor surface is turned on after the time point T2, and the external transistor is driven to be turned on for a certain period of time. However, as the capacity of the desired chicken increases, the current supplied by the constant current supply 1〇4 must be relatively increased. On the other hand, in order to avoid damage to the external transistor due to the voltage of the output driver circuit, the clamp circuit (10) shown in Fig. j can perform voltage limiting processing. Thus, the constant current supply is increased in order to enable the external transistor to be quickly turned on. When the size is 1〇4, due to the voltage limiting protection mechanism of the clamp circuit (10), after the first transistor is discussed, the constant current supply 104 still charges the clamp circuit 108 to raise the output signal 2 to a high level (4). Body, _ start the rich, the constant current supply 1 曰 04 continues to clamp the clamp circuit (10) to the level of the clamp circuit 1G8. When the gate voltage of the first electric two-body 超过1 exceeds the preset tank level, the excess current will be conducted to the ground through the home circuit, so that the energy supplied by the constant current supply 104 has a knife system. Because of the pressure limit Laihu. Change (4), the axis and the transistor open 201020714 The time rule of the '(10) 卩 caused (4), the efficiency of the system. The voltage-limiting protection of the clamp circuit reduces the current that is added by the turn-on time to be easily affected by three, resulting in poor circuit efficiency. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a high-efficiency output driving circuit and the present invention discloses a high-efficiency output driving circuit including a level-adjustable converter for performing an input signal Voltage level conversion to generate a plurality of signals; an output stage for generating an output driving signal to an output according to the plurality of pre-drive signals; and a preset driving circuit 'lighting up to the scale and turning to the output stage The laying (four) circuit includes a second current source 'for providing a first predetermined current; a second predetermined current source for providing a first predetermined current; and a clamping circuit for limiting the plurality of driving signals One of the voltage values; and a plurality of preset drivers, the first predetermined current source, the second predetermined current source, and the clamp circuit are used in the level converter to determine the plurality of The predetermined current and the second current are generated to generate the plurality of pre-drive signals to the output stage. The present invention further discloses a method for improving the efficiency of an output driving circuit, the method comprising: generating a plurality of signals according to an input signal and generating a synchronization signal; generating a --transition domain according to the synchronization signal and generating a second predetermined current, The first predetermined current and the second predetermined current of the 201020714 generate a plurality of pre-drive signals; and generate an output drive signal according to the plurality of pre-drive signals. [Embodiment] Ο
G 請參考第3圖，第3圖為本發明實施例一輸出驅動電路3〇之示意 圖。輸出驅動電路30包含一準位轉換器3〇2、預置驅動電路3〇〇及一 輸出級304。準位轉換器302用來根據一輸入訊號&進行電壓位準轉 換以產生一第一讯號Si與一第二訊號心。預置驅動電路3⑻包含有 一第-預置驅動器P_1 —第二預置驅動器p—2…第一預^電流源 306、一第二預定電流源3〇8及一箝位電路31〇。其中第一預定電流源 3〇6用來提供二第-預定電流&。第二預定電流源3〇8用來提供一第 二預定電流12。第-預預置驅動器pj及第二預置驅動器p—2麵接於 準位轉換器302、第-預定電流源3〇6及第二預定電流源，用來根 據第-訊號S!、第二訊號S2、第一預定電流^及第二預定電流匕，產 生一 ^-預驅動訊號SP1及-第二預驅動訊號〜以供驅動輸出級 3〇4。藉位電路310耦接於預置驅動器pj與一接地端，用來限制第一 驅動，號sP1之電壓大小。輸出級3〇4包含一第一電晶體峨及一第 「電晶體MN2 ’其输於預置驅動電路·，用來根據第—預驅動訊 號SP1與第一預驅動訊號&，產生一輸出驅動訊號& 一至一輸出端G. Referring to FIG. 3, FIG. 3 is a schematic diagram of an output driving circuit 3A according to an embodiment of the present invention. The output drive circuit 30 includes a level converter 3〇2, a preset drive circuit 3〇〇, and an output stage 304. The level converter 302 is configured to perform voltage level conversion according to an input signal & to generate a first signal Si and a second signal center. The preset drive circuit 3 (8) includes a first pre-set driver P_1 - a second pre-driver p - 2 ... a first pre-current source 306, a second predetermined current source 3 〇 8 and a clamp circuit 31 〇. The first predetermined current source 3〇6 is used to provide a second-predetermined current & The second predetermined current source 3〇8 is used to provide a second predetermined current 12. The first pre-preset driver pj and the second preset driver p-2 are surface-connected to the level converter 302, the first predetermined current source 3〇6 and the second predetermined current source for using the first signal S! The second signal S2, the first predetermined current ^ and the second predetermined current 产生 generate a pre-drive signal SP1 and a second pre-drive signal ~ for driving the output stage 3〇4. The borrow circuit 310 is coupled to the preset driver pj and a ground terminal for limiting the voltage of the first driver, the number sP1. The output stage 3〇4 includes a first transistor 峨 and a “transistor MN2 ′′ which is input to the preset driving circuit for generating an output according to the first pre-drive signal SP1 and the first pre-drive signal & Drive signal & one to one output
Li其Γ ’輸出端314較佳地係柄接一電容性負載，該電容性負載較 屬氧化半導體場效電晶體。㈣ 第-電曰曰體ΜΝ2係以串連輕财式連接，較佳地皆為_金屬氧 201020714 化半導體場效電晶體，其連接方式係如第3圖所示。 在第3圖中，輸出驅動電路3〇較佳地包含有一單擊電路μ】。單 擊電路312用來根據準位轉換器3〇2之一同步信號Ssyn產生一單擊訊 號Sos。其中較佳地同步信號Ssyn係於輸入訊號&之每一時脈週期中 於準位轉換器302將輸入訊號Sl進行電壓位準轉換後產生。此外，單 擊電路312透過產生單擊訊號s〇s以控制第二預定電流源3〇8之輪出。 ❹第二預定電流源308耦接於單擊電路312與預置驅動器及卩2， 可根據單擊訊號Sos產生第二預定電流至預置驅動器ρ—〗。因此， 透過本發明第二預定電流源3〇8之設計，根據單擊訊號&所產生之 第二預定電流I2可以輔助第-預定電流源鄕供應後端電容性負戟之 驅動，以降低所需之第-預定電流^的大小，進而提升電路效率。 進一步說明，請參考第4圖，第4圊為第3圖中輸出驅動電路3〇 之相關訊號之時序圖。單擊電路312較佳地可於輸入訊號&之每 ❿脈週期CLK中’當準位轉換器3〇2將輸入訊號&進行電壓位準轉換 後，產生單擊訊號sos。舉例來說，單擊電路312可於一時脈週期 開始後之-時間點τ2產生單擊訊號Sqs ;其中時間點Τι至A之期間， 輸出驅動電路30經由準位轉換器3〇2將輸入訊號&調整轉換產生曰第 一訊號s,與第二訊號S2。換句話說，單擊電路312可隨第一訊號& 與第二訊號S2之產生時間及頻率來產生單擊訊號S〇s。 ) 1 . 除此之外，帛二預定電流源308較佳地可於單擊城s〇s之訊 期内’提供第二預定電流I”舉例來說，當單擊訊號s〇s在時間點& 201020714 產生後’第-預定電流源3〇8持續產生第二預定電流^直到單擊訊號 sos周期結束（自時間點了2至時間點τ4)<>請繼續參考第4圖，第4 圖為本發明之箝位電路峨VZ1輸出鋪峨t的時序圖與習 知技術的比較。在相同第-預定電Μ大小之條件下，習知技術之電 路於時間點τ3才打開第—電晶體咖，而本發明在時間點&即已打 開第-電晶體ΜΝ1，_地，透過本發明，外接電晶體也將有較短的 開啟時間。 目此’透過本發明第二預定電流源3〇8之設計，根據單擊訊號^ 所產生之第-預定電机is可以輔助第一預定電流源供應後端電容 性負載之驅動。相較之下，f知技術為了加快開啟時間而加大定電流 供應器之从，會因輸出驅動電路之限壓保護輯生電路效率不彰之 缺點。簡單來說’本發明僅需在單擊訊號_提供第二舦電流_ 助’除了可以在祕限制下增加驅動電流以加快開啟時間，且不會讓 所提供之電流因保護功能而導通至地造成浪費，當然，第一預定電流 ❹即不需第—敢電流11或是設計為較小之電流供應，如此 來，將可以提供實現高效率、低損耗及最佳化之電路。 值付注思的是’第3圖之輸出驅動電略30係為本發日月之一實施例， ^領域f1常知識者當可據以做不同之變化及修飾，凡能達到相同功 ，笛^ I/由電路6十原理、方式或數量皆可適用於本發明。舉例來說， 第射，預置驅動電路僅包含有第-預置驅動器PJ及第二 •預置驅動器P_2 ’實際上，相同架構亦可衍生為多個預置驅動器，用 201020714 以產生複數個預驅動電流；當然、，在此情形下需產生複數個訊號，以 配合預驅動電路308之運作，相關實現方式係本領域具通常知識者所 熟知，在此不贅述。 此外’在第3圖中’第一預定電流源306較佳地係為一固定電流源。 第二預定電流源3〇8較佳地係為一脈衝電流源。輸入訊號^較佳地係 為-脈衝寬度調變信號。箝位電路31G係以—齊納二極體實現，用以 ❹限制第-驅動訊號SP1之電壓辦，賴，只魏確郷―驅動訊號 sP1不超過-預*錢位準她避免外接電晶體遭受損壞之裝置即可 適用於本發明。同樣地，第一預定電流源306可藉由任何可產生固定 電流大小之電流產生單元來實現，第二預定電流源306可藉由任何可 產生脈衝電流之電流產生單元來實現。而單擊電路312可藉由任何能 產生單擊訊號之電子裝置來實現，不論其電路原理或元件組合，皆可 適用於本發明。此外’由於單擊電路312係根據時脈訊號來運作因 此亦可以整合於準位轉換_ 302中。另外，輸出級304亦可由其它具 有緩衝及推動負載能力之電子裝置實現。 _第3圖中輸出驅動裝置3G的運作方式，可歸納為第5圖之一 流程50。流程50包含以下步驟： 步驟500 :開始 步驟502 :準位轉換器3〇2根據輸入訊號&產生第_訊號&與第 二訊號S2至預置_電路勘，且產鋼步訊號娜。 ,步驟5〇4 .早擊電路312根據同步信號Ssyii產生單擊訊號s〇s，第 201020714 二預定電流源308據以產生第二預定電流ι2。 v驟5〇6 .預置驅動電路根據第-預定電流l、第二預定電流 12、第一訊號Si與第二訊號S2產生第一預驅動訊號SP1 及第二預驅動訊號SP2至輸出級304。 步驟508:粮墙楚__ . 像第一預驅動訊號Spi及第二預驅動訊號&產生輸出 驅動訊號S(T至輸出端314。 步驟510:結束。 ❹ 味 本土明僅在單擊訊號s〇s期間增加第二預定電流L，可以在 2限制下加快開啟時間，並且不會讓所提供之電流因保護功能而排 k成/良費’將可以提供實現高效率、低損耗及最佳化之電路。 二τ上所述’本發明僅需在單擊訊號期間提供—定電流輔助供應後端 電各H負載之驅動，除了可以在箝位限制下增加驅動電流，且不會讓 所k供之電流因保護功能而排掉造成浪費如此一來將可以提供實 ©現南效率、低損耗及最佳化之電路。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所 做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知一輸出驅動電路之示意圖。 '第2圖為第1圖輸出驅動電路之相關訊號之時序圖。 12 201020714 第3圖為本發明實施例一輸出驅動電路之示意圖。 第4圖為第3圖中輸出驅動電路之相關訊號之時序圖 第5圖為本發明實施例一流程之示意圖。 【主要元件符號說明】 10、30 輸出驅動電路 102 、 302 準位轉換器 ©104 定電流供應器 106 、 300 預置驅動電路 108 、 310 箝位電路 110 、 304 輸出級 112 、 314 輸出端 306 第一預定電流源 308 第二預定電流源 〇 312 單擊電路 Si 輸入訊號 So 輸出訊號 Si 第一訊號 s2 第二訊號 Ιι 第一預定電流 h 第二預定電流 Spi 第一預驅動訊號 13 201020714The output terminal 314 of Li is preferably coupled to a capacitive load which is more dependent on the oxidized semiconductor field effect transistor. (4) The first-electrode body ΜΝ 2 is connected in series with light weight, preferably _ metal oxygen 201020714 semiconductor field effect transistor, the connection method is shown in Figure 3. In Fig. 3, the output drive circuit 3A preferably includes a click circuit [μ]. The click circuit 312 is operative to generate a click signal Sos based on the synchronization signal Ssyn of the level converter 3〇2. Preferably, the synchronization signal Ssyn is generated after the level converter 302 performs voltage level conversion on the input signal S1 in each clock cycle of the input signal & In addition, the click circuit 312 controls the rotation of the second predetermined current source 3〇8 by generating a click signal s〇s. The second predetermined current source 308 is coupled to the click circuit 312 and the preset driver and the 卩2, and generates a second predetermined current to the preset driver ρ_ according to the click signal Sos. Therefore, through the design of the second predetermined current source 3〇8 of the present invention, the second predetermined current I2 generated by the click signal & can assist the first predetermined current source 鄕 to supply the driving of the back end capacitive negative , to reduce The required first-predetermined current ^, which in turn increases circuit efficiency. For further explanation, please refer to FIG. 4, which is a timing diagram of the related signals of the output driving circuit 3A in FIG. The click circuit 312 is preferably operative in the input signal & every pulse period CLK' when the level converter 3〇2 performs voltage level conversion on the input signal & For example, the click circuit 312 can generate the click signal Sqs at the time point τ2 after the start of a clock cycle; during the time point Τι to A, the output drive circuit 30 inputs the input signal via the level converter 3〇2. The & adjustment conversion produces a first signal s, and a second signal S2. In other words, the click circuit 312 can generate the click signal S〇s with the time and frequency of the first signal & and the second signal S2. In addition, the second predetermined current source 308 is preferably capable of 'providing a second predetermined current I' during the period of clicking the city s〇s, for example, when clicking the signal s〇s at the time Point & 201020714 After the generation, the 'pre-determined current source 3〇8 continues to generate the second predetermined current ^ until the end of the signal sos cycle (from time point 2 to time point τ4) <> continue to refer to Figure 4 Figure 4 is a comparison of the timing diagram of the clamp circuit 峨VZ1 output 峨t of the present invention with the prior art. Under the same first-predetermined power size, the circuit of the prior art is turned on at the time point τ3. The first transistor, while the present invention has opened the first transistor ΜΝ1, _ ground, through the present invention, the external transistor will also have a shorter turn-on time. The design of the predetermined current source 3〇8, according to the first-predetermined motor is generated by clicking the signal ^, can assist the first predetermined current source to supply the driving of the back-end capacitive load. In contrast, in order to speed up the opening Increasing the timing of the constant current supply due to the time limit of the output drive circuit The advantages of the circuit are not effective. In simple terms, the invention only needs to click the signal _ to provide the second current _ help, in addition to the increase of the drive current under the secret limit to speed up the opening time, and will not let The current supplied is electrically isolated due to the protection function. Of course, the first predetermined current 不 does not require the first - dare current 11 or is designed to be a smaller current supply, so that high efficiency and low loss can be provided. And the circuit of optimization. The value of thinking is that the output driver of Figure 3 is a series of 30-day embodiment of the month, ^ domain f1 often knows how to make different changes and modifications Wherever the same work can be achieved, the flute can be applied to the present invention by the principle, method or quantity of the circuit 6. For example, the first shot, the preset drive circuit only includes the first pre-preset driver PJ and the second • Preset driver P_2 'In fact, the same architecture can also be derived into multiple pre-drivers, using 201020714 to generate a plurality of pre-drive currents; of course, in this case a plurality of signals are generated to match the pre-driver circuit 308. Operation Related implementations are well known to those of ordinary skill in the art and will not be described herein. Further, 'in FIG. 3' the first predetermined current source 306 is preferably a fixed current source. The second predetermined current source 3〇8 Preferably, the input signal is preferably a pulse width modulation signal. The clamp circuit 31G is implemented by a Zener diode for limiting the voltage of the first driving signal SP1. Do, Lai, only Wei Zhengyi - drive signal sP1 does not exceed - pre-* money position, she can avoid the damage of the external transistor can be applied to the present invention. Similarly, the first predetermined current source 306 can be used by any A current generating unit of a fixed current amount is generated, and the second predetermined current source 306 can be realized by any current generating unit that can generate a pulse current. The click circuit 312 can be implemented by any electronic device capable of generating a click signal, regardless of its circuit principle or component combination, and can be applied to the present invention. In addition, since the click circuit 312 operates according to the clock signal, it can also be integrated in the level conversion_302. In addition, the output stage 304 can also be implemented by other electronic devices having buffering and pushing capabilities. The operation mode of the output driving device 3G in Fig. 3 can be summarized as one of the processes in Fig. 5. The process 50 includes the following steps: Step 500: Start Step 502: The level converter 3〇2 generates a _signal & and a second signal S2 to a preset_circuit according to the input signal & and generates a steel step signal. Step 5〇4. The early strike circuit 312 generates a click signal s〇s according to the synchronization signal Ssyii, and the 2010201214 second predetermined current source 308 generates a second predetermined current ι2. Step 5: 6. The preset driving circuit generates the first pre-drive signal SP1 and the second pre-drive signal SP2 to the output stage 304 according to the first predetermined current l, the second predetermined current 12, the first signal Si and the second signal S2. . Step 508: The grain wall __. The first pre-drive signal Spi and the second pre-drive signal & generate an output drive signal S (T to the output terminal 314. Step 510: End. 味 味味明 only click on the signal Increasing the second predetermined current L during s〇s can speed up the turn-on time under the 2 limit, and will not allow the supplied current to be discharged due to the protection function. It will provide high efficiency, low loss and most The circuit of Jiahua. The invention described above is only required to provide the current supply to the back end of each H load during the click signal, except that the drive current can be increased under the clamp limit and will not be allowed. The current supplied by the current is drained due to the protection function, so that the circuit can provide the current efficiency, low loss and optimization. The above is only the preferred embodiment of the present invention. The average variation and modification of the scope of the invention should be within the scope of the invention. [Simplified illustration of the drawing] Fig. 1 is a schematic diagram of a conventional output driving circuit. 'Fig. 2 is the output driving of Fig. 1. When the circuit is related to the signal Fig. 12 is a schematic diagram of an output driving circuit according to an embodiment of the present invention. Fig. 4 is a timing chart of related signals of an output driving circuit in Fig. 3. Fig. 5 is a schematic diagram of a process according to an embodiment of the present invention. Main component symbol description] 10, 30 output drive circuit 102, 302 level converter ©104 constant current supply 106, 300 preset drive circuit 108, 310 clamp circuit 110, 304 output stage 112, 314 output 306 first Predetermined current source 308 Second predetermined current source 〇 312 Click circuit Si input signal So output signal Si first signal s2 second signal Ιι first predetermined current h second predetermined current Spi first pre-drive signal 13 201020714
Sp2 第二預驅動訊號 S〇s 單擊訊號 Ssyn 同步信號 MN1 第一電晶體 MN2 第二電晶體Sp2 second pre-drive signal S〇s click signal Ssyn synchronization signal MN1 first transistor MN2 second transistor
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