TW201019591A - Integrator-based common-mode stabilization technique for pseudo-differential switched-capacitor circuits - Google Patents

Abstract

A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout-), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout-) at a desirable level.

Description

201019591 V. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention:

VI. Description of the Invention: Ο Technical Field of the Invention The present invention relates to a pseudo differential switched capacitor circuit involving an integral form common mode voltage stabilization technique. .. [Prior Art] 201019591 In high-accuracy switched capacitive circuits, high-gain and high-linearity amplifiers are often required, and system performance is often determined by the efficiency of the amplifier. However, in advanced processes, in order to ensure the reliability of the circuit, the operating voltage of the circuit must be reduced. Therefore, the signal range of the amplifier is severely compressed, which increases the design difficulty of the amplifier. In order to maintain a sufficient signal-to-noise ratio, the power consumption of the amplifier is increased. ❹ The first A diagram shows a conventional fully differential amplifier circuit 10 that increases the circuit's ability to combat noise and increase the amplitude of the circuit signal. The fully differential amplifier circuit 10 uses a common-mode feedback circuit (CMFB) 102 to stabilize the output common-mode voltage (output 〇ut+/Out-). Since the total current of the circuit is controlled by the tail current MOS transistor Mcl, the common-mode disturbance of the input terminal In+/In- will not affect the circuit. Performance. Therefore, the fully differential amplifier circuit 10 has an extremely high common mode noise rejection ratio (CMRR). However, the transistor Mcl compresses the output signal range of the circuit' and is therefore detrimental to the operation of the low voltage circuit. In order to increase the signal output range of the circuit, a pseudo-differential amplifier circuit 12 as shown in Fig. B is used. The pseudo differential amplifier circuit 12 eliminates the tail current MOS transistor Mcl of the first A picture, but 201019591 means that this circuit will have no common mode noise rejection function. Therefore, the common mode noise of the input terminal In+/In- will be amplified by the pseudo differential amplifier circuit 12, which seriously affects the performance of the circuit. "Full differential amplifier circuit 1" (first A picture) and pseudo differential amplifier circuit 13⁄4 The operation of Figure 1B will be explained in the following paragraphs. The first figure shows the operation of the switched capacitor circuit 20 using a fully differential amplifier 1〇4. Only common mode voltage perturbations (AVcm) are considered here, and other parent flow # numbers are not considered. At the sample phase (shown at the left end of the figure), the common mode voltage disturbance (AVcm) is sampled by two capacitors C. In the amplification phase (shown at the right end of the figure), due to the relationship of the common mode feedback circuit (CMFB), the output common mode voltage will be maintained at VCtt^ according to the principle of charge conservation, which can be obtained as shown in the figure. The common mode voltage ν χ β input to the input voltage of the amplifier 104 is reflected by the voltage of the common mode voltage (Δν < ^). However, this common mode voltage perturbation (ΔVcm) drift can be tolerated as long as the amplifier 1〇4 ❹ has a sufficiently large input common mode range. The third diagram shows the operation of the switched capacitor circuit 30 using the pseudo differential amplifier 124. Since the pseudo differential amplifier 124 does not have a common mode feedback circuit (CMFB), its output lacks a forced force to control its output level. Thus, circuit 30 will perturb the input common mode voltage (which produces twice the common mode gain, where the common mode gain and differential mode gain are the same. 201019591 Once circuit 30 is applied to the series circuit as shown in the fourth figure) The pipeline analog-to-digital converter, since each stage has twice the common-mode gain, the latter circuit will be saturated and the circuit will be out of normal operation. For details of the analog-to-digital converter, refer to another patent application of the same applicant (titled "shared operational amplifier technology with adjustable resolution of the stage before the pipeline or cyclic analog to digital converter") The above pseudo-differential switched capacitor circuit requires a circuit mechanism that effectively stabilizes the common-mode voltage to maintain a sufficiently large signal amplitude in a low-voltage process. Several methods are currently available in the literature for the purpose, as described below. Common mode feedback circuit (CMFB) «Intuitive way is to use the common mode feedback circuit (CMFB) commonly used in fully differential circuits to stabilize the output common mode The fifth figure shows a pseudo-differential switched capacitive circuit 5〇 using a common mode feedback circuit 102, which is a schematic diagram of the amplified phase of the third figure. Due to the common mode feedback relationship, the output common mode level can be maintained at The ideal common mode voltage Vcm. · Since there is no tail ^, the current source, any input common mode voltage disturbance (△,) will cause the current change of the circuit 5〇, resulting in the circuit performance changing with the input common mode voltage. The circuit performance is seriously attenuated. 201019591 . 2. Differential floating sampling (DFS) mechanism

The reason why the pseudo-differential switching capacitor circuit generates the amplified common-mode gain is that the main reason is that when sampling the phase, the capacitor will sample the input common-mode voltage perturbation (A Vcm>. When the capacitor C is the same size, there will be 2xCxA Vcm The common mode voltage change charge is sampled by the capacitor, resulting in twice the common mode gain. If the capacitor can reduce the common mode voltage disturbance (AVcm) sampling, the common mode gain can be reduced, and the influence of the common mode voltage change on the circuit can be reduced. For this purpose, the differential floating sampling (DFS) circuit 60 of the sixth diagram can be used, which is disclosed in J. Li and UK Moon, "A 1.8-V 67-mW 10-bit 100 MS/S pipelined ADC using time- Shifted CDS technique, ΛIEBE J. SoZid-Siaie Circuits, vol. 39, pp. 1468 - 1476, Sep. 2004 ° Circuit 60 uses two single-ended amplifiers 602A/602B in the positive and negative paths, which function similarly to the third diagram The difference is that at the sampling phase (active 0 ❿ 1), the upper plates of capacitors C1 and C4 (connected to the input of amplifier 602A/602B) receive the common-mode voltage via the 01 control switch, while capacitors C2 and C3 The upper plate is floated by the dotted line The switch is in a floating state. Once there is an input common mode voltage disturbance (ΔVcm), only the capacitor C1 or C4 will sample the common mode voltage change charge (lxCx^vcm), and the capacitor C2 or C3 is floating due to the upper plate. The state 'bypasses the input common mode voltage disturbance. Thus, the common mode gain of circuit 60 will be one and will not amplify the input common mode voltage disturbance. Differential Floating Sampling (DFS) circuit 60 201019591 does not require additional The active circuit (such as the common mode feedback circuit) can reduce the power consumption of the circuit. However, the switch in the circuit 60 causes a charge injection effect, causing additional common mode voltage drift. When the circuit 60 is applied In the series circuit of the pipeline analog to digital converter (figure 4), the latter circuit will have a large common mode voltage drift, resulting in circuit performance degradation. ❹3, common mode pre-grant (common-mode feed -forward, CMFF) Mechanism Figure 7A shows a common mode pre-application (CMFF) circuit 70 whose stability concept is similar to the sixth picture, but can further reduce the common mode gain to 0. Seventh A to seventh C Expose Τ · Ueno, Τ · Ito et al., "A 1.2 V, 24 mW / ch, 10 bit, 80 MSample / s pipelined A / D converters, w JVoc. O / aCC, pp.501-504, Sep · 2006. The common mode voltage is sensed using a common mode (CM) Φ detector 702, and then the common mode voltage disturbance is reflected to the upper plate of the capacitor by an analog adder/subtracter 704. In this way, there will be no common mode voltage disturbance (Δνεπι) sampled by the capacitor, and the circuit 70 will not have any common mode gain, which can effectively eliminate the common mode voltage drift problem of the circuit. However, circuit 70 still suffers from the problem of common mode voltage drift due to the charge injection effect of the switch. 201019591 FIG. 7B shows a detailed circuit diagram of the common mode detector 702 of the seventh diagram, and the seventh C diagram shows a detailed circuit diagram of the analog adder/subtracter 7〇4 of the seventh diagram. The analog adder/subtracter 7〇4 is a two-stage amplifier, wherein the first stage circuit 7041 is a four-input single-ended amplifier, and the second stage 7042 is a common source amplifier. The analog adder/subtractor 7〇4 uses the Miller compensation method for frequency compensation. The output and input of the circuit 7〇4 are connected to a single gain amplifier. The open loop gain of the circuit will affect the accuracy of the analog add/subtracter 704. degree. Since the CMFF circuit 7 does not use feedback control to reduce the common mode voltage of the circuit, the finite gain error and settling error of the analog adder/subtracter 7〇4 are still amplified by the circuit 7〇. In order to reduce the common mode voltage error, it is necessary to try to increase the open loop gain and bandwidth of the analog adder/subtractor 704, but this will consume a large amount of power. The common mode of the above-described pseudo-differential switching capacitor circuit stabilizes the shortcomings of the prior art, and therefore it is urgent to propose a novel technique to effectively reduce the common mode voltage drift caused by the charge injection effect. SUMMARY OF THE INVENTION In view of the above, one of the objects of the present invention is to provide a common mode stabilization technique applied to a pseudo differential switched capacitor circuit, particularly an integral form technique 201019591, for substantially reducing charge injection. Common mode voltage drift caused by effects. In accordance with an embodiment of the invention, the differential floating-sampling (DFS) technique is used to cause the pseudo-differential switched capacitive circuit to have a gain value of one, thereby bypassing the input common mode voltage disturbance. Thereby, the input common mode disturbance and the common mode error caused by the charge injection effect can be sensed at the chirp output of the switched capacitor circuit. An integrator is used to sense the total output common mode disturbance, and the integrated output is fed back to the pseudo differential switching capacitive circuit using differential floating sampling (DFS) technology, thereby stabilizing the output common mode level to a required position quasi. When in the amplified phase (¢2), the integrator detects the common mode voltage disturbance of the differential positive output (V0Ut+) and the negative output (V〇ut_). When in the sampling phase (4 1), the integrator integrates and feeds the output of the integrating amplifier back to the switched capacitor circuit, thus forming a common mode negative feedback loop, using ® to adjust the differential positive output (V〇ut+) And negative output (V0Ut-). [Embodiment] The eighth figure shows a pseudo-differential switched capacitor circuit 80 according to an embodiment of the present invention, which uses an integral-mode common-mode stabilization (IB-CMS) technique. In the present embodiment, circuit 80 11 201019591 includes a pseudo differential switched capacitor circuit 802 and an integrator 804 using differential floating sampling (dfs) techniques. In the figure, control signal 0 1 represents the sampling phase control signal, i.e., active 01 indicates that circuit 80 is in the sampling phase. Another control signal ¢2 represents the amplified phase control signal, i.e., the active 0 2 indicates that the circuit 80 is in the amplified phase. Generally, the sampling phase control signal ¢1 and the amplification phase control signal ¢2 may be square waves that do not overlap each other. The pseudo-differential switching electric valley type circuit 802 using the differential floating sampling (DFS) technique in the present embodiment includes a positive path and a negative path. In the positive path, the input end of the first single-ended amplifier 8021 is electrically coupled to the first ends of the first capacitor Cl and the second capacitor C2, and the capacitors C1/C2 are electrically connected in parallel with each other. In the present embodiment, the term "electricaUy" means that a π piece/two end point is directly connected by a wire, or is indirectly connected by a switch, and the connection relationship can be illustrated and illustrated. Description is known. The output of the first amplifier 8021 provides forward rotation out of v〇ut+. The two ends of the first capacitor 〇1 and the second capacitor C2 are electrically connected to the positive input. The first capacitor ^ is electrically connected between the positive input % pin and the input end of the first amplifier 8〇21 via the 0 1 and 0 2 control switches, and the connection state is as follows: when sampling the phase, the first capacitor cn is directly connected. Between the positive input Vin+ and the rounder (cmi) of the integrator 8〇4; when the phase is amplified, the lower plate of the first capacitor is connected to the positive output vGUt+, and the upper plate of the first capacitor C1 and the integrator 12 201019591 The output (cmi) is separated. The second capacitor C2 is electrically connected between the positive input Vin+ and the input end of the first amplifier 8〇21 via a control switch, and the connection state is as follows: when sampling the phase, the lower plate of the second capacitor C2 Connected to the positive input Vin+, and the upper board is floating, which means that the node does not have a DC path; when the phase is amplified, the lower plate of the second capacitor C2 is connected to the reference voltage VR' and the upper plate is connected to the first amplifier 8021. Input. In the negative path, the connection state of the second single-ended amplifier 8022, the third capacitor C3, and the fourth capacitor C4 is similar to that of the first single-ended amplifier 8021, the second capacitor C2, and the first capacitor C1. That is, the connection of the second single-ended amplifier 8022 is similar to that of the first single-ended amplifier 8021, and the connection state of the third capacitor C3 is similar to that of the second capacitor C2' and the connection state of the fourth capacitor C4 is similar to that of the first capacitor C1. The connection state of the above components is as follows in Table 1. Lu meter-sampling phase amplification phase C1 is between the lower board and the upper board to the first amplifier input C2 lower board to Vu+; the upper board floats the lower board to Vr; the upper board is connected to the first amplifier input C3 lower board to Vin_ Upper plate floats down to Vr; upper plate to 竿- 13 201019591 * Poor" upper plate 1 large input C4 between Vin- and Cmi lower plate to Vout-; upper plate to the first input to 5 'At the sampling phase (active 01), the first capacitor C1 and the fourth capacitor C4 (via the 0 χ control switch) sample the input common mode disturbance, and the upper plates of the second capacitor C2 and the third capacitor C3 are indicated by the broken lines. The reason for the floating switch 处于 is in the floating state. The first capacitor C1 or the fourth capacitor will sample the common mode voltage perturbation (ΔVcm) and thus sample to the common mode voltage change charge (lxCxAVcm), while the floating second or third capacitor C3 will not sample the charge. Therefore, the gain value of circuit 80 is one, so the input common mode voltage disturbance will not be amplified. The DFS circuit 802 is similar to the circuit 60 of Figure 6, without the need for additional active circuitry (e.g., common mode feedback circuitry)' thus reducing the power consumption of the circuitry. As described in Figure 6, the φ switch causes a charge injection effect, causing additional common mode voltage drift. Integrator 804 is used as a non-inverting integrator in this embodiment to overcome the charge injection effect. Integrator 804 has two inputs that are coupled to outputs Vout+ and Vout- of DFS circuit 802, respectively. The negative input of the integrating amplifier 8040 is connected to the parallel sampling capacitors Cil and Ci2 via the ¢1 control switch, while the positive input of the integrating amplifier 8040 receives the input bias.

Vb is connected to the parallel sampling capacitors Cn and Cu via the ς6 2 control switch. Furthermore, the positive input is connected to the output (cmi) via the integrating capacitor Ci3. The output (cmi) of the integrating amplifier 8040 is coupled to the input of the amplifiers 8021/8022 via a 0 1 control switch.

When the integrator samples the phase (active ¢ 2), the integrator 804 is connected to the DFS circuit 802 via the ¢2 control switch for detecting the common mode electrical waste disturbance of the output terminals Vt) Ut+, V<) Ut- The common mode error caused by the input common mode disturbance and the dfs circuit 802 due to the charge injection effect. At this time, the lower plates of the sampling capacitors Cu and Cu are connected to the DFS circuit 802, and the upper plate is connected to the positive input terminal of the amplifier 8040. In the integral phase (active 1), the lower plate of the sampling capacitor Cn and Cu is connected to the common mode voltage, which is the required input voltage of the circuit 8〇2, and the negative input of the upper (four) phase is connected to the amplifier 8040. Human end. At this time, the integrator class performs the common mode disturbance integration, and feeds the output voltage cmi back to the upper capacitor of the first capacitor and the fourth capacitor, thereby forming a common mode negative feedback loop. Since the integrator 804 has a charge accumulation characteristic, the output voltage V〇ut+/Vout- can be gradually adjusted to stabilize the output common mode level at the ideal common mode level. The connection relationship of the above components is shown in Table 2 below.

15 201019591 Integral phase (active 0 1 ) Integrator sampling phase (active 02) Cu lower plate to Von; upper plate to amplifier negative input lower plate to DFS; upper plate to amplifier positive input terminal Ci2 lower plate to Voa; upper plate To the negative input of the amplifier to the DFS; the upper input to the positive input of the amplifier when designing the integrator 804, there are some important points to note: ❹ 1. The sampling capacitor Cii, Cu and the integrated capacitor Ci3 must be properly selected to ensure system stability. . In general, the sampling capacitors Cn, Ci2 must be smaller than the integrating capacitor Ci3. 2. The amplifier 8040 circuit gain will affect the stable output \^. ^+/乂. ^-the common mode voltage, too small gain will increase the common mode error. In practice, according to the circuit simulation results, the 2〇dB integral amplifier gain will only cause 30mV round-out common mode voltage error. This error will be tolerated. When the feedback control mechanism described above is applied to the serial circuit architecture, since each stage has the feedback adjustment mechanism of the present invention, the common mode error of each stage of the control unit is only caused by the induced error caused by the integrating amplifier. In this way, the integrator 8〇4 can be implemented using only a single stage amplifier. According to this embodiment, the integrator 804 can use only a single stage, gaining, low power consumption amplifier. Compared with the aforementioned seventh A diagram, the power consumption of the integrator 804 of the present embodiment 16 201019591 is much lower than that of the analog adder/subtracter 704 of the common mode preamble circuit (CMFF) 70. Furthermore, integrator 804 of the present embodiment has only one capacitor that samples the output voltage of the integrator (and therefore the gain value is one), while the common mode pre-circuit (CMFF) 70 has two capacitors that sample the analog adder/subtracter 704. Output voltage. Therefore, the load and power consumption of the integrator 804 can also be greatly reduced. This embodiment can therefore greatly reduce the common mode voltage drift caused by the charge injection effect. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application. [Simple description of the diagram] The first diagram shows the traditional fully differential amplifier circuit. The first B diagram shows a conventional pseudo-differential amplifier circuit. The second figure shows the operation of a switched capacitor circuit using a fully differential amplifier. The second figure shows the operation of a switched capacitor circuit using a pseudo differential amplifier. The fourth figure shows a conventional pipeline analog to digital converter. 17 201019591 The fifth figure shows the pseudo-differential switching using the common mode feedback circuit. The sixth figure shows the differential floating sampling (DFS) circuit. Circuitry Figure 7A shows the common mode pre-application (CMFF) circuit. Electricity % map < Xiang fine example (pseudo-differential) switching capacitive circuit common mode voltage stabilization (IB-CMS) technology. Figure 7B shows the detailed circuit diagram of the common mode detector of Figure 7A. <Pseudo-difference, which uses the integral form, the seventh C-picture shows the analogy adder/subtractor of the seventh A diagram. The eighth diagram shows the actual implementation of the present invention. [Main element symbol description] 10 Fully differential amplifier circuit 12 Pseudo-differential amplifier circuit 20 Fully Differential Amplifier Switching Capacitor Modem 30 Pseudo-Differential Amplifier Switching Capacitor Circuit 50 Pseudo-Differential Switching Capacitor Circuit 60 Differential Floating Sampling (DFS) Circuit 70 Common Mode Pre-Circuit Circuit (CMFF) 80 Pseudo-Differential Switched Capacitor Circuitry 102 Common Mode Feedback Circuit (CMFB) 104 Fully Differential Amplifier 124 Pseudo-Differential Amplifier 602A/602B Amplifier 18 201019591 702 Common Mode (cm) Detector 704 Analog Plus/Subtracter 802 Differential Floating Sampling (DFS) Circuitry 804 Integrator 7041 (First Stage) Four Input Single-Ended Amplifier 7042 (Second Stage) Common Source Amplifier 8021 First Single-Ended Amplifier

8022 second single-ended amplifier 8040 integrating amplifier

In+/In_ input

Out+/Out-output ί

Me 1 tail current MOS semi-transistor △Vcm common mode voltage disturbance

Vcm common mode voltage

Common mode voltage at the input of the Vx amplifier C Capacitor C1/C2/C3/C4 Capacitor 01 Sampling phase control signal Φ2 Amplifying the phase control signal

Vin+ positive input

Vin- Negative input V〇ut+ Positive output 201019591 V〇ut_ Negative output

Vr reference voltage

Vb input bias

Cil, Ci2 sampling capacitor Ci3 integrating capacitor cmi output of the integrating amplifier ❹

Claims (1)

201019591 VII. Patent application scope: 1. A pseudo differential switching capacitor circuit, which uses an integral form common mode voltage stabilization technology, the pseudo differential switching capacitor circuit comprises: a differential floating sampling (DFS) circuit, The pseudo-differential architecture has a common mode gain value of one. The DFS circuit has a differential positive input (Vin+) and a negative input (Vin-), and has a differential positive output (Vout+) and a negative output (V). 〇 ut_ ), and an integrator electrically coupled to the differential positive/negative output, the integrator detecting a common mode voltage disturbance of the differential positive output (vout+) and the negative output (vout−) The integrated output is output to the DFS circuit, thereby stabilizing the output common mode level of the differential positive output (Vout+) and the negative output (Vout-) to an expected level. 2. The pseudo differential switched capacitor circuit of claim 1, wherein the integrator is a non-inverting integrator. 3. The pseudo differential switched capacitor circuit of claim 1, wherein the integrator comprises: an integrating amplifier having a positive input and a negative input; a first sampling capacitor and a second sampling Capacitors, which are electrically connected in parallel; 21 201019591 an integrating capacitor connected between the output of the integrating amplifier and the negative input; wherein the integrating amplifier is connected to the first and second sampling capacitors via a switch. 4. The pseudo differential switched capacitor circuit of claim 3, wherein the integrator integrates at an integrated phase (0 1) and feeds back an output of the integrated split amplifier to the DFS circuit. Thus, a common mode negative feedback loop is formed for adjusting the differential positive output (Vout+) and the negative output (Vout-). 5. The pseudo differential switched capacitor circuit of claim 4, wherein the integrator detects the differential positive output (Vout+) and the negative output when the integrator samples the phase (¢2). Common mode voltage perturbation of Vout-). 6. The pseudo differential switched capacitor circuit of claim 5, wherein the integrator further comprises an integrated phase (0 1) control switch and an integrator sampling phase (¢2) control switch. 7. The pseudo differential switched capacitor circuit of claim 6, wherein, when in the integrated phase, the first and second sampling capacitors are connected to a common mode voltage via the Φ 1 control switch, and The Ψ1 control switch is connected to the negative input of the integrating amplifier. 22 201019591 8. The pseudo-differential switched capacitor circuit according to claim 7, wherein when the phase is integrated, the first and second terminals are respectively connected to the difference by the control switch The positive output (v〇ut+) and the negative output (V〇ut-)' are connected to the positive input of the integrating amplifier via the 0 2 control switch. The pseudo-differential switched capacitor circuit of the invention of claim 8, wherein the DFS circuit comprises: a positive path including a first single-ended amplifier, a first capacitor, and a first power The first and second capacitors are electrically connected in parallel; and a negative path includes a second single-ended amplifier, a third capacitor, and a fourth capacitor, wherein the third and fourth capacitors are electrically connected to each other Parallel; wherein the output of the integrating amplifier is connected to the input of the first and second single-ended amplifiers via the 0" switch, and the outputs of the first and second single-ended amplifiers respectively provide the differential positive output ( 〇 + ) 负 负 如 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪 伪(Vin+) and the output of the integrator; when the phase is amplified, the lower plate of the first capacitor is connected to the positive output (vout+); and 23 201019591 the second capacitor is electrically controlled via the 01 and 0 2 control switches Sexually connected to the positive input (Vin+) and the first Between the inputs of the terminal amplifiers, the connection type is as follows: When sampling the phase, the lower plate of the second capacitor is connected to the positive input (Vin+)' and the upper plate of the second capacitor is floating; when the phase is amplified The lower plate of the second capacitor is connected to the reference voltage, and the upper plate of the second capacitor is connected to the input of the first single-ended amplifier. 11. The pseudo-differential switching capacitor as described in claim 1 The circuit, in the sampling phase _, the above four electric materials are connected between the positive input and the product (4) output; when the phase is amplified, the lower plate of the fourth capacitor is connected to the positive wheel (vout+) And the third capacitor is connected between the input of the piano (Vin_) and the input of the second single-ended amplifier via the 4 1 and 4 2 control, and the connection is called m, the lower of the third capacitor The board is connected to the negative wheel (ln) and the third capacitor is connected; and the lower plate of the third capacitor is connected to the reference voltage, and the upper plate is connected to the wheel of the second single-ended amplifier In. twenty four