201019476 vmw “J08-0241 29029twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及積體電路晶片，且 特別是有關於一種橫向擴散金氧半導體(laterally diffused metal oxide semiconductor, LDMOS)元件及包含 LDMOS 元 件之積體電路晶片。 【先前技術】 橫向擴散金氧半導體(LDMOS)是半導體製程中廣為 使用的一種電源元件。LDMOS可提供較高的崩潰電壓 (Vbd) ’並且在操作時可具有低的導通電阻(〇n_resistance， Ron) ’因此LDMOS是常用作為電源管理IC(p〇wer management IC，PMIC)中的高壓元件。互補式金氧半導體_ 橫向擴散金氧半導體元件製程（CMOS_DM〇s process， CDMOS process)以及HV LDMOS類比製程，即是電源管 理1C普遍採用的製程平台。 典型的電源管理1C是在同一基底上建立HVPMOS和 ❹ LDNMOS。但由於HVPM〇s的汲極源極導通電阻 (drain/source on-resistance，Rdson；^LDNMOS 大上三至四 倍，在電路没計上為求阻抗匹配以及反應的上升時間與下 降時間的匹配，會把在同一組中的HVPM〇s佈局(1吖〇饥） 面積設計較LDNMOS來的大。一般而言，為了減少 HVPMOS在電源管理IC巾所佔有的面積，通常會採用在 操作時具有低RdSQn的LDNMOS來取代大尺寸的 HVPMOS，也就是在電源管理IC上使用多個lDNM〇s。 201019476 ^08-0241 29029twf.doc/n 然而，以LDNMOS取代HVPMOS後會使LDNM〇s的源 極相對地處在高電壓的工作條件下，此情形容易造成基底 與LDNMOS源極端存在電位差，進㈣發兩者間的漏電 流。 【發明内容】 有鑑於此，本發明提供一種半導體元件，其具有隔離 環。 • ^發明另提供一種積體電路晶片，可以有效防止漏電 流的發生。 本發明提出一種半導體元件，其包括N型深井區、p 型井區、閉極結構、P型基體區、第-N型摻雜區、第二 付推雜區、第—隔離結構以及N型隔離環。N型深井區 位於基底中。P型井區位於_深井區之外圍。閉極結構 ，：於N型冰井區的基底上。p型基體區配置於n型深井 二位於閘極結構之-侧。第—㈣摻雜區配置於p 癱 π二4區中。第二摻雜區配置於N型深井區中，且位 」構之另—側。第—隔離結構配置於閘極結構與第 m之間。Ν型隔離軸對應Ν型深井區之邊緣 声大置於Ν型深井區中’其中Ν型隔離環的摻雜濃 度=型深井區的摻雜濃度。 型漂移區，配置於中’上述之半導體元件更包_ 在本發明之i訾隔離結構之下方。 型輕摻雜區，航班實例中’上述之半導體元件更包括n 〜、°°配置於閘極結構與第一 N型摻雜區之間。 201019476 ------008-0241 29029twf.doc/n 在本發明之—實施例中，上述之半導體元件更包括p 配置於P型井區中，其中p型防護環的掺雜濃度 大於P型井區的摻雜濃度。 -本發明之—實施例中，上狀半導體元件更包括第 二隔離結構，配置於P型基舰與Ρϋ井區之間。N型隔 離環例如是位於第二隔離結構之下方。201019476 vmw "J08-0241 29029twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and an integrated circuit chip, and more particularly to a laterally diffused metal oxide semiconductor (laterally Diffused metal oxide semiconductor (LDMOS) device and integrated circuit chip including LDMOS device. [Prior Art] Lateral diffusion metal oxide semiconductor (LDMOS) is a power supply component widely used in semiconductor manufacturing. LDMOS can provide high breakdown voltage. (Vbd) 'and can have low on-resistance (〇n_resistance, Ron) during operation' Therefore LDMOS is commonly used as a high voltage component in power management ICs (PMICs). Complementary MOS _ The CMOS DM process (CDMOS process) and the HV LDMOS analog process are commonly used in power management 1C. Typical power management 1C is to build HVPMOS and ❹ LDNMOS on the same substrate. HVPM〇s bucker source on-resistance (drain/source on-resistance, Rdson; ^LDNMOS large Three to four times, in order to match the impedance and the rise time and fall time of the response, the HVPM〇s layout (1 hunger) area design in the same group is larger than that of the LDNMOS. In order to reduce the area occupied by the HVPMOS in the power management IC towel, an LDNMOS having a low RdSQn during operation is usually used instead of a large-sized HVPMOS, that is, a plurality of lDNM〇s are used on the power management IC. 201019476 ^ 08-0241 29029twf.doc/n However, replacing HVPMOS with LDNMOS causes the source of LDNM〇s to be relatively high voltage operating conditions. This situation tends to cause a potential difference between the substrate and the LDNMOS source terminal. In view of the above, the present invention provides a semiconductor device having an isolation ring. The invention further provides an integrated circuit chip which can effectively prevent leakage current from occurring. The component includes an N-type deep well region, a p-type well region, a closed-pole structure, a P-type base region, a first-N-type doped region, a second-doped hybrid region, a first-isolation structure, and a N Isolation ring. The N-type deep well area is located in the basement. The P-type well area is located at the periphery of the _ deep well area. The closed-pole structure: on the base of the N-type ice well area. The p-type base area is arranged in the n-type deep well 2 at the gate Structure - side. The first (d) doped region is disposed in the p 瘫 π 2 region. The second doped region is disposed in the N-type deep well region and is located on the other side. The first isolation structure is disposed between the gate structure and the mth. The 隔离-type isolation axis corresponds to the edge of the 深-type deep well zone. The sound is placed in the Ν-type deep well zone. The doping concentration of the 隔离-type isolation ring = the doping concentration of the deep well zone. The type drift region is disposed in the above-mentioned semiconductor element package _ under the i 訾 isolation structure of the present invention. The lightly doped region, in the flight example, wherein the semiconductor element further comprises n~, °° disposed between the gate structure and the first N-type doped region. 201019476 ------008-0241 29029twf.doc/n In the embodiment of the present invention, the semiconductor component further includes p disposed in the P-type well region, wherein the p-type guard ring has a doping concentration greater than P Doping concentration of the well zone. In the embodiment of the invention, the upper semiconductor element further comprises a second isolation structure disposed between the P-type base ship and the sluice area. The N-type isolation ring is, for example, located below the second isolation structure.
㈣ί本發明之—實施例中，上述之半導體元件更包括Ρ i摻雜區，配胁Ρ縣體區巾且與第—Ν㈣雜區相鄰。 ，本發明之—實施例中，上述型隔離環的摻 類為磷或石申。 1本發明另提出—種積體電路晶片，其包括基底、CMOS =_二及LDNMOS元件。基底包括分開配置的第一區與 ^區:CMOS元件位於第—區’且包括配置於基底中的 里井區、配置於N型井區以外的基底上的NM〇s電晶體 及配置於N型井區的基底上的PMOS電晶體。LDNMOS 元件位於第一區，LDNMOS元件包括]ST型深井區、p型井 區、閘極結構、P型基體區、第一 N型摻雜區、第二>^型 摻雜區、第一隔離結構以及N型隔離環。N型深井區位於 基底中。P型井區位於N型深井區之外圍。閘極結構配置 於N型深井區的基底上。P型基體區配置於N型深井區 中，且位於閘極結構之一侧。第一 N型摻雜區配置於p型 土體區中。第—N型摻雜區配置於N型深井區中，且位於 閘極結構之另一側。第一隔離結構配置於閘極結構與第二 N型推雜區之間。N型隔離環以對應n型深井區之邊緣的 201019476 一〜一 J〇8-〇241 29029twf.doc/n '而配置於N a井區巾，其巾N型隔離環的摻雜濃度 大於N型深井區的摻雜濃度。 f本發明之一實施例中，上述之N型隔離環的摻質種 gg I雜浪度及摻雜深度實質上會與N型井區的摻質種 類、摻雜濃度及摻雜深度相同。 紅在本發明之—實施例巾，上叙LDNMOS元件更包 的換區’配置於第—隔離結構之下方。_隔離環 移區二^、摻雜濃度及摻雜深度例如是實質上與Ν型漂 的推質種類、摻雜濃度及摻雜深度相同。 ，本㈣之—實施例巾上叙[。醒⑽元件更包 ，^摻雜區’配置於閘極結構與第—ν型摻雜區之間。 括ρ刑f明之—實施例巾，上述之LDNM0S元件更包 例如是型防護環的摻_(4) In the embodiment of the invention, the semiconductor element further comprises a Ρi-doped region, which is associated with the body region of the Ρ 且 and adjacent to the first (four) hetero region. In the embodiment of the present invention, the above-mentioned type of isolation ring is doped with phosphorus or stone. 1 The present invention further provides an integrated circuit chip including a substrate, a CMOS = NAND and an LDNMOS device. The substrate includes a first region and a region that are separately disposed: the CMOS device is located at the first region and includes a well region disposed in the substrate, an NM〇s transistor disposed on a substrate other than the N-well region, and configured in the N A PMOS transistor on the substrate of the well region. The LDNMOS device is located in the first region, and the LDNMOS device includes an ST type deep well region, a p-type well region, a gate structure, a P-type base region, a first N-type doped region, a second type, a ^-type doped region, and a first Isolation structure and N-type isolation ring. The N-type deep well zone is located in the basement. The P-type well area is located on the periphery of the N-type deep well area. The gate structure is disposed on the base of the N-type deep well area. The P-type base region is disposed in the N-type deep well region and is located on one side of the gate structure. The first N-type doped region is disposed in the p-type soil region. The first-N-type doped region is disposed in the N-type deep well region and is located on the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type dummy region. The N-type isolating ring is disposed in the N a well area towel with the 201019476 one to one J〇8-〇241 29029twf.doc/n ' corresponding to the edge of the n-type deep well area, and the doping concentration of the N-type isolating ring of the towel is greater than N The doping concentration of the deep well zone. In an embodiment of the present invention, the dopant species gg I and the doping depth of the N-type isolation ring are substantially the same as the dopant species, doping concentration, and doping depth of the N-type well region. Red is in the embodiment of the present invention, and the replacement region of the LDNMOS device is disposed below the first isolation structure. The spacer ring, the doping concentration, and the doping depth are, for example, substantially the same as the push type, doping concentration, and doping depth of the Ν type drift. , (4) - the embodiment of the towel on the [. The awake (10) component is further packaged, and the doped region is disposed between the gate structure and the ν-type doped region. Including the prance of the prance - the embodiment of the towel, the above-mentioned LDNM0S component is more packaged, for example, the type of protective ring
括第細种，上叙圓聰元件更包 型隔離環例:是位:型井區之間。N 括Ρ ΐίΐΖ之㈣實施例中，上述之LDNM〇S元件更包 相鄰 。•換雜區’配置於P型基體區巾且與第-N型摻雜區 類為磷或坤。冑_'丨中’上述之N型隔離環的摻質種 本發明之半導 摻雜漢度較高的 ^ ^深·的_邊緣設置 1⑹離％，稭由N型隔離環環繞於元件 JU8-0241 29029twf.doc/n 201019476 的四周，因此可有效阻隔橫向的漏電流路徑，增進高壓侧 能力（high side ability)以提升元件效能。 d a ^外-^發明之積體電路晶片在形成1^型漂移區或N 聖井區的同時形成N型隔離環，因此製程簡單 有的CDMQS製程相整合’且能夠朗在所有的電源管理 晶片上。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 ❿ 參 舉較佳實施例’並配合所附圖式，作詳細說明如下。 【實施方式】 圖1疋賊本發明之-實施狀半導體元件的電路 :詳的ί主:了:述之實施例將以兩個元件為例來 、、要疋為了使热習此項技術者能夠據以實 :旦旦、非用以限定本發明之範圍，本發明並不對元件的 數篁及排列方式做特別的限制。 請參照圖1 ’元件102與元件104例如分別是 閘電壓VG1於元件102的閘極及 =加閘極電壓VG2於元件⑽關極，可賤 2 與元件104於摔ό @ 古雷偏作夺各自獨 牛2的沒極會麵接至 :^端電源電〜元件1〇4的源極會輕接 杜是接地電壓Vss。元件102的源極會與元 區域10=極，接。由於元件102的源極端並不會接地(如 ^由且會被施加高電位，因此本發明之實施例 、:路和土，Γ置核繞在元件外圍的隔離環，以阻隔漏電 在—實施例中，隔離環是利用摻雜製程在深井區 20101947_6_4129— 中形成濃度較高的環狀結構以環繞在元件的四周。如此一 來，本發明之實施例可以增進高壓側能力（high side ability) ’亦即減少擊穿(punch_thr〇ugh)效應造成漏電到基 底的情況’進而達到提升元件效能之功效。Including the finest species, the above-mentioned rounded Cong components are more inclusive isolation rings: Yes: between wells. In the embodiment of the fourth embodiment, the above-mentioned LDNM〇S elements are further adjacent to each other. • The swap region is disposed in the P-type base region and is in the form of phosphorus or nucleus with the first-N type doping region.掺 丨 丨 丨 ' ' 上述 ' 上述 上述 上述 ' ' ' ' ' ' ' 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本-0241 29029twf.doc/n The perimeter of 201019476 can effectively block the lateral leakage current path and improve the high side ability to improve component performance. Da ^ 外-^Invented integrated circuit chip forms an N-type isolation ring while forming a 1^ type drift region or N holy well region, so the simple CDMQS process is integrated and can be applied to all power management chips. on. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 1 is a circuit of an embodiment of a semiconductor device of the present invention: a detailed description of the invention: The embodiment will be described by taking two components as an example, and in order to make the person skilled in the art The present invention is not intended to limit the scope of the invention, and the invention does not particularly limit the number and arrangement of elements. Referring to FIG. 1 'the element 102 and the element 104 are respectively, for example, the gate voltage VG1 is at the gate of the element 102 and the gate voltage VG2 is turned off at the element (10), and the 贱2 and the element 104 are wrestled. The immersive meeting of each of the single cows 2 is connected to: ^ terminal power supply ~ the source of the component 1 〇 4 will be lightly connected to the ground voltage Vss. The source of element 102 will be connected to the source region 10 = pole. Since the source terminal of the component 102 is not grounded (eg, and a high potential is applied, embodiments of the present invention, the road and the earth, the core is wound around the isolation ring around the component to block leakage) In the example, the isolation ring is formed by a doping process in the deep well region 20101947_6_4129 to form a higher concentration annular structure to surround the periphery of the component. Thus, the embodiment of the present invention can enhance the high side ability. 'That is to reduce the breakdown of the (punch_thr〇ugh) effect caused by leakage to the substrate' and thus improve the efficiency of the component.
接下來，進一步以上視圖及剖面圖的方式說明本發明 之實施例。圖2A是依照本發明之一實施例之半導體元件 的上視示意圖。圖2B是沿著圖2A中I-Ι線段的剖面示意 圖。圖3A是依照本發明之另一實施例之半導體元件的上 視示意圖。圖3B是沿著圖3A中Ι，-Γ線段的剖面示意圖。 在圖3Α與圖3Β中，和圖2Α與圖2Β相同的構件則使用 相同的標號並省略其說明。 請參照圖2A與圖2B，本發明之半導體元件例如是 LDNMOS 元件 10、20。LDNMOS 元件 10 與 LDNMOS 元 件20例如是分開配置於p型的基底2〇〇上。基底2〇〇中 配置有N型深井區202與P型井區(p_WELL)203。 N型深井區202例如是高壓N型深井區(JJVDNW)。 在一實施例中，N型深井區202所植入的摻質為磷，所使 用的植入能量約為120〇keV-2400 keV’且其摻雜濃度約為 /cm2-1013 /cm2。形成N型深井區2〇2的植入能量例如 是約為1800keV，且其摻雜濃度例如是約為1〇12/cm2。 P型井區203位於N型深井區202的外圍。在一實施 例中，如圖2A與圖2B所示，P型井區2〇3鄰接於N型深 井區202的外圍。在另一實施例中，如圖3A與圖3B所示， P型井區203,與N型深井區202之間具有間隔3⑻，而環 2〇1〇19476_412_w_ 繞在N型深井區202的外圍。在一實施例中，p型井區2〇3 所植入的摻質為硼，所使用的植入能量約為12〇 keV 24〇 keV ’且其摻雜濃度約為1.5xl012 /cm2-1.5xl014/cm2。形成 P型井區203的植入能量例如是約為18〇keV，且其摻雜濃 度例如是約為1.5xl〇13/cm2。 LDNMOS元件10包括閘極結構2〇4a、第一 N型摻雜 區206a、第二N型摻雜區208、P型摻雜區21〇a及P型基 ❹ 體區(p-body)212a〇LDNMOS元件20包括閘極結構204b、 第一 N型摻雜區206b、第二N型摻雜區208、P型摻雜區 210b及P型基體區212b。 更具體地說，P型基體區212a、212b分別位於N型 深井區202中。在一實施例中，p型基體區212a、2121)所 植入的摻質為硼。 第一 N型摻雜區206a、2〇6b例如是N+摻雜區，其分 別位於P型基體區212a、212b中，以作為LDNMOS元件 10、20的源極區。在一實施例中，第一 N型摻雜區2〇如、 ❿ 2〇6b所植入的摻質為磷。 第一 N型摻雜區208例如是N+摻雜區，其位於N型 深井區202中’並配置於兩P型基體區212a、212b之間。 第二N型摻雜區208是作為LDNM〇s元件10、2〇的共同 汲極區。在一實施例中，第二N型摻雜區2〇8所植入的摻 質為麟·。 P型摻雜區210a、210b例如是P+摻雜區，其分別位 於P型基體區212a、212b _，且與該第一 N型摻雜區 11 JU8-0241 29029twf.doc/n 201019476 206a、206b相鄰。在一實施例中，p型摻雜區21〇a、21〇b 所植入的摻質為硼。 閘極結構204a位於第二n型摻雜區208與第一 N型 摻雜區206a之間的N型深井區202上。閘極結構204a包 括閘極214a、閘介電層216a以及間隙壁218a。閘介電層 216a配置於閘極214a與基底200之間，間隙壁218a配置 於閘極214a與閘介電層216a的侧壁上。閘極結構204b • 位於第二N型摻雜區208與第一 N型摻雜區206b之間的 N型深井區202上。閘極結構204b包括閘極214b、閘介 電層216b以及間隙壁218b。閘介電層216b配置於閘極 214b與基底200之間，間隙壁218b配置於閘極214b與閘 介電層216b的侧壁上。在一實施例中，閘極結構2〇4a、 204b會分別延伸至部分的p型基體區212a、212b上方， 亦即閘極結構204a、204b下方與P型基體區212a、212b 耦合的區域會構成通道區220。 此外，LDNMOS元件10、20彼此可以電性連接，其 參 例如是藉由延伸部214c將閘極214a、214b的末端連接在 一起，而形成兩指狀的結構，如圖2A所示。當然，在其 他實施例中，當具有多個LDNMOS元件時，各LDNMOS 的閘極亦可以彼此電性連接，而形成多指狀結構。 請繼續參照圖2A與圖2B，LDNMOS元件1〇還包括 N型輕換雜區222a、N型漂移區(N-drift)224a與隔離结構 226a、228a’LDNMOS元件20還包括N型輕捧雜區222b、 N型漂移區224b與隔離結構226b、228b。 12 201019476 08-0241 29029twidoc/n N型輕摻雜區222a、222b分別配置於p型基體區 212a、212b中’而位於閘極結構2〇4a、2〇仆的一側與第 一 N型摻雜區206a、206b電性連接，以防止熱載子^應 的發生N型輕摻雜區222a例如是位於閘極結構2〇4a與 第一 N型摻雜區206a之間，N型輕摻雜區222b例如是；|立 於閘極結構204b與第一 N型摻雜區206b之間。 隔離結構226a位於閘極結構2〇4a與第二>^型摻雜區 φ 208之間，隔離結構226b位於閘極結構204b與第二N型 摻雜區20+8之間。在一實施例中，部分閘極214a 2Mb 還分別覆蓋在隔離結構226a、226b上。隔離結構226a、 226b例如是場氧化層(F〇x)結構或淺溝渠隔離(sti)結構。 N型漂移區224a、224b配置於n型深井區202中， 且分別環繞於至少部分隔離結構226a、226b的周圍，並與 ，一 N型摻雜區208電性連接。在一實施例中，N型漂移 區224a、224b所植入的摻質為神，且形成N型漂移區 224a、224b的能量約為100 keV_2⑻keV，其摻雜濃度約 ❹ 為 5x10 /cm2_1〇13/cm2。形成 N 型漂移區 224a、224b 的 植入能量例如是約為150 keV，且其摻雜濃度例如是約為 4><1〇12 /cm2。 隔離結構228a位於P型基體區212a與P型井區203 之間’隔離結構228b位於P型基體區212b與p型井區2〇3 之間。也就是說，LDNMOS元件1〇例如是形成在隔離結 構226a與隔離結構228a所定義出的區域内，而LDNM〇s 兀件20例如是形成在隔離結構226b與隔離結構228b所定 13 -------UU8-0241 29029twf.doc/n 義出的區域内。隔離結構228a、228b例如是場氧化層結構 或淺溝渠隔離結構。 θ'° 此外，本發明之半導體元件還可以包括Ρ型防護環 (guard ring)230 ’其配置於Ρ型井區203中。ρ型防護環23〇 例如是p+摻雜區，其是以對應N型深井區2〇2之 方式而配置於P型井區2G3中，以防止雜訊傳遞韻到周 圍的其他元件陣列。P型防護環23〇的摻雜濃度大於p型 井區的摻雜濃度。在一實施例中，ρ型防護環23〇所 植入，摻質為硼。P型防護環23〇與ρ型摻雜區21〇a之間 例如疋疋利用隔離結構228a作隔絕，而ρ型防護環230 與P型摻雜區210b之間例如是利用隔離結構228b作隔絕。 值得注意的是，如圖2A與圖2B所示，在本發明之半 導體元件還包括N型隔離環(is〇iati〇n ring)232，其配置於 N型深井區202中。N型隔離環232是以對應]^型深井區 2〇2之邊緣的方式而配置型深井區2〇2中。在一實施 例中，N型隔離環232可以是配置於隔離結構228&、22肋 ❹ 的下方。 N型隔離環232的摻雜濃度大於]^型深井區2〇2的摻 雜濃度N型隔離環232所植入的掺質可以是磷或神。在 實鈿例中，當N型隔離環232所植入的摻質為磷時，形 f N型隔離環232的能量約為150 keV-270 keV，其摻雜 辰度約為1G!2 /em2_1()14 “2 ;例如是使用植人能量約為 = 0keV及摻雜濃度約為Mxl〇13/cm2。在另一實施例中， 田N型隔離環232所植入的摻質為坤時，形成n型隔離環 14 JO8-0241 29029twf.doc/n 201019476 232的能量約為1〇〇keV_2〇〇keV，其摻雜濃度約為5χ1〇11 /cm -10 3 /cm2 ;例如是使用植入能量約為i5〇 kev及摻雜 浪度約為4xl〇12/cm2。 由於在N型深井區202中的最外圍配置有N型隔離 環232以環繞LDNMOS元件1〇、2〇的四周，且N型隔離 環232的摻雜濃度大於N型深井區202的摻雜濃度，因此 N型隔離環232可以有效地阻隔橫向的漏電流路徑，防止 電流由P型基體區212a、212b洩漏到基底200中，進而增 進高壓側能力並提升元件效能。 特別說明的是，由於上述實施例之LDNMOS元件的 製程可以與CMOS元件的製程相整合而達到簡化製程步 驟的功效，因此在以下實施例中將同時以配置於基底上的 CMOS元件與LDNMOS元件來對本發明之積體電路晶片 作說明。圖4是依照本發明之一實施例之積體電路晶片的 剖面示意圖。 請參照圖4，本發明之積體電路晶片至少包含CM〇s 參 元件與元件。為方便說明，僅以一個CMOS元 件406與一個LDNMOS元件408配置於p型的基底400 上來說明之。然而，本發明並不以此為限。CM〇s元件4〇6 配置於基底400的第一區402，LDNMOS元件408配置於 基底400的第二區404，其中第一區402與第二區404為 分開配置。 CMOS元件406包括N型井區410、NMOS電晶體412 與PMOS電晶體414。N型井區410配置於基底400中。 15 U08-0241 29029twf.doc/n 201019476 NMOS電晶體412，配置於N型井區410以外的基底400 上。PMOS電晶體414 ’配置於N型井區410的基底400 上。NMOS電晶體412與PMOS電晶體414之間例如是藉 由隔離結構420隔絕。在一實施例中，NMOS電晶體412 與PMOS電晶體414各包括位於基底400上的閘極結構 416與位於閘極結構416兩側基底400中的摻雜區418。閘 極結構416包括閘極416a、閘介電層416b及間隙壁416c， 0 其中閘介電層416b配置於閘極416a與基底400之間，間 隙壁416c配置於閘極416a與閘介電層416b的侧壁上。 LDNMOS元件408例如是如圖2B所繪示之LDNMOS 元件，其至少包括N型深井區422、P型井區424、閘極結 構426、P型基體區428、第一 N型摻雜區430、第二N型 摻雜區432、隔離結構434、N型隔離環436。N型深井區 422與P型井區424位於基底400中，且p型井區424位 於N型深井區422之外圍。閘極結構426配置於N型深井 區422的基底400上。P型基體區428配置於N型深井區 β 422中，且位於閘極結構426之一側。第一 Ν型摻雜區430 配置於Ρ型基體區428中。第二ν型摻雜區432配置於Ν 型深井區422中，且位於閘極結構426之另一侧。隔離結 構434配置於閘極結構426與第二Ν型摻雜區432之間。 Ν型隔離環436以對應Ν型深井區422之邊緣的方式而配 置於Ν型深井區422中，其中Ν型隔離環436的摻雜濃度 大於Ν型深井區422的摻雜濃度。 在一實施例中，LDNMOS元件408還可以包括Ν型 201019476 —-008-0241 29029twf.doc/n 漂移區438、N型輕摻雜區440 ' p型防護環442、p型摻 雜區444以及隔離結構446。N型漂移區438配置於隔離 結構434之下方。N型輕摻雜區440配置於閘極結構426 ，第一 N型摻雜區430之間。p型防護環442以對應1^型 沬井區422之邊緣的方式而配置於p型井區424中，其中 P型防護環442的摻雜濃度大於P型井區424的摻雜濃度。 隔離結構446配置於p型基體區428與該p型井區 φ 間，且N型隔離環436例如是位於隔離結構446之下方。 p型摻雜區444配置於P型基體區428中，且與第—N 摻雜區430相鄰。 特別說明的是，如圖4所示，N型隔離環436例如是 與N型漂移區438在同一個製程步驟中同時形成，也就是 說N型隔離環436的摻質種類、摻雜濃度及摻雜深度實質 上會與N型漂移區438的摻質種類、摻雜濃度及摻雜深产 相同。在一實施例中，1^型隔離環436 與N型漂移區4= 所植入的摻質為砷，且形成N型隔離環436與N型浮 ❹的能量約為廳V-2〇〇keV，其摻雜濃度約為㈣二 /Cm -1013 /Cm2。形成N型隔離環436與N型漂移區438的 ，入，量例如是約為15G keV，且其摻雜濃度例如是 4χ1〇 2 /cm2。 圖5是依照本發明之另一實施例之積體電路晶片 ，不意圖。在圖5中，與圖4相同的構件則使用相同 請參照圖5，組成積體電路晶片的主要構件與組成圖 17 201019476 ju8-0241 29029twf.doc/n 4所示之積體電路晶片的主要構件大致相同，然而兩者之 間的差異主要是在於N型隔離環436’所植入的摻質種類、 掺雜濃度及摻雜深度。N型隔離環436,例如是與N型井區 410在同一個製程步驟中同時形成，也就是說N塑隔離環 436的摻質種類、摻雜濃度及摻雜深度實質上會與N型井 區410的摻質種類、摻雜濃度及摻雜深度相同。在另一實 施例中’N型隔離環436’與N型井區410所植入的摻質為 鱗，且形成N型隔離環436’與:N型井區410的能量約為 ❿ 150 keV-270 keV ’ 其接雜濃度約為 1〇12/CIn2_iQi4/cm2。形 成N型隔離環436’與N型井區410的植入能量例如是約為 210keV，且其摻雜濃度例如是約為丨4xl〇i3/cm2。 在圖4與圖5中，藉由在N型深井區422中的最外圍 配置摻雜濃度較大的N型隔離環436、436,以環繞 LDNMOS元件408的四周’可以有效地防止由p型基體區 428洩漏到基底400漏電流。此外，N型隔離環436、436, 可與現有的CDMOS製程整合，僅需藉由植入罩幕的形成 φ 以及離子植入製程的施行即可形成之。 β為證實本發明之半導體元件及積體電路晶片確實能 夠提升元件效能，接下來將以實驗例說明其特性。以下實 驗例之說明僅是用來說明配置Ν型隔離環對於漏電流的影 響，但並非用以限定本發明之範圍。 實驗例 圖6為根據本發明之_實驗例之閘極電壓(^)與基底 18 ϋ〇8-0241 29029twf.doc/n 201019476 電流(Isub)的關係曲線圖。 在此實驗例中’在0.35微米3.3/5/40伏特之CDM〇s 製程中，以及在P型基體區到N型深井區邊緣的距離為51 μπι的情況下(Ε = 5.1 μιη)，以相同型井區的形成條件 在LDNMOS的源極與Ρ型基底間植入Ν型隔離環。如圖 6所示，在未佈值Ν型隔離環的LDNM0S會在閘極電壓 約9.5伏特時產生崩潰，造成基底漏電流迅速增加並致使 LDNMOS作用失效。另一條曲線顯示經過N型隔離環佈 值後的關係圖，LDNMOS可以承受閘極電壓超過％伏特 仍未有崩潰現象，整體的基底漏電流也能維持在平穩的極 低電流值，保持LDNMOS的操作穩定性。 〜 综上所述，本發明之半導體元件及積體電路晶片藉由 在N型深井區的内側邊緣設置隔離環，且ν型^離 環的摻雜濃度大於N魏井區的摻雜濃度。由於 繞於兀件的四周，因此可有效阻隔漏電流路徑，以辩 進高壓侧能力並提升元件效能。 θ 本發明之半導體元件及積體電路晶片可以應用 在=有電源管理之半導體元件上，且可賤過光罩圖案的 改變而與财的CDM()S製練合，製程簡單且可以避免 晶片面積不必要的浪費。 ΡΓΐί發明已以較佳實施例揭露如上，然、其並非用以 限疋本發明’任何賴技術領域巾具有通常知識者，在不 申和範圍内，當可作些許之更動與潤飾， 本發月之保護範圍當視後附之申請專利範圍所界定者 2010刚76_24129__ 為準。 【圖式簡單說明】 圖1是依照本發明之一實施例之半導體元件的電路 圖。 圖2A是依照本發明之一實施例之半導體元件的上視 示意圖。 圖2B是沿著圖2A中I-Ι線段的剖面示意圖。 圖3A是依照本發明之另一實施例之半導體元件的上 ® 視示意圖。 圖3B是沿著圖3A中Γ-Γ線段的剖面示意圖。 圖4是依照本發明之一實施例之積體電路晶片的剖面 示意圖。 圖5是依照本發明之另一實施例之積體電路晶片的剖 面示意圖。 圖6為根據本發明之一實驗例之閘極電壓(Vgs)與基底 電流(ISUb)的關係曲線圖。 φ 【主要元件符號說明】 10、20、408 : LDNMOS 元件 102、104 :元件 106 :區域 200、400 :基底 202、 422 : N型深井區 203、 203’、424 : P 型井區 204a、204b、416、426 :閘極結構 20 U08-0241 29029twf.doc/n 201019476 206a、206b、430 :第一 N 型摻雜區 208、432 :第二N型摻雜區 210a、210b、444 : P 型摻雜區 212a、212b、428 : P 型基體區 214a、214b、416a :閘極 216a、216b、416b :閘介電層 218a、218b、416c :間隙壁 214c :延伸部 ® 220 :通道區 222a、222b、440 : N型輕摻雜區 224a、224b、438 : N 型漂移區 226a、228a、226b、228b、420、434、446 :隔離結 構 230、442 : P型防護環 232、436、436’ ： N 型隔離環 300 :間隔 參 402 :第一區 404 :第二區 406 : CMOS 元件 410 : N型井區 412 : NMOS電晶體 414:PMOS電晶體 418 :摻雜區 21Next, embodiments of the present invention will be described in further aspects and cross-sectional views. Fig. 2A is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view along the line I-Ι in Fig. 2A. Fig. 3A is a schematic top view of a semiconductor device in accordance with another embodiment of the present invention. Figure 3B is a cross-sectional view along line Ι, -Γ of Figure 3A. In Figs. 3A and 3B, the same members as those in Fig. 2A and Fig. 2A are denoted by the same reference numerals and the description thereof will be omitted. Referring to Figures 2A and 2B, the semiconductor device of the present invention is, for example, LDNMOS devices 10, 20. The LDNMOS element 10 and the LDNMOS element 20 are, for example, disposed separately from the p-type substrate 2A. An N-type deep well region 202 and a P-type well region (p_WELL) 203 are disposed in the substrate 2〇〇. The N-type deep well area 202 is, for example, a high pressure N-type deep well area (JJVDNW). In one embodiment, the N-type deep well region 202 is implanted with phosphorus having an implantation energy of about 120 〇 keV to 2400 keV' and a doping concentration of about /cm 2-1 13 /cm 2 . The implantation energy for forming the N-type deep well region 2 〇 2 is, for example, about 1800 keV, and its doping concentration is, for example, about 1 〇 12 / cm 2 . The P-type well region 203 is located at the periphery of the N-type deep well region 202. In one embodiment, as shown in Figures 2A and 2B, the P-type well region 2〇3 is adjacent to the periphery of the N-type deep well region 202. In another embodiment, as shown in FIGS. 3A and 3B, the P-type well region 203 has a spacing 3 (8) from the N-type deep well region 202, and the ring 2〇1〇19476_412_w_ is wound around the periphery of the N-type deep well region 202. . In one embodiment, the dopant implanted in the p-type well region 2〇3 is boron, and the implantation energy used is about 12 〇 keV 24 〇 keV 'and its doping concentration is about 1.5 x l 012 / cm 2 - 1.5 Xl014/cm2. The implantation energy for forming the P-type well region 203 is, for example, about 18 〇 keV, and its doping concentration is, for example, about 1.5 x 13 〇 13 / cm 2 . The LDNMOS device 10 includes a gate structure 2〇4a, a first N-type doping region 206a, a second N-type doping region 208, a P-type doping region 21〇a, and a P-type body region (p-body) 212a. The NMOS NMOS device 20 includes a gate structure 204b, a first N-type doping region 206b, a second N-type doping region 208, a P-type doping region 210b, and a P-type body region 212b. More specifically, the P-type base regions 212a, 212b are respectively located in the N-type deep well region 202. In one embodiment, the p-type matrix regions 212a, 2121) are implanted with boron. The first N-type doped regions 206a, 2〇6b are, for example, N+ doped regions which are respectively located in the P-type body regions 212a, 212b as the source regions of the LDNMOS devices 10, 20. In one embodiment, the dopant implanted in the first N-type doped region 2, for example, ❿ 2〇6b is phosphorus. The first N-type doped region 208 is, for example, an N+ doped region located in the N-type deep well region 202 and disposed between the two P-type base regions 212a, 212b. The second N-type doped region 208 is a common drain region of the LDNM〇s elements 10, 2〇. In one embodiment, the dopant implanted in the second N-type doped region 2〇8 is lin. The P-type doped regions 210a, 210b are, for example, P+ doped regions located in the P-type body regions 212a, 212b_, respectively, and with the first N-type doped regions 11 JU8-0241 29029twf.doc/n 201019476 206a, 206b Adjacent. In one embodiment, the dopant implanted in the p-doped regions 21a, 21b is boron. The gate structure 204a is located on the N-type deep well region 202 between the second n-type doped region 208 and the first N-type doped region 206a. The gate structure 204a includes a gate 214a, a gate dielectric layer 216a, and a spacer 218a. The gate dielectric layer 216a is disposed between the gate 214a and the substrate 200, and the spacer 218a is disposed on the sidewalls of the gate 214a and the gate dielectric layer 216a. The gate structure 204b is located on the N-type deep well region 202 between the second N-type doped region 208 and the first N-type doped region 206b. The gate structure 204b includes a gate 214b, a gate dielectric layer 216b, and a spacer 218b. The gate dielectric layer 216b is disposed between the gate 214b and the substrate 200, and the spacer 218b is disposed on the sidewalls of the gate 214b and the gate dielectric layer 216b. In one embodiment, the gate structures 2A, 4b, 204b extend over portions of the p-type body regions 212a, 212b, respectively, that is, regions of the gate structures 204a, 204b that are coupled to the P-type body regions 212a, 212b. The channel area 220 is formed. Further, the LDNMOS elements 10, 20 may be electrically connected to each other, for example, by connecting the ends of the gates 214a, 214b together by the extending portion 214c to form a two-finger structure as shown in Fig. 2A. Of course, in other embodiments, when there are a plurality of LDNMOS elements, the gates of the respective LDNMOSs may also be electrically connected to each other to form a multi-finger structure. 2A and 2B, the LDNMOS device 1A further includes an N-type light-changing region 222a, an N-type drift region (N-drift) 224a, and an isolation structure 226a, 228a. The LDNMOS device 20 further includes an N-type light-weight A region 222b, an N-type drift region 224b, and isolation structures 226b, 228b. 12 201019476 08-0241 29029twidoc/n N-type lightly doped regions 222a, 222b are respectively disposed in the p-type base regions 212a, 212b' and are located on the side of the gate structure 2〇4a, 2 servant and the first N-type doping The miscellaneous regions 206a, 206b are electrically connected to prevent the occurrence of hot carriers. The N-type lightly doped region 222a is, for example, located between the gate structure 2〇4a and the first N-type doped region 206a, and the N-type light doping The impurity region 222b is, for example, positioned between the gate structure 204b and the first N-type doping region 206b. The isolation structure 226a is between the gate structure 2〇4a and the second >-type doped region φ208, and the isolation structure 226b is between the gate structure 204b and the second N-type doped region 20+8. In one embodiment, portions of gates 214a 2Mb are also overlying isolation structures 226a, 226b, respectively. The isolation structures 226a, 226b are, for example, field oxide (F〇x) structures or shallow trench isolation (sti) structures. N-type drift regions 224a, 224b are disposed in n-type deep well region 202 and surround respective at least portions of isolation structures 226a, 226b and are electrically coupled to an N-type doped region 208. In one embodiment, the dopants implanted in the N-type drift regions 224a, 224b are gods, and the energy forming the N-type drift regions 224a, 224b is about 100 keV_2 (8) keV, and the doping concentration is about 5x10 / cm2_1 〇 13 /cm2. The implantation energy for forming the N-type drift regions 224a, 224b is, for example, about 150 keV, and its doping concentration is, for example, about 4 > 1 〇 12 /cm 2 . The isolation structure 228a is located between the P-type base region 212a and the P-type well region 203. The isolation structure 228b is located between the P-type base region 212b and the p-type well region 2〇3. That is, the LDNMOS device 1 is formed, for example, in a region defined by the isolation structure 226a and the isolation structure 228a, and the LDNM〇s device 20 is formed, for example, in the isolation structure 226b and the isolation structure 228b. ---UU8-0241 29029twf.doc/n Within the meaning of the area. The isolation structures 228a, 228b are, for example, field oxide layer structures or shallow trench isolation structures. θ'° Further, the semiconductor element of the present invention may further include a guard ring 230' disposed in the crucible well region 203. The p-type guard ring 23 is, for example, a p+ doped region which is disposed in the P-type well region 2G3 in a manner corresponding to the N-type deep well region 2〇2 to prevent noise transmission to the surrounding other element array. The doping concentration of the P-type guard ring 23〇 is greater than the doping concentration of the p-type well region. In one embodiment, the p-type guard ring 23 is implanted and the dopant is boron. Between the P-type guard ring 23〇 and the p-type doped region 21〇a, for example, the isolation structure 228a is isolated, and the p-type guard ring 230 and the P-type doped region 210b are separated from each other by, for example, the isolation structure 228b. . It is to be noted that, as shown in Figs. 2A and 2B, the semiconductor component of the present invention further includes an N-type isolation ring 232 disposed in the N-type deep well region 202. The N-type isolating ring 232 is disposed in the deep well region 2〇2 in a manner corresponding to the edge of the deep well region 2〇2. In one embodiment, the N-type isolation ring 232 can be disposed below the isolation structures 228 & 22 ribs. The doping concentration of the N-type isolating ring 232 is greater than the doping concentration of the deep well region 2〇2. The dopant implanted in the N-type isolating ring 232 may be phosphorus or god. In the example, when the dopant implanted in the N-type isolation ring 232 is phosphorus, the energy of the f-type isolation ring 232 is about 150 keV-270 keV, and the doping degree is about 1 G! 2 / Em2_1()14 "2; for example, using implant energy of about = 0 keV and doping concentration of about Mxl 〇 13 / cm 2 . In another embodiment, the implant of the N-type spacer ring 232 is Kun. When the n-type isolation ring 14 is formed, JO8-0241 29029twf.doc/n 201019476 232 has an energy of about 1 〇〇 keV 2 〇〇 keV and a doping concentration of about 5 χ 1 〇 11 /cm -10 3 /cm 2 ; for example, The implantation energy is about i5〇kev and the doping wave is about 4xl〇12/cm2. Since the outermost periphery of the N-type deep well region 202 is provided with an N-type isolation ring 232 to surround the periphery of the LDNMOS element 1〇, 2〇 The doping concentration of the N-type isolation ring 232 is greater than the doping concentration of the N-type deep well region 202. Therefore, the N-type isolation ring 232 can effectively block the lateral leakage current path and prevent current from leaking from the P-type base regions 212a, 212b. In the substrate 200, the high-voltage side capability is further enhanced and the device performance is improved. In particular, since the process of the LDNMOS device of the above embodiment can be combined with the CMOS element The process is integrated to achieve the simplification of the process steps. Therefore, in the following embodiments, the integrated circuit wafer of the present invention will be described simultaneously with the CMOS device and the LDNMOS device disposed on the substrate. FIG. 4 is a view of the present invention. A schematic cross-sectional view of an integrated circuit wafer of an embodiment. Referring to Figure 4, the integrated circuit wafer of the present invention includes at least CM 〇 参 元件 elements and elements. For convenience of explanation, only one CMOS element 406 and one LD NMOS element 408 are disposed. The p-type substrate 400 is illustrated. However, the invention is not limited thereto. The CM 〇 s element 4 〇 6 is disposed in the first region 402 of the substrate 400, and the LD NMOS device 408 is disposed in the second region 404 of the substrate 400. The first region 402 and the second region 404 are separately disposed. The CMOS device 406 includes an N-type well region 410, an NMOS transistor 412, and a PMOS transistor 414. The N-type well region 410 is disposed in the substrate 400. 15 U08-0241 29029twf Doc/n 201019476 NMOS transistor 412 is disposed on substrate 400 other than N-type well region 410. PMOS transistor 414' is disposed on substrate 400 of N-type well region 410. NMOS transistor 412 and PMOS transistor 414 For example, Isolated by the isolation structure 420. In one embodiment, NMOS transistor 412 and PMOS transistor 414 comprises a gate structure 416 each located on both sides of the gate structure 416 in the substrate 400 doped regions 418 on the substrate 400 is located. The gate structure 416 includes a gate 416a, a gate dielectric layer 416b, and a spacer 416c, wherein the gate dielectric layer 416b is disposed between the gate 416a and the substrate 400, and the spacer 416c is disposed on the gate 416a and the gate dielectric layer. On the side wall of 416b. The LDNMOS device 408 is, for example, an LDNMOS device as shown in FIG. 2B, and includes at least an N-type deep well region 422, a P-type well region 424, a gate structure 426, a P-type base region 428, and a first N-type doped region 430. A second N-type doped region 432, an isolation structure 434, and an N-type isolation ring 436. The N-type deep well zone 422 and the P-type well zone 424 are located in the substrate 400, and the p-type well zone 424 is located outside the N-type deep well zone 422. The gate structure 426 is disposed on the substrate 400 of the N-type deep well region 422. The P-type base region 428 is disposed in the N-type deep well region β 422 and is located on one side of the gate structure 426. The first erbium type doped region 430 is disposed in the 基 type substrate region 428. The second v-type doped region 432 is disposed in the Ν-type deep well region 422 and on the other side of the gate structure 426. The isolation structure 434 is disposed between the gate structure 426 and the second germanium doped region 432. The 隔离-type isolating ring 436 is disposed in the 深-type deep well region 422 in a manner corresponding to the edge of the Ν-type deep well region 422, wherein the doping concentration of the Ν-type isolating ring 436 is greater than the doping concentration of the Ν-type deep well region 422. In an embodiment, the LDNMOS device 408 may further include a 2010-type 201019476--008-0241 29029 twf.doc/n drift region 438, an N-type lightly doped region 440 'p-type guard ring 442, a p-type doped region 444, and Isolation structure 446. The N-type drift region 438 is disposed below the isolation structure 434. The N-type lightly doped region 440 is disposed between the gate structure 426 and the first N-type doped region 430. The p-type guard ring 442 is disposed in the p-type well region 424 in a manner corresponding to the edge of the 1^-type well region 422, wherein the doping concentration of the P-type guard ring 442 is greater than the doping concentration of the P-type well region 424. The isolation structure 446 is disposed between the p-type base region 428 and the p-type well region φ, and the N-type isolation ring 436 is, for example, located below the isolation structure 446. The p-type doped region 444 is disposed in the P-type body region 428 and adjacent to the first-N-doped region 430. Specifically, as shown in FIG. 4, the N-type isolation ring 436 is formed simultaneously with the N-type drift region 438 in the same process step, that is, the dopant type, doping concentration, and the doping concentration of the N-type isolation ring 436. The doping depth is substantially the same as the dopant type, doping concentration, and doping depth of the N-type drift region 438. In one embodiment, the type I isolation ring 436 and the N-type drift region 4 = the implanted dopant is arsenic, and the energy forming the N-type isolation ring 436 and the N-type floating raft is about the chamber V-2. keV, its doping concentration is about (four) two / Cm -1013 / Cm2. The N-type isolation ring 436 and the N-type drift region 438 are formed in an amount of, for example, about 15 G keV, and the doping concentration thereof is, for example, 4 χ 1 〇 2 /cm 2 . Figure 5 is an integrated circuit chip in accordance with another embodiment of the present invention, which is not intended. In Fig. 5, the same components as those in Fig. 4 are used. Referring to Fig. 5, the main components constituting the integrated circuit wafer and the main components of the integrated circuit shown in Fig. 17 201019476 ju8-0241 29029twf.doc/n 4 The components are substantially identical, however the difference between the two is primarily due to the dopant species, doping concentration, and doping depth implanted by the N-type isolation ring 436'. The N-type isolation ring 436 is formed simultaneously with the N-type well region 410 in the same process step, that is, the dopant type, doping concentration, and doping depth of the N-plastic isolation ring 436 are substantially identical to the N-type well. The dopant type, doping concentration, and doping depth of the region 410 are the same. In another embodiment, the dopants implanted in the 'N-type isolation ring 436' and the N-type well region 410 are scaled, and the N-type isolation ring 436' and the N-type well region 410 have an energy of about 150 keV. -270 keV ' has a mixed concentration of about 1〇12/CIn2_iQi4/cm2. The implantation energy for forming the N-type isolation ring 436' and the N-type well region 410 is, for example, about 210 keV, and its doping concentration is, for example, about x4xl〇i3/cm2. In FIGS. 4 and 5, by arranging the N-type isolation rings 436, 436 having a larger doping concentration in the outermost periphery of the N-type deep well region 422 to surround the periphery of the LDNMOS element 408, the p-type can be effectively prevented. The base region 428 leaks into the substrate 400 to leak current. In addition, the N-type isolating rings 436, 436 can be integrated with the existing CDMOS process, and can be formed only by the formation of the implant mask φ and the ion implantation process. In order to confirm that the semiconductor device and the integrated circuit chip of the present invention can surely improve the device performance, the characteristics will be described experimentally. The following description of the experimental examples is merely illustrative of the effect of configuring the 隔离-type isolation ring on leakage current, but is not intended to limit the scope of the invention. Experimental Example Fig. 6 is a graph showing the relationship between the gate voltage (^) of the experimental example according to the present invention and the current (Isub) of the substrate 18 ϋ〇 8-0241 29029 twf.doc/n 201019476. In this experimental example, 'in the 0.35 micron 3.35/40 volt CDM 〇s process, and in the case where the distance from the P-type base region to the N-type deep well region is 51 μπι (Ε = 5.1 μιη), The formation conditions of the same well region are implanted with a 隔离-type isolation ring between the source of the LDNMOS and the Ρ-type substrate. As shown in Figure 6, the unloaded Ν-type isolation ring LDNM0S will collapse at a gate voltage of approximately 9.5 volts, causing a rapid increase in substrate leakage current and failure of the LDNMOS. The other curve shows the relationship between the values of the N-type isolation ring. The LDNMOS can withstand the gate voltage exceeding % volts and there is still no collapse. The overall substrate leakage current can also be maintained at a very stable low current value, maintaining the LDNMOS. Operational stability. ~ In summary, the semiconductor device and the integrated circuit chip of the present invention are provided with an isolation ring at the inner edge of the N-type deep well region, and the doping concentration of the ν-type ring is larger than the doping concentration of the N-well region. Because it surrounds the components, it effectively blocks the leakage current path to resolve high-side capability and improve component performance. θ The semiconductor device and the integrated circuit chip of the present invention can be applied to a semiconductor component having power management, and can be combined with the CDM (S) of the financial system by changing the mask pattern, and the process is simple and the wafer can be avoided. Unnecessary waste of area. The invention has been disclosed in the preferred embodiments as above, but it is not intended to limit the invention to any of the technical field of the invention, and it is possible to make some changes and refinements within the scope of the application. The scope of protection for the month is subject to the scope of the patent application attached to the following paragraph 2010 just 76_24129__. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a semiconductor device in accordance with an embodiment of the present invention. Fig. 2A is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view along the line I-Ι in Fig. 2A. 3A is a top plan view of a semiconductor device in accordance with another embodiment of the present invention. Fig. 3B is a schematic cross-sectional view along the Γ-Γ line segment of Fig. 3A. Figure 4 is a cross-sectional view showing an integrated circuit wafer in accordance with an embodiment of the present invention. Figure 5 is a cross-sectional view showing an integrated circuit wafer in accordance with another embodiment of the present invention. Fig. 6 is a graph showing gate voltage (Vgs) versus substrate current (ISUb) according to an experimental example of the present invention. Φ [Description of main component symbols] 10, 20, 408: LDNMOS components 102, 104: Component 106: Regions 200, 400: Substrate 202, 422: N-type deep well regions 203, 203', 424: P-type well regions 204a, 204b 416, 426: gate structure 20 U08-0241 29029twf.doc/n 201019476 206a, 206b, 430: first N-type doping regions 208, 432: second N-type doping regions 210a, 210b, 444: P-type Doped regions 212a, 212b, 428: P-type base regions 214a, 214b, 416a: gates 216a, 216b, 416b: gate dielectric layers 218a, 218b, 416c: spacers 214c: extensions 220: channel regions 222a, 222b, 440: N-type lightly doped regions 224a, 224b, 438: N-type drift regions 226a, 228a, 226b, 228b, 420, 434, 446: isolation structures 230, 442: P-type guard rings 232, 436, 436' : N-type isolation ring 300: spacer 402: first region 404: second region 406: CMOS component 410: N-type well region 412: NMOS transistor 414: PMOS transistor 418: doped region 21