201019437 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體裝置、嵌埋電子元件之封裝 構、及其製法’尤指一種適用於大區域且多電子元件之 5 10 15 e 半導體裝置、嵌埋電子元件之封裝結構、及其製法，以提 升對位之精準度。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (integration)以及微型化（miniatuHzati〇n)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (intedayei· connection)擴大電路板上可利用的佈線面積而 配合咼電子密度之積體電路（integrated circuit)需求。 一般半導體裝置之製程，首先係由晶片載板製造業者 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 線、封膠以及植球等封裝製程。又一般半導體封裝是將半 導體晶片背面黏貼於封裝基板頂面進行打線接合（wire bonding)，或者將半導體晶片之作用面以覆晶接合（fnpchip) 方式與封裝基板接合，再於基板之背面植以焊料球以供與 其他電子裝置進行電性連接。 20 201019437 5 參 10 15 ❿ 隨著技術發展，近來有許多研究發展出電子元件嵌埋 於基板中之方法，在相同封裝單位體積中容納更多數量的 線路及電子元件，以滿足電子產品輕薄短小化之需求。業 界現行嵌埋晶片於基板之技術中，多將晶片埋入基板後， 於晶片及基板表面同時進行增層。其中，美國專利第 6928726號，係揭示一種嵌埋電子元件之封裝結構及其製作 方法’以將電子元件嵌埋於封裝基板。 請參閱圖1A至圖1D，此為習知之嵌埋電子元件之封裝 結構之製作流程剖視圖。首先，如圖1A所示，提供一表面 具有線路層51a之核心板4。接著，於核心板4形成一貫穿開 口 420,而後將一電子元件丨置入此貫穿開口42〇。而後，利 用增層技術，形成一增層結構6a於電子元件1及核心板4之 表面，其中此增層結構6a具有一介電層6〇、介電層6〇表面 之第二線路層62、及導電盲孔63，如圖1B所示。在形成增 層結構的過程中，經熱壓後，介電層6〇會流入電子元件1及 貫穿開口 420間的間隙44中，使電子元件i固定於核心板4之 貝穿開口中。此外，增層結構6a之導電盲孔63係使用雷射 燒灼（laser ablation)的方式形成在介電層6〇中，且部分之導 電盲孔63係電性連接於電子元件丨之電極墊丨丨。此外，更於 核心板4之兩側分別進行增層製程，以形成一嵌埋電子元件 之封裝基板，如圖1C所示。 因此，若要電性連接電子元件與增層結構之第二線路 層，必須在對應於電子元件之電極墊位置之介電層進行雷 射燒灼以形成導電盲孔，以達到最佳的對位精準度。然而， 20 201019437 對各個電子元件分別進行對位，將择 5 ❹ 10 其他各增層線路的電性連接更須重^的=此外’ 導::孔，無法r高產量之需求，，在= -會電盲孔時若產生對位偏移的情形，可 到電子元件的問題，更可能會造成 題或缺點之封裝 ’並避免因雷射 因此，現行亟需研發出能改善上述問 基板結構，以提升電子元件之對位精準度 燒灼而造成電子元件之損傷。 【發明内容】 本發明之主要目的係在提供一種半導體裝置及包含其 之敌埋電子元件之封裝基板結構，俾能藉由提升電子元件 之對位精準度’而改善因電子元件對位偏移而影響品質及 15 良率的問題。 本發明之另一目的係在提供一種半導體裝置及包含其 ❹ ^埋電子it件之封裝基板結構之製法，俾能大面積進行 電子元件之對位，而節省製作成本且提升量產能力。 為達成上述目的，本發明提供一種半導體 ： 20 —電子元件’係具有相對之_作用面、一非作用面、及」 保護層，該作用面具有複數電極墊，該保護層係設於該作 用面，且該保護層具有複數第一開孔以使該第一開孔中之 該等電極墊不被保護層所覆蓋；一承載板，係具有一第一 表面及一相對之第二表面，該第一表面設有複數金屬凸 6 201019437 塊，該等金屬凸塊具有與該第一表面接著之第二端及面向 該等電極墊之第-端；以及複數谭料凸塊，係設於該等電 極墊與該等金屬凸塊間，以電性連接該等電極塾與該 屬凸塊。 ^ 5 此外，本發明亦提供一種嵌埋電子元件之封裝結構， 包括：一電子元件，係具有相對之一作用面、一非作用面、 及一保護層，該作用面具有複數電極墊，該保護層係覆蓋 豸作用面，且該保護層具有複數第-開孔以使該第一開孔 +之該等電極墊不被保護層所覆蓋；複數金屬凸塊，係具 10有第:端及相對之第二端，且該等第一端係面向該等電極 塾；複數焊料凸塊，係設於該電子元件之該等電極塾及該 等金屬凸塊間，以電性連接該等電極塾與該等金屬凸塊； 以及-核心板，其包括一核心層及一第一介電層，該核心 層具有一第三表面、一第四表面、及一貫穿開口，該第一 15介電層具有一第五表面及一第六表面該核心層之該第四 表面係與該第一介電層之該第五表面相結合，而該電子元 〇 件係設於該貫穿開口内。 於本發明之一實施態樣中，上述之嵌埋電子元件之封 裝結構可更包括一第一線路層，該第一線路層係設於該第 20 一介電層之該第六表面並電性連接至該等金屬凸塊之該第 二端。此外，於本實施態樣中，嵌埋電子元件之封裝結構 可更包括至少一第一增層結構，係設於該核心板之該第一 介電層之該第六表面及該第一線路層上，其中該第一增層 結構具有至少一第三介電層、至少一疊置於該第三介電層 201019437 上之第—線路層、及複數電性連接該第一線路層與該第二 線路層之導電盲孔。 此外，於本發明之另一實施態樣中，嵌埋電子元件之 封裝結構之核心板可更包括一第二介電層，該第二介電層 具有一第七表面及一第八表面，該第二介電層之該第八表 '、/、核、層之該第二表面相結合，使該核心層設於該 第介電層及該第二介電層間，且該第二介電層係與該電201019437 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, a package structure of embedded electronic components, and a method of manufacturing the same, particularly a 5 10 15 e suitable for large-area and multi-electronic components The semiconductor device, the package structure of the embedded electronic component, and the manufacturing method thereof, to improve the accuracy of the alignment. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high integration and miniaturization requirements of semiconductor packages, most active and passive components and circuit-connected circuit boards are gradually evolved from single-layer boards to multi-layer boards. In a limited space, the inter-layer connection technology (intedayei·connection) is used to expand the available wiring area on the board to meet the requirements of the integrated circuit of the electron density. In general, the process of a semiconductor device is firstly produced by a wafer carrier manufacturer for a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. The wafer carriers are then placed in a packaging process by a semiconductor packager for crystallization, wire bonding, encapsulation, and ball placement. In a general semiconductor package, the back surface of the semiconductor wafer is adhered to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by flip chip bonding, and then implanted on the back surface of the substrate. The solder balls are electrically connected to other electronic devices. 20 201019437 5 Ref. 10 15 ❿ With the development of technology, many recent studies have developed methods for embedding electronic components in substrates, accommodating a larger number of lines and electronic components in the same package unit volume to meet the light and short electronic products. Demand for change. In the current technology of embedding a wafer in a substrate, the wafer is often embedded in a substrate, and the wafer and the surface of the substrate are simultaneously layered. Among them, U.S. Patent No. 6,928,726 discloses a package structure for embedding electronic components and a method of fabricating the same to embed electronic components in a package substrate. Please refer to FIG. 1A to FIG. 1D, which are cross-sectional views showing the fabrication process of a conventional package structure for embedded electronic components. First, as shown in Fig. 1A, a core board 4 having a wiring layer 51a on its surface is provided. Next, a through opening 420 is formed in the core board 4, and then an electronic component is placed in the through opening 42A. Then, a build-up structure 6a is formed on the surface of the electronic component 1 and the core board 4 by a build-up technique, wherein the build-up structure 6a has a dielectric layer 6〇, and a second trace layer 62 of the dielectric layer 6〇 surface. And the conductive blind hole 63, as shown in FIG. 1B. In the process of forming the build-up structure, after the hot pressing, the dielectric layer 6 流入 flows into the gap 44 between the electronic component 1 and the through opening 420, so that the electronic component i is fixed in the via opening of the core board 4. In addition, the conductive blind vias 63 of the build-up structure 6a are formed in the dielectric layer 6 by laser ablation, and a part of the conductive vias 63 are electrically connected to the electrode pads of the electronic component. Hey. In addition, a build-up process is separately performed on both sides of the core board 4 to form a package substrate in which electronic components are embedded, as shown in Fig. 1C. Therefore, if the second circuit layer of the electronic component and the build-up structure is to be electrically connected, laser cauterization must be performed on the dielectric layer corresponding to the position of the electrode pad of the electronic component to form a conductive blind via hole for optimal alignment. Precision. However, 20 201019437 separately aligns the various electronic components, and selects 5 ❹ 10. The electrical connection of the other additional layers is more important. ^ In addition: the hole: cannot meet the demand of high output, at = - If there is a misalignment when the blind hole is generated, the problem of the electronic component may be caused, and the package of the problem or the defect may be caused to avoid the laser. Therefore, it is urgent to develop an improved substrate structure. In order to improve the accuracy of the alignment of electronic components, the electronic components are damaged. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor device and a package substrate structure including the embedded electronic component thereof, which can improve the alignment deviation of the electronic component by improving the alignment accuracy of the electronic component. And the problem that affects quality and 15 yield. Another object of the present invention is to provide a semiconductor device and a method of fabricating a package substrate including the same, which can perform alignment of electronic components over a large area, thereby saving manufacturing costs and improving mass production capability. In order to achieve the above object, the present invention provides a semiconductor: 20 - an electronic component ' has a relative _ active surface, a non-active surface, and a protective layer, the active surface having a plurality of electrode pads, the protective layer being disposed in the role And the protective layer has a plurality of first openings such that the electrode pads in the first opening are not covered by the protective layer; a carrier plate having a first surface and an opposite second surface, The first surface is provided with a plurality of metal bumps 6 201019437 blocks having a second end adjacent to the first surface and a first end facing the electrode pads; and a plurality of tan bumps The electrode pads and the metal bumps are electrically connected to the electrode pads and the gene bumps. In addition, the present invention also provides a package structure for embedding an electronic component, comprising: an electronic component having a relatively active surface, a non-active surface, and a protective layer, the active surface having a plurality of electrode pads, The protective layer covers the 豸 active surface, and the protective layer has a plurality of first-opening holes such that the electrode pads of the first opening + are not covered by the protective layer; the plurality of metal bumps, the pedestal 10 has the first end And the second end of the second end, and the first end faces the electrode 塾; the plurality of solder bumps are disposed between the electrodes of the electronic component and the metal bumps to electrically connect the electrodes And a core plate comprising a core layer and a first dielectric layer, the core layer having a third surface, a fourth surface, and a through opening, the first 15 The dielectric layer has a fifth surface and a sixth surface. The fourth surface of the core layer is combined with the fifth surface of the first dielectric layer, and the electronic element is disposed in the through opening. . In an embodiment of the present invention, the package structure for embedding the electronic component further includes a first circuit layer disposed on the sixth surface of the 20th dielectric layer and electrically Sexually connected to the second end of the metal bumps. In addition, in this embodiment, the package structure for embedding the electronic component further includes at least one first build-up structure disposed on the sixth surface of the first dielectric layer of the core board and the first line The first build-up structure has at least one third dielectric layer, at least one first circuit layer stacked on the third dielectric layer 201019437, and a plurality of electrically connected to the first circuit layer Conductive blind hole of the second circuit layer. In addition, in another embodiment of the present invention, the core board of the package structure for embedding the electronic component further includes a second dielectric layer, the second dielectric layer having a seventh surface and an eighth surface. The second surface of the second dielectric layer, the core layer, and the second surface of the layer are combined such that the core layer is disposed between the dielectric layer and the second dielectric layer, and the second dielectric layer Electrical layer and the electricity
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子7^^件之該非作用面相結合。於本實施態樣中，嵌埋電子 疋件之封裝結構可更包括二第一線路層，該等第一線路層 係=別設於該第一介電層之該第六表面、及該第二介電層 之該第七表面。此外，核心板可更包括複數導電通孔，該 等導電通孔係貫穿該核心層、該第一介電層、及該第二介 電層，以電性連接該等第一線路層。同時，於本實施態樣 中、，封裝結構可更包括二第一增層結構，係分別設於該核 板之4第一介電層之該第六表面該第二介電層之該第 表面、及該等第一線路層上，其中各該第一增層結 有至少一第三介電層、至少一疊置於該第三介電層上之第 一線路層、及複數電性連接該等第一線路層與該第二線路 層之導電盲孔。 ' 另一方面，本發明亦提供另一種嵌埋電子元件之封聿 結構’包括：—電子元件，係具有相對之—作用面、1 作用面、及一保護層’該作用Φ具有複數電極塾，該保護 ㈣覆蓋該作用面，且該保制具有複數第—開孔以使該 第開孔中之該等電極墊不被保護層所覆蓋；複數金屬凸 20 201019437 塊，係具有第-端及相對之第二端，且該等第—端係面向 該等電極墊；複數焊料凸塊，係設於該電子元件之該等電 極墊及該等金屬凸塊間’以電性連接該等電極塾與該等金 5 10 15 20 屬凸塊；以及一核心板，其包括一第一介電層，該第一介 電層具有-第五表面及-第六表面，而該電子元件係喪埋 於該第一介電層中。 於本發明之再一實施態樣中，上述之嵌埋電子元件之 封裝結構可更包括H路層，該第—線路層係設於該 第一介電層之該第六表面並電性連接至該等金屬凸塊之該 第二端。此外，於本實施態樣中，封裝結構可更包括至少 第一增層結構，係設於該核心板之該第一介電層之該第 2表面及該第一線路層上，其中該第一增層結構具有至少 -第三介電層、至少一疊置於該第三介電層上之第二線路 層、及複數電性連接該第一線路層與該第二線路層之導電 盲孔。 此外，於本發明之更一實施態樣中，嵌埋電子元件之 封襄結構之核心板可更包括-第二介電層，胃第二介電層 具有一第七表面及一第八表面，該第二介電層之該第八表 面係與該第一介電層之該第五表面相結合，且該第二介電 層係覆蓋該電子元件之該非作用面。於此實施態樣中，封 裝結構可更包括二第一線路層，該等第一線路層係分別設 於該第一介電層之該第六表面及該第二介電層之該第七表 面同時，於本實施態樣中，核心板可更包括複數導電通 孔，該等導電通孔係貫穿該第一介電層、及該第二介電層， 9 201019437 以電性連接該等第-線路層。此外，於本實施態樣中封 裝結構可更包括二第一增層結構，係分別設於該核心板之 該第一介電層之該第六表面、言亥第二介電層之該第七表 5 ❹ 10 15 面、及該等第一線路層上，其中該第一增層結構具有至少 -第三介電層、至少一疊置於該第三介電層上之第二線路 層、及複數電性連接該等第一線路層與該第二線路層之 電盲孔。 於上述之半導體裝置及嵌埋電子元件之封裝結構中， 電子元件可更包括複數金屬墊，係覆蓋該等電極墊，且該 等焊料凸塊係藉由該等金屬塾電性連接該等電極塾。此 外’金屬墊之材料可分別選自焊料、銀、金、鎳,金、鎳/ 鈀/金、及其組合所組群組之其中一者。 再者，於上述之半導體裝置及嵌埋電子元件之封裝結 構中’半導體裝置可更包括一保護金屬層，係完全覆蓋該 承載板之第-表面’且該等金屬凸塊係設於該保護金屬層 之表面上。 於上述之半導體裝置及嵌埋電子元件之封裝結構中， 金屬凸塊之材料可分別選自烊料、銅、銀、金、錄/金、錄 /鈀/金、及其組合所組群組之其中一者。 另一方面，本發明提供一種半導體裝置之製法，包括 下列步驟.(A)提供一電子元件及一承載板，其中該電子 疋件/、有相對之-作用面、一非作用面、及一保護層，該 作用面具有複數電極墊’該保護層係設於該作用面，該保 4層具有複數第一開孔以使該第一開孔中之該等電極塾不 20 201019437 被保護層所覆蓋’該承戴板具有—第—表面及—相對之第 二表面，該第-表面設有複數金屬凸塊，且該等金屬凸塊 具有與該第-表面接著之第二端及面向該等電極塾之第一 端；以及（B)㈣複數焊料凸塊於該電子元件及該承載板 間，該等焊料凸塊係分別對應且電性連接該等電極塾愈該 等金屬凸塊。 〃 e 10 15The non-active surfaces of the sub-pieces are combined. In this embodiment, the package structure of the embedded electronic component may further include two first circuit layers, the first circuit layer is disposed on the sixth surface of the first dielectric layer, and the first The seventh surface of the two dielectric layers. In addition, the core board may further include a plurality of conductive vias extending through the core layer, the first dielectric layer, and the second dielectric layer to electrically connect the first circuit layers. In the embodiment, the package structure may further include two first build-up structures, which are respectively disposed on the sixth surface of the first dielectric layer of the core plate and the second dielectric layer. And a surface of the first circuit layer, wherein each of the first build-up layers has at least one third dielectric layer, at least one first circuit layer stacked on the third dielectric layer, and a plurality of electrical layers Connecting the first circuit layer and the conductive via hole of the second circuit layer. On the other hand, the present invention also provides another sealing structure for embedded electronic components' including: - an electronic component having a relative - active surface, an active surface, and a protective layer Φ having a plurality of electrodes The protection (4) covers the active surface, and the protection has a plurality of first openings to prevent the electrode pads in the first opening from being covered by the protective layer; the plurality of metal protrusions 20 201019437 blocks having a first end And the opposite ends of the second end, and the first end faces the electrode pads; the plurality of solder bumps are disposed between the electrode pads of the electronic component and the metal bumps to electrically connect the electrodes An electrode 塾 and the gold 5 10 15 20 are bumps; and a core plate including a first dielectric layer having a fifth surface and a sixth surface, and the electronic component The burial is buried in the first dielectric layer. In a further embodiment of the present invention, the package structure of the embedded electronic component may further include an H-channel layer disposed on the sixth surface of the first dielectric layer and electrically connected To the second end of the metal bumps. In addition, in this embodiment, the package structure may further include at least a first build-up structure disposed on the second surface of the first dielectric layer of the core board and the first circuit layer, wherein the first a build-up structure having at least a third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrically conductively electrically connected to the first circuit layer and the second circuit layer hole. In addition, in a further embodiment of the present invention, the core board of the sealing structure embedded with the electronic component may further include a second dielectric layer, the second dielectric layer of the stomach having a seventh surface and an eighth surface The eighth surface of the second dielectric layer is bonded to the fifth surface of the first dielectric layer, and the second dielectric layer covers the non-active surface of the electronic component. In this embodiment, the package structure may further include two first circuit layers respectively disposed on the sixth surface of the first dielectric layer and the seventh surface of the second dielectric layer At the same time, in the embodiment, the core board may further include a plurality of conductive vias extending through the first dielectric layer and the second dielectric layer, 9 201019437 to electrically connect the core layers. First-line layer. In addition, in the embodiment, the package structure may further include two first build-up structures respectively disposed on the sixth surface of the first dielectric layer of the core board and the second dielectric layer of the second dielectric layer And the first circuit layer, wherein the first build-up structure has at least a third dielectric layer and at least one second circuit layer stacked on the third dielectric layer And electrically connecting the first circuit layer and the second circuit layer to the electric blind hole. In the above-mentioned package structure of the semiconductor device and the embedded electronic component, the electronic component may further include a plurality of metal pads covering the electrode pads, and the solder bumps are electrically connected to the electrodes by the metal wires private school. Further, the material of the metal pad may be selected from the group consisting of solder, silver, gold, nickel, gold, nickel/palladium/gold, and combinations thereof, respectively. Furthermore, in the above-described package structure of the semiconductor device and the embedded electronic component, the 'semiconductor device may further include a protective metal layer that completely covers the first surface of the carrier plate and the metal bumps are attached to the protection On the surface of the metal layer. In the above package structure of the semiconductor device and the embedded electronic component, the material of the metal bumps may be selected from the group consisting of tantalum, copper, silver, gold, gold/gold, recording/palladium/gold, and combinations thereof. One of them. In another aspect, the present invention provides a method of fabricating a semiconductor device, comprising the steps of: (A) providing an electronic component and a carrier, wherein the electronic component has a relative active surface, a non-active surface, and a a protective layer having a plurality of electrode pads disposed on the active surface, the protective layer having a plurality of first openings such that the electrodes in the first opening are not 20 201019437 protected layer Covering the 'the wearing board has a first surface and an opposite second surface, the first surface is provided with a plurality of metal bumps, and the metal bumps have a second end and a surface facing the first surface a first end of the electrode ;; and (B) (4) a plurality of solder bumps between the electronic component and the carrier plate, the solder bumps respectively corresponding to and electrically connected to the electrodes to cure the metal bumps . 〃 e 10 15
此外，本發明亦提供-種歲埋電子元件封裝結構之製 法，包括下列步驟、A)提供一電子元件及一承載板，苴 中該電子元件具有相對之-作用面、_非作用面及一保 護層’該作用面具有複數電極墊，該保護層係設於該作用 面，該保護層具有複數第-開孔以使該第—開孔中之該等 電極墊不被保護層所覆蓋，該承載板具有—第—表面及一 相對之第二表面’該第一表面設有複數金屬凸塊，且該等 金屬凸塊具有與該第-表面接著之第二端及面向該等電極 塾之第一端；（B)形成複數焊料凸塊於該電子元件及該承 載板間，該料料凸塊係㈣對應且電性連接該等電極塾 與該等金屬凸塊；（C)开>成一核心板，其包括一核心層及 一第一介電層，該核心層具有一第三表面、一第四表面、 及-貫穿開口，該第一介電層具有_第五表面及一第六表 面，該核心層之該第四表面係與該第一介電層之該第五表 面相結合，而該電子元件係設於該貫穿開口内；以及（D)移 除該承載板。 於本發明之一實施態樣中，於步驟（D)後可更包括一 步驟（D1):於該第一介電層之該第六表面及該等金屬凸塊 20 201019437 5 參 10 15 Φ 20 之該第二端上’形成一第一線路層。此外，於本實施態樣 中’於步驟（D1)後，可更包括一步驟（D2):於該第一介電層 之該第六表面及該第一線路層上，形成至少一第一增層結 構’其中該第一增層結構具有至少一第三介電層、至少一 疊置於該第三介電層上之第二線路層、及複數電性連接該 第一線路層與該第二線路層之導電盲孔。 此外，於本發明之另一實施態樣中，步驟（D)中之該核 心板更包括一第二介電層，該第二介電層具有一第七表面 及一第八表面，該第二介電層之該第八表面係與該核心層 之該第三表面相結合’使該核心層設於該第一介電層及該 第二介電層間’且該第二介電層係覆蓋該電子元件之該非 作用面。於本實施態樣中’步驟(m)後，更包括一步驟 (D1’ ）：形成複數導電通孔、及二第一線路層，其中，該 等導電通孔係貫穿該核心層、該第_介電層、及該第二介 電層，以電性連接該等第—線路層，且該等第—線路層係 分別設於該第一介電層之第六表面及該第二介電層之第七 表面。同時，在本實施態樣中，步驟(m，）後，更包括一 步驟cm’於該核心板之該第—介電層之該第六表面、 該第二介電層之該第七表面、及該等第—線路層上分別 = 增層結構，其中各該第—增層結構具有至少- 一1 1》一#置於該第三介電層上之第二線路 層、及複數電性連接該第—線路層與該第二線路層之導電 盲孔。 12 201019437 構之製法，包括ΐ:步月:乂:另:種嵌埋電子元件封裝結 10 r其中該電子元件具有相對之一作用面、一:=載 ::保護層’該作用面具有複數電極墊：於 該，’該保護層具有複數第一開孔以使該;層= 之該等電極塾不被保護層所覆蓋，該承載板具有-第—表 面及相對之第一表面’該第一表面設有複數金屬凸塊， =該等金屬凸塊具有與該第一表面接著之第二端及面向該 電極墊之第-端；(B)形成複數焊料凸塊於該電子元件 及該承載板間，該等焊料凸塊係分別對應且電性連接該等 電極塾與該等金屬凸塊；（C)形成一核心板’其包括一第 一介電層，該第一介電層具有一第五表面及一第六表面， 而該電子元件係嵌埋於該第一介電層中；以及（D)移除該 承載板。 、*" 15 於本發明之再一實施態樣中，於步驟（D)後，可更包括 一步驟（D1):於該第一介電層之該第六表面及該等金屬凸 〇 塊之該第二端上，形成一第一線路層。此外，於本實施態 樣中’步驟（D1)後可更包括一步驟（D2):於該第一介電層之 該第六表面及該第一線路層上，形成至少一第一增層結 20 構’其中該第一增層結構具有至少一第三介電層、至少一 疊置於該第三介電層上之第二線路層、及複數電性連接該 第一線路層5與該第二線路層之導電盲孔。 另一方面，於本發明之更一實施態樣中，步驟（D)中之 該核心板更包括一第二介電層，該第二介電層具有一第七 13 201019437 表面及 ' 一第八表面後—>V ¢3¾ c? 第一"電層之該第八表面係與該第 ;:電：之該第五表面相結合，且該第二介電層係覆蓋該 5 Φ 10 15 ❹ 後可更包括-步驟⑼，）：形成複數導電通孔、及二^ ^路=中’該等導電通孔係貫穿該第一介電層、及該 第二"電層，以電性連接該等第一線路層，且該等第一線 別設於該第一介電層之第六表面及該第二介電層 之第七表面。同時’在本實施態樣中，步驟（m，）後 包括-步驟（D2’）：於該核心板之該第一介電層之該第六 表面、該第二介電層之該第七表面、及該等第一線路層上’： 分別形成二第-增層結構’其中各該第一增層結構具有至 乂第一介電層、至少一疊置於該第三介電層上之第二線 路層、及複數電性連接該第一線路層與該第二線一之 導電盲孔。 於上述之半導體裝置及嵌埋電子元件之封裝結構中， 承載板可更包括一保護金屬層，係完全覆蓋該承載板之第 -表面’且該等金屬凸塊係設於該保護金屬層之表面上。 同時，於上述之半導體裝置及嵌埋電子元件之封裝结 構中，電子元件可更包括複數金屬墊，係覆蓋該等電極塾、: 且該等谭料凸塊係藉由該等金屬墊電性連接該等電極塾。 此外，金屬墊13之材料可分別選自焊料、銀金、鎳/金、 鎳/鈀/金、及其組合所組群組之其中一者。 再者，於上述之半導體裝置及嵌埋電子元件之封裝任 構中，於步驟（B)中，該等焊料凸塊可_成在該等金屬凸° 20 201019437 5 e 10 15 20 鬼之第端上，再與該金屬凸塊焊接。或者，步驟⑻中， 該等焊料凸塊係先形成在該等金屬塾上，再與該 焊接。 此外，於_L述之半導體裝置及嵌埋電子元件之封裝結 構中，金屬凸塊之材料可分別選自焊料、銅、銀、金、錄/ 金、鎳/鈀/金、及其組合所組群組之其中一者。 習知之嵌埋電子元件之封裝結構，需對增層結構進行 雷射燒灼，以將各個電子元件之電極塾與電性連接塾電性 連接。然而’電子元件所置入的位置，往往造成電極塾盘 電性連接墊電性連接之誤差。反之，本發明之半導體裝置^ 嵌埋電子元件之封裝結構、及其製法，先利用金屬凸塊(可 用以做為電性連接墊）與電子元件覆蓋於電極墊上之金 塾進订對位’再利料料凸塊連接金屬凸塊與電子元件， 而達到提升對位精準叙效果。因此，利用本發明之半導 體裝置、钱埋電子元件之封裝結構、及其製法，可減少一 次雷射燒灼’即不需進行雷射燒灼形成將電子元件之電極 墊與電性連接墊電性連接之導電盲孔，不僅可避免電子元 件受到損害’且由於對位精準度之提高’以一次對位即可 同時進行整版面基板上全數晶片之電性連接 :之製作亦只須一次對位，同時提高封裝結構之上: 二製程以滿足量產之效率’且更易於應用在大面 積且多電子元件之封裝結構中。 實施方式】 15 201019437 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書申的各項細節亦 5 ❹ 10 15 ❹ 20 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 實施例1 请參考圖2A至圖2G，此為本實施例之嵌埋電子元件之 封裝結構之製作流程剖視圖。 如圖2A所示，首先’提供一電子元件！及一承載板2〇， 其中電子元件1具有相對之一作用面lb、一非作用面ia、及 一保護層12 ’作用面ib具有複數電極墊，保護層12係設 於作用面lb，保護層12具有複數第一開孔121以使第一開孔 121中之電極墊11不被保護層12所覆蓋，承載板2〇具有一第 一表面2a及一相對之第二表面2b，第一表面2a設有複數金 屬Λ塊21 ’且金屬凸塊21具有與第一表面2a接著之第二端 21b及面向電極墊11之第一端2ia。 此外’如圖2A所示’承載板20可更包括一保護金屬層 22 ’係完全覆蓋承載板2〇之第一表面2a，且金屬凸塊21係 設於保護金屬層22之表面22a上。藉由此保護金屬層22可防 止後續製程破壞電子元件1。 再者’如圖2A所示，電子元件1可更包括複數金屬墊 13，係覆蓋電極墊u，且焊料凸塊31係藉由金屬墊13電性 連接電極墊11。其中，金屬墊13之材料可分別選自焊料、 16 201019437 銀、金、鎳/金、鎳/把/金、及其組合所組群組之其中一者。 此外，金屬塾13可以焊料下凸塊（under bump metal, UBM)、 化錄浸金（Electroless Ni & Immersion Gold, ENIG)、化學鑛 錄纪浸金（electroless nickel & electroless palladium & 5 immersion gold, ENEPIG)等方式形成。於本實施例中，覆 蓋電極墊11之金屬墊13，係以焊料下凸塊之方式形成。 另一方面，金屬凸塊21之材料可分別選自焊料、銅、 銀、金、錄/金、錄/纪/金、及其組合所組群組之其中一者。 〇 其中，金屬凸塊21可為一銅塊、一具有電性連接墊之銅塊、 10 或一外表面鍵有金屬層（Ni/Au或Ni/Pd/Au)之銅塊。於本實 施例中，金屬凸塊2 1係為一銅塊。此外，金屬凸塊21可為 長方體、圓柱體、或梯形趙。於本實施例中，金屬凸塊21 為一圓柱體。 此外，如圖2A’所示’此為本發明之另一實施態樣，其 15 中，覆蓋電子元件1電極墊11之金屬墊13係以化學鍍鎳鈀浸 金的方式形成，且設於承載板20上之金屬凸塊21更具有一 φ 電性連接墊21’。 接下來，如圖2A所示’形成複數焊料凸塊31於電子元 件1及承載板20間，而焊料凸塊31係分別對應且電性連接電 20 極墊11與金屬凸塊21。在此，焊料凸塊31可先形成在金屬 凸塊21之第一端21a上’再與金屬凸塊21焊接；或者焊料凸 塊31可先形成在金屬墊13上，再與金屬凸塊21焊接。於本 實施例中，焊料凸塊31係先形成在金屬凸塊21之第一端21a 17 201019437 上，再與金屬凸塊21焊接’以形成一半導體裝置，如圖2B 所示。 因此’如圖2B所示’本實施例所製備之半導體裝置， 其包括：一電子元件1，係具有相對之一作用面化、一非作 5 用面la、及一保護層12’作用面lb具有複數電極墊丨丨，保 護層12係設於作用面lb，且保護層12具有複數第一開孔121 以使第一開孔121中之電極墊11不被保護層12所覆蓋；一承 載板20 ’係具有一第一表面2a及一相對之第二表面2b，第 © 一表面2a設有複數金屬凸塊21 ’金屬凸塊21具有與第一表 10 面2a接著之第二端21b及面向電極墊11之第一端21a ;以及 複數焊料凸塊31，係設於電極墊11與金屬凸塊21間，以電 性連接電極墊11與金屬凸塊21。 接下來’如圖2C所示，形成一核心板4,其包括一核心 層42及一第一介電層41，核心層42具有一第三表面42a、一 15 第四表面42b、及一貫穿開口 420，第一介電層41具有一第 五表面41a及一第六表面41b，核心層42之第四表面42b係與 ^ 第一介電層41之第五表面41 a相結合，而電子元件1係設於 貫穿開口 420内。 此外’如圖2C所示，核心板4更包括一第二介電層43， 20 該第二介電層43具有一第七表面43a及一第八表面43b，第 二介電層43之第八表面43b係與核心層42之第三表面42a相 結合’使核心層42設於第一介電層41及第二介電層43間， 且第二介電層43係覆蓋電子元件1之非作用面la。 18 201019437 其中，核心板4可以習知之方法形成，如壓合、真空貼 合、塗佈、或印刷等方式。此外，上述之第一介電層41與 第二介電層43之材料，可為習知常用之有機介電材料，如： ABF(Ajinomoto Build-up Film)、雙順丁酿二酸酿亞胺/三氮 5 陕（Bismaleimide triazine，BT)、聯二苯環 丁二晞 (benzocylobutene，BCB)、液晶聚合物（Liquid Crystal Polymer)、聚亞酸胺（Polyimide， PI)、聚乙烯謎 (Poly(phenylene ether))、聚四氟i 乙 浠(Poly ⑩ （tetra-fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂或玻 10 璃纖維等感光或非感光有機樹脂，或混合環氧樹脂與玻璃 纖維等材質。 此外，第一介電層41或第二介電層43之介電材料，可 填充於核心層42貫穿開口 421與晶片1之間之間隙44。電性 連接結構3間之間隙410，可能會未填充介電材料、部分填 15 充有第一介電層41之介電材料、或完全填充有第一介電層 41之介電材料等情形發生。 φ 接下來，如圖2D所示，移除承載板20。此外，移除承 載板20時，也可同時移除保護金屬層22。其中，電性連接 結構3間之間隙410未填充有任何介電材料。或者，如圖2D’ 20 所示，電性連接結構3間之間隙410完全填充有第一介電層 41之介電材料。 接著，如圖2E所示，於第二介電層43之第七表面43a 及第一介電層41之第六表面41b上，分別形成金屬層51， 51’，以用於圖案化形成線路層。 19 201019437 如圖2F所示，形成複數導電通孔45、及二第一線路層 51b，51a，其中，導電通孔45係貫穿核心層42、第一介電層 41、及第二介電層43，以電性連接第一線路層51a，51b，且 第一線路層51b，51a係分別設於第一介電層41之第六表面 5 41b及該第二介電層43之第七表面43a。 接下來’如圖2G所示’於核心板4之第一介電層41之 第六表面41b、第二介電層43之第七表面43a、及第一線路 層51b，5 la上，分別形成二第一增層結構6b，6a，其中各第 ❿一增層結構6b，6&具有至少一第三介電層61、至少一疊置於 10第二介電層61上之第二線路層62、及複數電性連接第一線 路層51 b，51 a與第二線路層62之導電盲孔63。 此外，各第一增層結構6a，6b分別具有一防焊層7a, 7b’而防焊層7a，7b具有複數開孔7〇，以顯露電性連接墊 64，如圖2G所示。 15 實施例2 φ —本實施例之半導體裝置之製法與實施例！相同，除了覆 蓋電子7G件1電極墊1丨之金屬墊13係以化學鍍鎳鈀浸金的 方式形成’如圖3A所示。接著’形成一核心板4，其包括一 20核心層42及一第一介電層41，且核心層42之貫穿開口421與 晶片1之間的間隙，係填充有第一介電層41之介電材料。 接著，如圖3B所示，移除該承載板2〇及保護金屬層22 後，即形成一種嵌埋電子元件之封装結構。本實施例之嵌 埋電子7L件之封裝結構，包括：一電子元件丨，係具有相對 25之一作用面1b、一非作用面la、及一保護層12，作用面lb 20 201019437 具有複數電極墊11，保護層12係覆蓋作用面lb，且保護層 12八有複數第一開孔121以使第一開孔121中之電極塾11不 被保護層12所覆蓋；複數金屬凸塊21，係具有第一端2u及 相對之第—端2ib，且該等第一端2ia係面向該等電極墊 5 U ;複數焊料凸塊31，係設於電子元件丨之電極墊丨丨及金屬 凸塊21間，以電性連接電極墊u與金屬凸塊21 ;以及一核 心板4’其包括一核心層42及一第一介電層41，核心層化具 有一第二表面42a、一第四表面42b、及一貫穿開口 420，第 ® 一介電層41具有一第五表面41 a及一第六表面4 lb，核心層 1〇 42之第四表面42b係與第一介電層41之第五表面41a相結 合’而電子元件1係設於貫穿開口 420内。 接著，如圖3C所示，於第一介電層41之第六表面 及金屬凸塊21之該第二端21b上，形成一第一線路層51b。 其中’第一線路層51b係設於第一介電層41之第六表面41b 15 並電性連接至金屬凸塊21之第二端21b。 如圖3D所示’於第一介電層41之第六表面4 lb及第一 ❾ 線路層51b上，形成至少一第一增層結構6b，其中第一增層 結構6b具有至少一第三介電層61、至少一疊置於第三介電 層61上之第二線路層62、及複數電性連接第一線路層5 lb與 20 第二線路層62之導電盲孔63。 此外’第一增層結構6b更具有一防焊層7b，而防焊層 7b具有複數開孔70，以顯露電性連接墊64，如圖3D所示。 另一方面，本實施例之後埋電子元件之封裝結構，更 可進行雙邊增層，如圖3D’所示。於核心層42之第三表面42a 21 201019437 及電子兀件i非作用Sla上，更形成至少一第一增層結構 6a，其中第一增層結構6a具有至少一第三介電㈣、至少 -疊置於第三介電層61上之第二線路層62、及複數電性連 接第線路層51b與第二線路層62之導電盲孔63。且第一增 層結構6a更具有一防焊層7a’而防焊層〜具有複數開： 70，以顯露電性連接墊64。 實施例3 > 請參考圖4A至圖4G，此為本實施例之嵌埋電子元件之 10 封裝結構之製作流程剖視圖。 首先，如圖4A所示，提供一電子元件丨及一承載板2〇, 其中電子元件1具有相對之一作用面lb、一非作用面la、及 一保護層12，作用面lb具有複數電極，保護層12係設 於作用面lb，保護層12具有複數第一開孔121以使第一開孔 15 121中之電極墊11不被保護層12所覆蓋，承載板2〇具有一第 一表面2a及一相對之第二表面2b，第一表面2a設有複數金 _ 屬凸塊21，且金屬凸塊21具有與第一表面2a接著之第二端 2 lb及面向電極墊11之第一端2ia。 其中’本實施例之金屬凸塊21係為一外表面鍍有金屬 20 層211之銅塊。於本實施例中，鍍在金屬凸塊21外表面之金 屬層211係為一鎳層。 此外’如圖4A所示’承載板20可更包括一保護金屬層 22’係完全覆蓋承載板20之第一表面2a，且金屬凸塊21係 設於保護金屬層22之表面22a上。藉由此保護金屬層22可防 25 止後續製程破壞電子元件1。 22 201019437 再者，如圖4A所示，電子元件1可更包括複數金屬墊 13 ’係覆蓋電極墊11，且焊料凸塊31係藉由金屬墊13電性 連接電極墊11。於本實施例中，覆蓋電極墊11之金屬墊13， 係以焊料下凸塊之方式形成。 5 接下來’如圖2A所示，形成複數焊料凸塊31於電子元 件1及承載板20間，而焊料凸塊3 1係分別對應且電性連接電 極墊11與金屬凸塊21。在此，焊料凸塊31可先形成在金屬 凸塊21之第一端21a上，再與金屬凸塊21焊接；或者焊料凸 © 塊31可先形成在金屬墊13上，再與金屬凸塊21焊接。於本 10 實施例中’焊料凸塊31係先形成在金屬墊13上，再與金屬 凸塊21焊接’以形成一半導體裝置，如圖4B所示。 如圖4C所示，形成一核心板4，其包括一第一介電層 41’第一介電層41具有一第五表面41a及一第六表面41b， 而電子元件1係嵌埋於第一介電層41中。 15 此外’如圖4C所示，核心板4更包括一第二介電層43， 第二介電層43具有一第七表面43a及一第八表面43b，第二 Ο 介電層43之第八表面43b係與第一介電層41之第五表面41a 相結合’且第二介電層43係覆蓋電子元件1之非作用面la 移除該承載板20及保護金屬層22，及形成一嵌埋電子 20元件之封裝結構，如圖4D所示。在此，本實施例之嵌埋電 子元件之封裝結構，包括：一電子元件i，係具有相對之一 作用面ib、一非作用面la、及一保護層12，作用面讣具有 複數電極墊11，保護層12係覆蓋作用面lb，且保護層12具 有複數第一開孔121以使第一開孔121中之電極墊n不被保 23 201019437 5 ❹ 10 15 參 20 護層12所覆蓋；複數金屬凸塊2卜係具有第—端2u及相對 之第二端21b，且該等第一端2ia係面向該等電極墊u ;複 數焊料凸塊31，係設於電子元件丨之電極墊丨丨及金屬凸塊21 間，以電性連接電極墊n與金屬凸塊21 ;以及一核心板4, 其包括一第一介電層41，第一介電層41具有一第五表面41a 及一第六表面41b，而電子元件1係嵌埋於第一介電層41 中。此外，核心板4更包括一第二介電層43，而第二介電層 43係覆蓋電子元件1之非作用面la。 接著，如圖2E所示，於第二介電層43之第七表面43a 及第一介電層41之第六表面41b上，分別形成金屬層51， 51’，以用於圖案化形成線路層。 此外，如圖4E’所示，此為本實施例之另一實施態樣， 其中，核心板4除有第一介電層41及第二介電層43外，更包 括一核心層42，其中，核心層42係位於第一介電層41與第 二介電層43之間。 接下來’如圖4F所示，形成複數導電通孔45、及二第 一線路層51b，51a’其中，導電通孔45係貫穿核心層42、第 一介電層41、及第二介電層43,以電性連接第一線路層51b， 51a’且第一線路層51b, 51 a係分別設於第一介電層41之第 六表面41b及該第二介電層43之第七表面43a。 最後’如圖4G所示，於核心板4之第一介電層41之第 六表面41b、第二介電層43之第七表面43a、及第一線路層 51 b，51 a上’分別形成二第一增層結構6b，6a，其中各第一 增層結構6b, 6a具有至少一第三介電層61、至少一疊置於第 24 201019437 201019437 15 ❹ 20 二介電層61上之第二線路層62、及複數電性連接第一線路 層51b，51a與第二線路層62之導電盲孔63。 此外，各第一增層結構6a，讣分別具有_防焊層％ 7b’而防焊層7a, 7b具有複數開孔7()，以顯露電性連^塾 64 ’如圖4G所示。 綜上所述，利用本發明製法所製得之嵌埋電子元件之 封裝結構，利用覆蓋於電子元件電極塾上之金屬塾和承載 板上之金屬凸塊，透過焊料凸塊之連接，可提高自我對位 10 玄並提升對位精準度。同時，不需經過雷射燒灼形 成導電盲孔，即可使電子元件與增層結構之線路層電性連 接。另一方面’由於本發明是先進 核心板及增層結構，故可大面積的進行對位，節崔立封= 板之製作成本，更能提升封裝基板之量產能力。此外，^ 之Γ電子元件之封裝結構，因電子元件的對位精ί =，更：避免增層加工時產生對位偏移的問 產品之品質及良率。 穴开 上述實施例僅係為了方便說明而舉例而已，本發 主張之權利範圍自應以申請專利範圍所述為準， 於上述實施例。 僅限 【圖式簡單說明】 圓1Α至圖1C係習知之嵌埋電 程剖視圖。 子元件之封裝結構之製作流 25 201019437 圖2A至圖2G係本發明實施例1之嵌埋電子元件之封裝結 之製作流程剖視圖。 圖3A至圖3D’係本發明實施例2之嵌埋電子元件之封袭妙 構之製作流程剖視圖。 5 圖4 A至圖4G係本發明實施例3之嵌埋電子元件之封裝結構 之製作流程剖視圖。In addition, the present invention also provides a method for manufacturing a package structure of a buried electronic component, comprising the following steps: A) providing an electronic component and a carrier board, wherein the electronic component has a relative-active surface, a non-active surface, and a The protective layer has a plurality of electrode pads, the protective layer is disposed on the active surface, and the protective layer has a plurality of first-opening holes such that the electrode pads in the first opening are not covered by the protective layer. The carrier plate has a first surface and an opposite second surface. The first surface is provided with a plurality of metal bumps, and the metal bumps have a second end adjacent to the first surface and face the electrodes a first end; (B) forming a plurality of solder bumps between the electronic component and the carrier plate, the material bumps (4) corresponding to and electrically connecting the electrodes and the metal bumps; (C) < forming a core board comprising a core layer and a first dielectric layer, the core layer having a third surface, a fourth surface, and a through opening, the first dielectric layer having a fifth surface and a sixth surface, the fourth surface of the core layer A first table of the fifth dielectric layer surface binding, and the electronic components disposed in the system through the opening; and (D) in addition to shifting the carrier plate. In an embodiment of the present invention, after the step (D), the method further includes a step (D1): the sixth surface of the first dielectric layer and the metal bumps 20 201019437 5 参 10 15 Φ On the second end of 20, a first circuit layer is formed. In addition, in the embodiment, after the step (D1), the method further includes a step (D2) of forming at least one first on the sixth surface of the first dielectric layer and the first circuit layer. The build-up structure </ RTI> wherein the first build-up structure has at least one third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrically connected to the first circuit layer Conductive blind hole of the second circuit layer. In another embodiment of the present invention, the core board in the step (D) further includes a second dielectric layer, the second dielectric layer having a seventh surface and an eighth surface, the The eighth surface of the second dielectric layer is combined with the third surface of the core layer to "make the core layer between the first dielectric layer and the second dielectric layer" and the second dielectric layer Covering the non-active surface of the electronic component. In the embodiment, after the step (m), the method further includes a step (D1′): forming a plurality of conductive vias and two first circuit layers, wherein the conductive vias penetrate the core layer, the first The dielectric layer and the second dielectric layer are electrically connected to the first circuit layer, and the first circuit layers are respectively disposed on the sixth surface of the first dielectric layer and the second dielectric layer The seventh surface of the electrical layer. In the embodiment, after the step (m), the method further includes a step of the sixth surface of the first dielectric layer of the core board and the seventh surface of the second dielectric layer. And the layer-layer layer respectively have a build-up structure, wherein each of the first-growth layer structures has at least a first circuit layer disposed on the third dielectric layer, and a plurality of layers The conductive layer is connected to the conductive layer blind hole of the first circuit layer and the second circuit layer. 12 201019437 The method of construction, including: 步: step: 另: another: embedded electronic component package junction 10 r where the electronic component has a relative action surface, a: = carrier:: protective layer 'the active surface has a plurality Electrode pad: wherein the protective layer has a plurality of first openings to enable the layer 之 of the electrodes 塾 not covered by the protective layer, the carrier plate having a first surface and an opposite first surface The first surface is provided with a plurality of metal bumps, and the metal bumps have a second end adjacent to the first surface and a first end facing the electrode pad; (B) forming a plurality of solder bumps on the electronic component and Between the carrier plates, the solder bumps respectively correspond to and electrically connect the electrodes and the metal bumps; (C) form a core plate, which includes a first dielectric layer, the first dielectric The layer has a fifth surface and a sixth surface, and the electronic component is embedded in the first dielectric layer; and (D) the carrier is removed. In a further embodiment of the present invention, after the step (D), the method further includes a step (D1): the sixth surface of the first dielectric layer and the metal tendons A second circuit layer is formed on the second end of the block. In addition, in the embodiment, the step (D1) may further include a step (D2) of forming at least one first buildup layer on the sixth surface of the first dielectric layer and the first circuit layer. The junction structure has a structure of at least one third dielectric layer, at least one second wiring layer stacked on the third dielectric layer, and a plurality of electrically connected to the first circuit layer 5 a conductive blind hole of the second circuit layer. In another aspect of the present invention, the core board in the step (D) further includes a second dielectric layer having a seventh 13 201019437 surface and a first After the eight surfaces -> V ¢ 33⁄4 c? the eighth surface of the first " electrical layer is combined with the fifth surface of the first: and the second dielectric layer covers the 5 Φ 10 15 ❹ may further include - step (9),): forming a plurality of conductive vias, and a plurality of conductive vias extending through the first dielectric layer and the second "electric layer; The first circuit layers are electrically connected, and the first lines are disposed on the sixth surface of the first dielectric layer and the seventh surface of the second dielectric layer. Meanwhile, in this embodiment, the step (m,) includes a step (D2′): the sixth surface of the first dielectric layer of the core board, and the seventh surface of the second dielectric layer a surface of the first circuit layer and a first two-layered structure, wherein each of the first build-up structures has a first dielectric layer, at least one of which is stacked on the third dielectric layer The second circuit layer and the plurality of conductive blind holes electrically connected to the first circuit layer and the second line. In the above package structure of the semiconductor device and the embedded electronic component, the carrier plate further includes a protective metal layer completely covering the first surface of the carrier plate and the metal bumps are disposed on the protective metal layer On the surface. Meanwhile, in the above-described package structure of the semiconductor device and the embedded electronic component, the electronic component may further include a plurality of metal pads covering the electrodes, and the semiconductor bumps are electrically connected by the metal pads Connect the electrodes. Further, the material of the metal pad 13 may be selected from the group consisting of solder, silver gold, nickel/gold, nickel/palladium/gold, and combinations thereof, respectively. Furthermore, in the above-described package arrangement of the semiconductor device and the embedded electronic component, in the step (B), the solder bumps may be formed in the metal bumps 20 201019437 5 e 10 15 20 On the end, it is welded to the metal bump. Alternatively, in the step (8), the solder bumps are first formed on the metal crucibles and then soldered. In addition, in the package structure of the semiconductor device and the embedded electronic component described in the above, the material of the metal bump may be selected from the group consisting of solder, copper, silver, gold, gold/gold, nickel/palladium/gold, and combinations thereof, respectively. One of the group groups. In conventional packaging structures for embedded electronic components, the build-up structure is subjected to laser cauterization to electrically connect the electrodes of the respective electronic components to the electrical connections. However, the position where the electronic component is placed often causes an error in the electrical connection of the electrode pads. On the contrary, the semiconductor device of the present invention embeds the electronic component package structure and the method for manufacturing the same, and firstly uses the metal bump (which can be used as an electrical connection pad) and the electronic component to cover the metal pad on the electrode pad to be aligned. The bumps of the material are connected to the metal bumps and the electronic components, thereby achieving the effect of improving the alignment accuracy. Therefore, by using the semiconductor device of the present invention, the package structure of the buried electronic component, and the manufacturing method thereof, the laser burning can be reduced by one time, that is, the laser pad is not formed, and the electrode pad of the electronic component is electrically connected to the electrical connection pad. The conductive blind hole not only avoids damage to the electronic components, but also improves the accuracy of the alignment. The electrical connection of all the wafers on the entire surface of the substrate can be simultaneously performed in one alignment: the fabrication only needs to be aligned once. At the same time, the package structure is improved: the two processes are designed to meet the efficiency of mass production' and are easier to apply in the packaging structure of large-area and multi-electronic components. The present invention is described in the following by means of specific embodiments thereof, and those skilled in the art can readily appreciate other advantages and advantages of the present invention from the disclosure herein. The present invention may also be implemented or applied by other different embodiments, and the details of the present application are also 5 ❹ 10 15 ❹ 20 Various modifications may be made without departing from the spirit of the present invention based on different viewpoints and applications. With changes. Embodiment 1 Please refer to FIG. 2A to FIG. 2G, which are cross-sectional views showing the manufacturing process of the package structure of the embedded electronic component of the present embodiment. As shown in Figure 2A, first provide an electronic component! And a carrier board 2, wherein the electronic component 1 has a pair of active surfaces lb, an inactive surface ia, and a protective layer 12'. The active surface ib has a plurality of electrode pads, and the protective layer 12 is disposed on the active surface lb to protect The layer 12 has a plurality of first openings 121 such that the electrode pads 11 of the first openings 121 are not covered by the protective layer 12. The carrier plate 2 has a first surface 2a and an opposite second surface 2b. The surface 2a is provided with a plurality of metal blocks 21' and the metal bumps 21 have a second end 21b followed by the first surface 2a and a first end 2ia facing the electrode pad 11. Further, the carrier plate 20 as shown in Fig. 2A may further include a protective metal layer 22' which completely covers the first surface 2a of the carrier plate 2, and the metal bumps 21 are provided on the surface 22a of the protective metal layer 22. By thus protecting the metal layer 22, the subsequent process can be prevented from damaging the electronic component 1. Further, as shown in FIG. 2A, the electronic component 1 may further include a plurality of metal pads 13, which cover the electrode pads u, and the solder bumps 31 are electrically connected to the electrode pads 11 by the metal pads 13. The material of the metal pad 13 may be selected from the group consisting of solder, 16 201019437 silver, gold, nickel/gold, nickel/pump/gold, and combinations thereof, respectively. In addition, the metal crucible 13 can be under bump metal (UBM), Electroless Ni & Immersion Gold (ENIG), electroless nickel & electroless palladium & 5 immersion Gold, ENEPIG) and other forms. In the present embodiment, the metal pad 13 covering the electrode pad 11 is formed by solder bumps. On the other hand, the material of the metal bumps 21 may be selected from one of the group consisting of solder, copper, silver, gold, gold/gold, recording/gold/gold, and combinations thereof. The metal bump 21 may be a copper block, a copper block having an electrical connection pad, or a copper block with a metal layer (Ni/Au or Ni/Pd/Au) bonded to the outer surface. In the present embodiment, the metal bumps 2 1 are a copper block. Further, the metal bumps 21 may be a rectangular parallelepiped, a cylinder, or a trapezoidal. In this embodiment, the metal bump 21 is a cylinder. In addition, as shown in FIG. 2A', this is another embodiment of the present invention. In the fifteenth, the metal pad 13 covering the electrode pad 11 of the electronic component 1 is formed by electroless nickel-plated palladium immersion gold, and is disposed on The metal bumps 21 on the carrier board 20 further have a φ electrical connection pad 21'. Next, as shown in FIG. 2A, a plurality of solder bumps 31 are formed between the electronic component 1 and the carrier 20, and the solder bumps 31 are electrically connected to the electrical pads 21 and the metal bumps 21, respectively. Here, the solder bumps 31 may be first formed on the first end 21a of the metal bumps 21 and then soldered to the metal bumps 21; or the solder bumps 31 may be formed on the metal pads 13 first, and then with the metal bumps 21 welding. In the present embodiment, the solder bumps 31 are first formed on the first ends 21a 17 201019437 of the metal bumps 21 and then soldered to the metal bumps 21 to form a semiconductor device, as shown in FIG. 2B. Therefore, the semiconductor device prepared in the present embodiment, as shown in FIG. 2B, comprises: an electronic component 1 having a functioning surface, a non-face 5, and a protective layer 12'. The lb has a plurality of electrode pads, the protective layer 12 is disposed on the active surface lb, and the protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first openings 121 are not covered by the protective layer 12; The carrier plate 20' has a first surface 2a and an opposite second surface 2b. The first surface 2a is provided with a plurality of metal bumps 21'. The metal bumps 21 have a second end adjacent to the first surface 10a. 21b and the first end 21a facing the electrode pad 11 and the plurality of solder bumps 31 are disposed between the electrode pad 11 and the metal bump 21 to electrically connect the electrode pad 11 and the metal bump 21. Next, as shown in FIG. 2C, a core board 4 is formed, which includes a core layer 42 and a first dielectric layer 41. The core layer 42 has a third surface 42a, a 15 fourth surface 42b, and a through layer. The opening 420, the first dielectric layer 41 has a fifth surface 41a and a sixth surface 41b, and the fourth surface 42b of the core layer 42 is combined with the fifth surface 41a of the first dielectric layer 41, and the electrons The element 1 is disposed within the through opening 420. In addition, as shown in FIG. 2C, the core board 4 further includes a second dielectric layer 43, 20, the second dielectric layer 43 has a seventh surface 43a and an eighth surface 43b, and the second dielectric layer 43 The eighth surface 43b is combined with the third surface 42a of the core layer 42. The core layer 42 is disposed between the first dielectric layer 41 and the second dielectric layer 43, and the second dielectric layer 43 covers the electronic component 1. Non-active surface la. 18 201019437 wherein the core sheet 4 can be formed by conventional methods such as pressing, vacuum bonding, coating, or printing. In addition, the materials of the first dielectric layer 41 and the second dielectric layer 43 may be commonly used organic dielectric materials, such as: ABF (Ajinomoto Build-up Film), double-butadiene brewed acid Amine/Bismaleimide triazine (BT), benzocylobutene (BCB), Liquid Crystal Polymer, Polyimide (PI), Poly (phenylene) Ether)), photographic or non-photosensitive organic resins such as poly 10 (tetra-fluoroethylene), aromatic polyamide (Aramide), epoxy resin or glass fiber, or mixed epoxy resin and glass fiber And other materials. In addition, the dielectric material of the first dielectric layer 41 or the second dielectric layer 43 may be filled in the gap 44 between the core layer 42 and the opening 421 and the wafer 1. The gap 410 between the electrical connection structures 3 may be filled with a dielectric material, partially filled with a dielectric material filled with the first dielectric layer 41, or completely filled with a dielectric material of the first dielectric layer 41. occur. φ Next, as shown in Fig. 2D, the carrier board 20 is removed. Further, when the carrier plate 20 is removed, the protective metal layer 22 can also be removed at the same time. The gap 410 between the electrical connection structures 3 is not filled with any dielectric material. Alternatively, as shown in Fig. 2D'20, the gap 410 between the electrical connection structures 3 is completely filled with the dielectric material of the first dielectric layer 41. Next, as shown in FIG. 2E, metal layers 51, 51' are formed on the seventh surface 43a of the second dielectric layer 43 and the sixth surface 41b of the first dielectric layer 41, respectively, for patterning to form lines. Floor. 19201019437, as shown in FIG. 2F, a plurality of conductive vias 45 and two first wiring layers 51b, 51a are formed, wherein the conductive vias 45 extend through the core layer 42, the first dielectric layer 41, and the second dielectric layer. The first circuit layer 51a, 51b is electrically connected to the sixth surface 51bb of the first dielectric layer 41 and the seventh surface of the second dielectric layer 43 respectively. 43a. Next, as shown in FIG. 2G, the sixth surface 41b of the first dielectric layer 41 of the core board 4, the seventh surface 43a of the second dielectric layer 43, and the first wiring layers 51b, 5la are respectively Forming two first build-up structures 6b, 6a, wherein each of the second build-up structures 6b, 6& has at least a third dielectric layer 61, at least one second line stacked on the 10 second dielectric layer 61 The layer 62 and the plurality of conductive blind vias 63 electrically connected to the first circuit layers 51 b, 51 a and the second circuit layer 62 . Further, each of the first build-up structures 6a, 6b has a solder resist layer 7a, 7b', respectively, and the solder resist layers 7a, 7b have a plurality of openings 7A to expose the electrical connection pads 64, as shown in Fig. 2G. 15 Embodiment 2 φ - Method and embodiment of the semiconductor device of the present embodiment! Similarly, the metal pad 13 covering the electron 7G piece 1 electrode pad 1 is formed by electroless nickel-palladium immersion gold as shown in Fig. 3A. Then, a core board 4 is formed, which includes a 20 core layer 42 and a first dielectric layer 41, and a gap between the through opening 421 of the core layer 42 and the wafer 1 is filled with the first dielectric layer 41. Dielectric material. Next, as shown in FIG. 3B, after the carrier board 2 and the protective metal layer 22 are removed, a package structure in which electronic components are embedded is formed. The package structure of the embedded electronic 7L device of the embodiment comprises: an electronic component 丨 having a relatively active surface 1b, an inactive surface la, and a protective layer 12, the active surface lb 20 201019437 having a plurality of electrodes The pad 11, the protective layer 12 covers the active surface lb, and the protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first opening 121 are not covered by the protective layer 12; the plurality of metal bumps 21, The first end 2u and the opposite end 2ib are disposed, and the first end 2ia faces the electrode pad 5 U; the plurality of solder bumps 31 are disposed on the electrode pad and the metal bump of the electronic component Between the blocks 21, the electrode pads u and the metal bumps 21 are electrically connected; and a core plate 4' includes a core layer 42 and a first dielectric layer 41. The core layer has a second surface 42a and a first layer. The fourth surface 42b and a through opening 420, the first dielectric layer 41 has a fifth surface 41a and a sixth surface 4lb, and the fourth surface 42b of the core layer 〇42 is connected to the first dielectric layer 41. The fifth surface 41a is combined with 'the electronic component 1 is disposed within the through opening 420. Next, as shown in FIG. 3C, a first wiring layer 51b is formed on the sixth surface of the first dielectric layer 41 and the second end 21b of the metal bump 21. The first circuit layer 51b is disposed on the sixth surface 41b 15 of the first dielectric layer 41 and electrically connected to the second end 21b of the metal bump 21. As shown in FIG. 3D, at least a first build-up structure 6b is formed on the sixth surface 4 lb of the first dielectric layer 41 and the first germanium circuit layer 51b, wherein the first build-up structure 6b has at least a third The dielectric layer 61, the second circuit layer 62 disposed on the third dielectric layer 61, and the conductive vias 63 electrically connected to the first circuit layers 5 lb and 20 of the second circuit layer 62. Further, the first build-up structure 6b further has a solder resist layer 7b, and the solder resist layer 7b has a plurality of openings 70 to expose the electrical connection pads 64, as shown in Fig. 3D. On the other hand, the package structure of the buried electronic component after this embodiment can be further double-layered as shown in Fig. 3D'. On the third surface 42a 21 201019437 of the core layer 42 and the electronic component i inactive Sla, at least one first build-up structure 6a is further formed, wherein the first build-up structure 6a has at least a third dielectric (four), at least - The second circuit layer 62 stacked on the third dielectric layer 61 and the conductive blind vias 63 electrically connected to the second wiring layer 51b and the second wiring layer 62. The first build-up structure 6a further has a solder resist layer 7a' and the solder resist layer has a plurality of openings 70 to expose the electrical connection pads 64. Embodiment 3 > Referring to FIG. 4A to FIG. 4G, a cross-sectional view showing the manufacturing process of the package structure of the embedded electronic component of the present embodiment is shown. First, as shown in FIG. 4A, an electronic component 丨 and a carrier board 2 are provided, wherein the electronic component 1 has a pair of active surfaces lb, an inactive surface la, and a protective layer 12, and the active surface lb has a plurality of electrodes. The protective layer 12 is disposed on the active surface lb. The protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first openings 15 121 are not covered by the protective layer 12. The carrier board 2 has a first a surface 2a and an opposite second surface 2b, the first surface 2a is provided with a plurality of gold-like bumps 21, and the metal bumps 21 have a second end 2 lb followed by the first surface 2a and a surface facing the electrode pads 11 One end 2ia. The metal bump 21 of the present embodiment is a copper block whose outer surface is plated with a metal 20 layer 211. In the present embodiment, the metal layer 211 plated on the outer surface of the metal bump 21 is a nickel layer. Further, the carrier board 20 may further include a protective metal layer 22' which completely covers the first surface 2a of the carrier board 20, and the metal bumps 21 are provided on the surface 22a of the protective metal layer 22. By thus protecting the metal layer 22, it is possible to prevent the subsequent process from damaging the electronic component 1. Further, as shown in FIG. 4A, the electronic component 1 may further include a plurality of metal pads 13 ′ covering the electrode pads 11 , and the solder bumps 31 are electrically connected to the electrode pads 11 by the metal pads 13 . In the present embodiment, the metal pad 13 covering the electrode pad 11 is formed by solder bumps. 5 Next, as shown in FIG. 2A, a plurality of solder bumps 31 are formed between the electronic component 1 and the carrier 20, and the solder bumps 31 are electrically connected to the electrode pads 11 and the metal bumps 21, respectively. Here, the solder bumps 31 may be formed on the first end 21a of the metal bump 21 and then soldered to the metal bumps 21; or the solder bumps 31 may be formed on the metal pads 13 first, and then with the metal bumps. 21 welding. In the present embodiment, the solder bumps 31 are first formed on the metal pad 13 and then soldered to the metal bumps 21 to form a semiconductor device as shown in Fig. 4B. As shown in FIG. 4C, a core board 4 is formed, which includes a first dielectric layer 41'. The first dielectric layer 41 has a fifth surface 41a and a sixth surface 41b, and the electronic component 1 is embedded in the first layer. In a dielectric layer 41. Further, as shown in FIG. 4C, the core board 4 further includes a second dielectric layer 43 having a seventh surface 43a and an eighth surface 43b, and a second dielectric layer 43. The eighth surface 43b is combined with the fifth surface 41a of the first dielectric layer 41 and the second dielectric layer 43 covers the inactive surface 1 of the electronic component 1 to remove the carrier 20 and the protective metal layer 22, and form A package structure in which an electronic component 20 is embedded, as shown in FIG. 4D. Here, the package structure of the embedded electronic component of the embodiment includes: an electronic component i having a pair of active surfaces ib, a non-active surface la, and a protective layer 12 having a plurality of electrode pads 11. The protective layer 12 covers the active surface lb, and the protective layer 12 has a plurality of first openings 121 so that the electrode pads n in the first opening 121 are not covered by the cover layer 12 201019437 5 ❹ 10 15 The plurality of metal bumps 2 have a first end 2u and an opposite second end 21b, and the first end 2ia faces the electrode pad u; the plurality of solder bumps 31 are disposed on the electrode of the electronic component Between the pad and the metal bump 21, the electrode pad n and the metal bump 21 are electrically connected; and a core plate 4 including a first dielectric layer 41, the first dielectric layer 41 having a fifth surface 41a and a sixth surface 41b, and the electronic component 1 is embedded in the first dielectric layer 41. In addition, the core board 4 further includes a second dielectric layer 43, and the second dielectric layer 43 covers the inactive surface la of the electronic component 1. Next, as shown in FIG. 2E, metal layers 51, 51' are formed on the seventh surface 43a of the second dielectric layer 43 and the sixth surface 41b of the first dielectric layer 41, respectively, for patterning to form lines. Floor. In addition, as shown in FIG. 4E′, this is another embodiment of the embodiment, wherein the core board 4 includes a core layer 42 in addition to the first dielectric layer 41 and the second dielectric layer 43. The core layer 42 is located between the first dielectric layer 41 and the second dielectric layer 43. Next, as shown in FIG. 4F, a plurality of conductive vias 45 and two first wiring layers 51b, 51a' are formed, wherein the conductive vias 45 extend through the core layer 42, the first dielectric layer 41, and the second dielectric. The layer 43 is electrically connected to the first circuit layer 51b, 51a' and the first circuit layers 51b, 51a are respectively disposed on the sixth surface 41b of the first dielectric layer 41 and the seventh of the second dielectric layer 43 Surface 43a. Finally, as shown in FIG. 4G, the sixth surface 41b of the first dielectric layer 41 of the core board 4, the seventh surface 43a of the second dielectric layer 43, and the first circuit layer 51b, 51a respectively Forming two first build-up structures 6b, 6a, wherein each of the first build-up structures 6b, 6a has at least one third dielectric layer 61, at least one of which is placed on the second dielectric layer 61 of the 24th 201019437 201019437 15 ❹ 20 The second circuit layer 62 and the plurality of conductive blind holes 63 electrically connected to the first circuit layers 51b, 51a and the second circuit layer 62. Further, each of the first build-up structures 6a, 讣 has a _ solder resist layer % 7b', and the solder resist layers 7a, 7b have a plurality of openings 7 () to expose an electrical connection 64' as shown in Fig. 4G. In summary, the package structure of the embedded electronic component obtained by the method of the present invention can be improved by connecting the metal bumps on the electrode pads of the electronic component and the metal bumps on the carrier board through the solder bumps. Self-alignment 10 Xuan and improve alignment accuracy. At the same time, the electronic component can be electrically connected to the wiring layer of the build-up structure without laser bumping to form a conductive blind hole. On the other hand, since the present invention is an advanced core board and a build-up structure, it can be aligned in a large area, and the production cost of the board is improved, and the mass production capability of the package substrate can be improved. In addition, the package structure of the electronic components is due to the alignment of the electronic components, and the quality and yield of the products that avoid the offset during the layering process. The above embodiments are merely examples for the convenience of the description, and the scope of the claims is based on the above-mentioned embodiments. [Simplified description of the drawing] The circle 1Α to Fig. 1C is a conventional embedded circuit sectional view. Flow of the package structure of the sub-element 25 201019437 Fig. 2A to Fig. 2G are cross-sectional views showing the fabrication process of the package junction of the embedded electronic component of the first embodiment of the present invention. 3A to 3D are cross-sectional views showing a manufacturing process of the embedding structure of the embedded electronic component of the second embodiment of the present invention. 5A to 4G are cross-sectional views showing a manufacturing process of a package structure of an embedded electronic component according to Embodiment 3 of the present invention.
【主要元件符號說明】 1 電子元件 lb 作用面 12 保護層 13 金屬墊 2a 第一表面 21 金屬凸塊 21b 第二端 22 保護金屬層 3 電性連接結構 4 核心板 410 間隙 41b 第六表面 420 貫穿開口 42b 第四表面 43a 第七表面 44 間隙 la 非作用面 11 電極墊 121 第一開孔 20 承載板 2b 第二表面 21a 第一端 21， 電性連接墊 22a 表面 31 焊料凸塊 41 第一介電層 41a 第五表面 42 核心層 42a 第三表面 43 第二介電層 43b 第八表面 45 導電通孔 26 201019437 51，51， 金屬層 51a, 51b 第一線路層 6a, 6b 第一增層結構 60 介電層 61 第三介電層 62 第二線路層 63 導電盲孔 64 電性連接墊 7a, 7b 防焊層 70 開孔 參 27[Main component symbol description] 1 electronic component lb active surface 12 protective layer 13 metal pad 2a first surface 21 metal bump 21b second end 22 protective metal layer 3 electrical connection structure 4 core plate 410 gap 41b sixth surface 420 through Opening 42b fourth surface 43a seventh surface 44 gap la non-active surface 11 electrode pad 121 first opening 20 carrier plate 2b second surface 21a first end 21, electrical connection pad 22a surface 31 solder bump 41 first Electrical layer 41a fifth surface 42 core layer 42a third surface 43 second dielectric layer 43b eighth surface 45 conductive via 26 201019437 51, 51, metal layer 51a, 51b first wiring layer 6a, 6b first buildup structure 60 dielectric layer 61 third dielectric layer 62 second circuit layer 63 conductive blind hole 64 electrical connection pad 7a, 7b solder resist layer 70 open hole 27