201019400 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置’並且，特別關於一種半導體 裝置之製造方法，其能夠提高該半導體裝置中一通道區域之導電 度。 【先前技術】 一金氧半導體（MOS)電晶體中之通道區域之導電度透過— 閘極控制。也就是說’透過閘極控制一導電通道之電流驅動能力， 此閘極使用通道區域之上形成的一薄膜絕緣層與通道區域相絕 緣。 如果透過向此閘極作用一適當的控制電壓形成導電通道，則 通道區域之導電度隨一摻雜濃度，以及複數個電荷載子之移動性 變化。通道區域之導電度係為紋此金氧半導體（MOS)電晶體 一實際性能的主要因素。 如果一半導體裝置之尺寸變為逐漸減小，則- P型金氧半導❹ 體（PMOS)中之載子’即電洞的移紐減少，使得不可能獲得， 期望之汲極電流。 【發明内容】 法。 因此’繁於上_題’本發明關於—種半導财置之製造方 在於提供一種半導體裝置之製造方法，其 能夠提高半導體裝置中-通道區域之導電度。 201019400 本發明其他的優點、目的、以及特徵將在如下的說明書中部 分地加以闡述，並且本發明其他的優點、目的和特徵對於本領域 的普通技術人員來說，可以透過本發明如下的說明得以部分地理 解或者可以從本發明的實踐中得出。本發明的目的和其他優點可 以透過本發明所記載的說明書和申請專利範圍中特別指明的結構 並結合圖式部份，得以實現和獲得。 為了獲得本發明之目的的這些目的及其他優點，現對本發明 〇 作具體化和概括性的描述，本發明的一種半導體裝置之製造方法 包含以下步驟：相繼形成一第一氧化膜、一氮化膜、以及一第二 氧化膜於一半導體基板之上，蝕刻第二氧化膜及氮化膜用以形成 一第二氧化膜圖案及一氮化膜圖案，用以暴露第一氧化膜之一部 份，至少執行一次氮植入，用以在半導體基板中於暴露的第一氧 化膜之下形成一氮注入區，形成一第三氧化膜於半導體基板之一 表面之上，其中此半導體基板具有第二氧化膜圖案及第二氧化膜 ❹圖案之上形成的氮化膜圖案，蝕刻具有第三氧化膜的半導體基板 用以形成-穿過氮離子注人區的溝道，以及填充-氧化膜於此溝 道中用以形成一裝置絕緣膜。 在本發明之另一方面中，一種半導體裝置之製造方法包含以 下步驟：形成-第-絕緣麵案於一半導體基板之上，透過使用 第-絕緣膜圖案作為光罩對半導體基板之一部份至少執行一次氣 植入，用以形成一氮注入區，形成一第二絕緣膜於第一絕緣膜圖 案之側壁之上，對其上形成有第—絕緣膜圖案及第二絕緣膜之半 5 201019400 導體基板執行-各向同性侧，用以形成一穿過氮注入區的溝 道’以及填充—氧化膜於此溝道中用以形成-裝置絕緣區。 可以理解的是’如上所述的本發明之概括說明和隨後所述的 本發明之詳細朗均是具有代表性和解釋性的說明 ，並且是為了 進一步揭示本發明之申請專利範圍。 【實施方式】 以下’將結合圖式部份對本發明的具體實施例作詳細說明。 其中在這些圖式部份中所使用的相同的參考標號代表相同或同類❹ 部件。 「第1圖」至「第7圖」係為本發明的一種半導體裝置之製 造方法之步驟之剖視圖。。 請參閱「第1圖」，一第一絕緣膜101形成於一半導體基板100 之上。舉例而言，第一絕緣膜101能夠為一氧化物_氮化物_氧化物 (Oxide-Nitride-Oxide，ΟΝΟ )層’該氧化物-氮化物氧化物（ΟΝΟ ) 層具有相繼堆疊於半導體基板100上的一第一氧化膜110、一氮化 ❹ 膜115、以及一第二氧化膜120。 此種情況下，第一氧化膜110能夠具有一 40埃（□)至50 埃（□)之厚度，並且第二氧化膜120能夠具有一 1〇〇〇 (□)埃至 1500埃（□)之厚度。也就是說，第二氧化膜120具有之厚度相 比較於第一氧化膜110更厚。 然後，請參閱「第2圖」’一光阻抗蝕圖案125透過光微影技 術形成於第二氧化膜120之上，用以形成一裝置絕緣膜。然後， 201019400 透過使用光阻抗姓圖案125作為一光罩，相繼蝕刻第二氧化膜12〇 及氮化膜115以保留第一氧化膜110之一部份。 請參閱「第3 ®」’執行灰化或_践去除細抗侧案 125。 然後，透過使用蝕刻的第二氧化膜（以下稱作一第二氧化膜 圖案120-1)及氮化膜（以下稱作一氮化膜圖案1151)作為一光 罩至少執行一次植入，用以通過第一氧化膜11〇之暴露部份將氮 ❹植入於半導體基板1⑻中。利用氮植入，一氮注入區130在半導 體基板100中形成於第一氧化膜110之下。 舉例而言，氮植入可透過兩個步驟進行。在第一步驟中，在 劑量為1E15〜2E15原子/平方公分（at〇ms/cm2 )且能量為 10〜15KeV之條件下植入氮。在第二步驟中，在劑量為mi5〜2Ei5 原子/平方公分（atoms/cm2 )且能量為2〇〜25KeV之條件下植入 氮。也就是說，雖然在第一步驟與第二步驟中劑量相同，但第二 ® 步驟中之能量相比較於第一步驟更高。 透過逐漸增加氮注入能量執行複數次氮植入用以形成一較大 的氮注入區130。如此形成的較大氮注入區13〇使得作用於半導體 基板100之活性區的壓應力更大，並且該較大的壓應力可提高在 該活性區形成的通道區域之導電度。也就是說，壓應力能夠增加 一 P型金氧半導體（PMOS)中的載子，即電洞之移動性。 請參閱「第4圖」，一第三氧化膜135，例如四乙氧基矽烷 (TetraEthOxySilane,TEOS)沉積於半導體基板100之一表面上， 7 201019400 其中半導體基板100之上形成有第二氧化膜圖案120-1及氮化膜圖 案 115-1 。 請參閱「第5圖」，透過使用活性離子餘刻，對其上沉積有第 二氧化膜135的半導體基板1〇〇執行各向同性姓刻。由於第二氧 化膜圖案120-1具有一相比較於第一氧化膜11〇更厚之厚度，並且 該半導體基板相比較於第二氧化膜圖案120-1具有更大之姓刻速 率，因此一溝道透過各向同性蚀刻形成於半導體基板100中，該 溝道通過氮注入區130。此種情況下’各向同性餘刻在第二氧化膜 ❹ 圖案120-1及氮化膜圖案115-1之侧壁上形成一剩留第三氧化膜 135-卜 半導體基板100中保留的氮注入區之一邊緣區域130-1鄰近溝 道137之頂邊緣。也就是說’如「第4圖」所示，氮注入區no 之邊緣區域130-1與剩留的第三氧化膜135相對應，並且鄰近於溝 道137之頂邊緣形成於半導體基板1〇〇之中。這是因為在氮注入 時，第三氧化膜135可減少暴露的一半導體基板之面積。 ❹ 然後，請參閱「第5圖」，由於在蝕刻該半導體基板時，與氮 注入區130之邊緣區域130-1相對應的剩留第三氧化膜135-1作為 一蝕刻屏障，因此甚至在活性離子蝕刻之後，氮注入區13〇之邊 緣區域130-1能夠鄰近於溝道137之頂邊緣保留於半導體基板100 中。也就是說，「第5圖」所示之暴露於溝道的半導體基板之寬度 相比較於「第3圖」所示之氮注入時暴露的半導體基板之寬度為 201019400 請參閱「第6圖」，一第四氧化膜140形成於半導體基板100 之上用以使用該氧化膜填充溝道137。 請參閱「第7圖」，執行一化學機械研磨（Chemical Mechanical Polishing, CMP)用以平整第四氧化膜140以形成一裝置絕緣膜 150。裝置絕緣膜150將半導體基板100劃分為一裝置絕緣區及一 活性區。 在半導體基板100中形成的鄰近於裝置絕緣膜150之頂邊緣 ❹ 的氮注入區130之邊緣區域130-1將壓應力作用至半導體基板1〇〇 之活性區，並且如此作用的該壓應力提高在活性區中形成的一通 道區域之導電度。也就是說，如此作用的該壓應力能夠提高p型 金氧半導體（PMOS)中的載子，即電洞之移動性。由於作用於通 道區域的該壓應力可提高電洞之移動性，因此壓應力能夠提高一 p 型電晶體之性能。 而且，在形成氮注入區的植入期間，透過利用氮劑量及能量 β控騎道區域之導電度（例如，電敗移動性），能夠容祕得一 期望的沒極電流。 而且，由於氮離子僅注入於裝置絕緣區及活性區中形成相接 觸的源極及沒極之-部份，因此氮離子注入不影響該源極及沒極 以及通道區域。 以下將描述本發明之另一較佳實施例之一半導體裝置之製造 方法’該半導體裝置之製造方法與結合「第1圖」至「第7圖」 所描述之製造方法不相同。 9 201019400 一第一氧化膜、一氮化膜、以及一第二氧化膜相繼形成於一 半導體基板之上。然後，相繼蝕刻第二氧化膜、氮化膜、以及第 一氧化膜，用以形成一暴露半導體基板之一部份的第一絕緣膜圖 案。雖然「第2圖」中顯示未蝕刻第一氧化膜110，然而在本發明 之另一較佳實施例之半導體裝置之製造方法中，蝕刻該第二氧化 膜以暴露半導體基板。 透過使用第一絕緣膜圖案作為一光罩，能夠至少執行一次植 入用以將氮植入於半導體基板100之一暴露部份。可利用前述之 一方法實現氮植入。 然後’一例如四乙氧基石夕烧（TEOS )的第二絕緣膜形成於第 一絕緣膜圖案之側壁上。此種情況下’第二絕緣膜覆蓋氮注入區 之邊緣區域。具有第一絕緣膜圖案及第二絕緣膜的該半導體基板 進行各向同性蝕刻，用以形成一穿過氮注入區的溝道，其中第二 絕緣膜形成於第一絕緣膜圖案之上。此種情況下，氮注入區之邊 緣區域相鄰於溝道之頂部相對之邊緣保留於半導體基板中。然 後’一氧化膜填充於溝道中以形成一裝置絕緣區。 如上所述，本發明之一半導體裝置之製造方法具有以下之優 點。 由於鄰近魏置絕賴之頂邊緣的轉體基板巾形成的氮注 入區將壓應力_於半導體基板之活性區，因此該活性區中形成 的通道區域具有提高的導電度。 本領域之技術人員應當意識到在不脫離本發明所附之申請專 201019400 利h圍所揭tf之本發明之精神和細的情況下，所作之更動與潤 飾屬本發月之專利保護範圍之内。關於本發明所界定之 範圍請參照所附之申請專利範圍。 【圖式簡單說明】 第1圖至第7圖係為本發明的一種半導體裝置之製造方法之 步驟之剖視圖。 【主要元件符號說明】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a method of fabricating a semiconductor device capable of improving the conductivity of a channel region in the semiconductor device. [Prior Art] The conductivity of a channel region in a metal oxide semiconductor (MOS) transistor is transmitted through a gate. That is to say, the current driving capability of a conductive path is controlled by the gate, and the gate electrode is insulated from the channel region by a thin film insulating layer formed over the channel region. If a conductive path is formed by applying an appropriate control voltage to the gate, the conductivity of the channel region varies with a doping concentration and the mobility of the plurality of charge carriers. The conductivity of the channel region is a major factor in the actual performance of the metal oxide semiconductor (MOS) transistor. If the size of a semiconductor device becomes gradually reduced, the carrier of the -P-type MOS transistor (PMOS), i.e., the movement of the hole, is reduced, making it impossible to obtain the desired drain current. SUMMARY OF INVENTION Therefore, the present invention relates to a method of manufacturing a semiconductor device capable of improving the conductivity of a channel region in a semiconductor device. Other advantages, objects, and features of the present invention will be set forth in part in the description which follows, and <RTIgt; Partially understood or can be derived from the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the <RTI In order to achieve the object and other advantages of the present invention, the present invention is embodied and described in detail. A method of fabricating a semiconductor device of the present invention comprises the steps of: sequentially forming a first oxide film, and nitriding. a film and a second oxide film on a semiconductor substrate, etching the second oxide film and the nitride film to form a second oxide film pattern and a nitride film pattern for exposing one of the first oxide films And performing at least one nitrogen implantation to form a nitrogen implantation region under the exposed first oxide film in the semiconductor substrate to form a third oxide film on a surface of the semiconductor substrate, wherein the semiconductor substrate has a second oxide film pattern and a nitride film pattern formed over the second oxide film pattern, etching a semiconductor substrate having a third oxide film to form a channel through the nitrogen ion implantation region, and a fill-oxide film In this channel, a device insulating film is formed. In another aspect of the invention, a method of fabricating a semiconductor device includes the steps of: forming a first-insulating surface on a semiconductor substrate by using a first insulating film pattern as a mask for a portion of the semiconductor substrate At least one gas implantation is performed to form a nitrogen implantation region, and a second insulating film is formed on the sidewall of the first insulating film pattern, and the first insulating film pattern and the second insulating film are formed thereon. The 201019400 conductor substrate performs an isotropic side for forming a channel through the nitrogen implantation region and a fill-oxide film for forming a device isolation region in the channel. It is to be understood that the foregoing general description of the invention and the claims [Embodiment] Hereinafter, specific embodiments of the present invention will be described in detail in conjunction with the drawings. The same reference numerals are used throughout the drawings to refer to the same or the like. The "Fig. 1" to "Fig. 7" are cross-sectional views showing the steps of a method of manufacturing a semiconductor device of the present invention. . Referring to FIG. 1, a first insulating film 101 is formed on a semiconductor substrate 100. For example, the first insulating film 101 can be an oxide-nitride-oxide layer (Oxide-Nitride-Oxide, ΟΝΟ) layer having the oxide-nitride oxide layer disposed successively on the semiconductor substrate 100. A first oxide film 110, a tantalum nitride film 115, and a second oxide film 120 are formed. In this case, the first oxide film 110 can have a thickness of 40 angstroms (□) to 50 angstroms (□), and the second oxide film 120 can have a thickness of 1 〇〇〇 (□) Å to 1500 Å (□). The thickness. That is, the second oxide film 120 has a thickness thicker than that of the first oxide film 110. Then, referring to "Fig. 2", a photoresist pattern 125 is formed on the second oxide film 120 by photolithography to form a device insulating film. Then, 201019400 sequentially etches the second oxide film 12A and the nitride film 115 to retain a portion of the first oxide film 110 by using the photo-resistance pattern 125 as a mask. Please refer to “3®” to perform the ashing or _practice removal of the side effect 125. Then, at least one implantation is performed by using the etched second oxide film (hereinafter referred to as a second oxide film pattern 120-1) and the nitride film (hereinafter referred to as a nitride film pattern 1151) as a mask. Nitrogen germanium is implanted into the semiconductor substrate 1 (8) through the exposed portion of the first oxide film 11 . A nitrogen implantation region 130 is formed under the first oxide film 110 in the semiconductor substrate 100 by nitrogen implantation. For example, nitrogen implantation can be performed in two steps. In the first step, nitrogen is implanted at a dose of 1E15 to 2E15 atoms/cm 2 (at 〇ms/cm 2 ) and an energy of 10 to 15 KeV. In the second step, nitrogen is implanted at a dose of mi 5 to 2 Ei 5 atoms/cm 2 (atoms/cm 2 ) and an energy of 2 〇 to 25 KeV. That is, although the dose is the same in the first step and the second step, the energy in the second step is higher than in the first step. A plurality of nitrogen implants are performed to gradually form a larger nitrogen implant region 130 by gradually increasing the nitrogen implant energy. The larger nitrogen implantation region 13 thus formed causes the compressive stress acting on the active region of the semiconductor substrate 100 to be larger, and the larger compressive stress can increase the conductivity of the channel region formed in the active region. That is, the compressive stress can increase the carrier in a P-type metal oxide semiconductor (PMOS), that is, the mobility of the hole. Referring to FIG. 4, a third oxide film 135, such as TetraEthOxySilane (TEOS), is deposited on one surface of the semiconductor substrate 100, 7 201019400, wherein a second oxide film is formed on the semiconductor substrate 100. Pattern 120-1 and nitride film pattern 115-1. Referring to Fig. 5, an isotropic surname is performed on the semiconductor substrate 1 on which the second oxide film 135 is deposited by using the active ion residue. Since the second oxide film pattern 120-1 has a thicker thickness than the first oxide film 11〇, and the semiconductor substrate has a larger surname rate than the second oxide film pattern 120-1, The channel is formed in the semiconductor substrate 100 by isotropic etching, and the channel passes through the nitrogen implantation region 130. In this case, the isotropic residue forms a remaining third oxide film 135 on the sidewalls of the second oxide film pattern 120-1 and the nitride film pattern 115-1. One edge region 130-1 of the implantation region is adjacent to the top edge of the channel 137. That is, as shown in Fig. 4, the edge region 130-1 of the nitrogen implantation region no corresponds to the remaining third oxide film 135, and is formed on the semiconductor substrate 1 adjacent to the top edge of the channel 137. In the middle of it. This is because the third oxide film 135 can reduce the area of a semiconductor substrate exposed during nitrogen implantation. ❹ Then, referring to "figure 5", since the third oxide film 135-1 corresponding to the edge region 130-1 of the nitrogen implantation region 130 is left as an etching barrier when etching the semiconductor substrate, even After the reactive ion etching, the edge region 130-1 of the nitrogen implantation region 13 can remain in the semiconductor substrate 100 adjacent to the top edge of the channel 137. In other words, the width of the semiconductor substrate exposed to the channel shown in "Fig. 5" is 201019400 compared to the width of the semiconductor substrate exposed during the nitrogen implantation shown in Fig. 3. Please refer to "Fig. 6" A fourth oxide film 140 is formed over the semiconductor substrate 100 to fill the channel 137 with the oxide film. Referring to Fig. 7, a chemical mechanical polishing (CMP) is performed to planarize the fourth oxide film 140 to form a device insulating film 150. The device insulating film 150 divides the semiconductor substrate 100 into a device insulating region and an active region. The edge region 130-1 of the nitrogen implantation region 130 formed in the semiconductor substrate 100 adjacent to the top edge ❹ of the device insulating film 150 applies a compressive stress to the active region of the semiconductor substrate 1 , and the compressive stress thus applied is improved. The conductivity of a channel region formed in the active region. That is to say, the compressive stress thus acting can increase the mobility of the carrier in the p-type metal oxide semiconductor (PMOS), that is, the hole. Since the compressive stress acting on the channel region improves the mobility of the hole, the compressive stress can improve the performance of a p-type transistor. Moreover, during implantation of the nitrogen implanted region, a desired immersed current can be tolerated by utilizing the nitrogen dose and energy to control the conductivity of the riding region (e.g., electrical mobility). Moreover, since nitrogen ions are implanted only in the insulating region and the active region of the device to form a source and a portion of the contact, the nitrogen ion implantation does not affect the source and the gate and the channel region. Hereinafter, a method of manufacturing a semiconductor device according to another preferred embodiment of the present invention will be described. The method of manufacturing the semiconductor device is different from the manufacturing method described in connection with "Fig. 1" to "Fig. 7". 9 201019400 A first oxide film, a nitride film, and a second oxide film are successively formed on a semiconductor substrate. Then, the second oxide film, the nitride film, and the first oxide film are successively etched to form a first insulating film pattern exposing a portion of the semiconductor substrate. Although the first oxide film 110 is not etched in the "Fig. 2", in the method of fabricating the semiconductor device of another preferred embodiment of the present invention, the second oxide film is etched to expose the semiconductor substrate. By using the first insulating film pattern as a mask, implantation can be performed at least once to implant nitrogen into one exposed portion of the semiconductor substrate 100. Nitrogen implantation can be achieved by one of the methods described above. Then, a second insulating film such as tetraethoxy cerium (TEOS) is formed on the sidewall of the first insulating film pattern. In this case, the second insulating film covers the edge region of the nitrogen implantation region. The semiconductor substrate having the first insulating film pattern and the second insulating film is isotropically etched to form a channel through the nitrogen implantation region, wherein the second insulating film is formed over the first insulating film pattern. In this case, the edge region of the nitrogen implantation region remains in the semiconductor substrate adjacent to the edge of the top of the channel. An oxide film is then filled in the trench to form a device insulating region. As described above, the method of manufacturing a semiconductor device of the present invention has the following advantages. The channel region formed in the active region has an increased conductivity because the nitrogen implantation region formed by the rotating substrate towel adjacent to the top edge of the top of the wafer is subjected to compressive stress to the active region of the semiconductor substrate. Those skilled in the art will appreciate that the modifications and refinements of the present invention are within the scope of the present invention without departing from the spirit and scope of the invention as disclosed in the appended claims. Inside. Please refer to the attached patent application for the scope defined by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 7 are cross-sectional views showing the steps of a method of fabricating a semiconductor device of the present invention. [Main component symbol description]
100 半導體基板 101 第一絕緣膜 110 第一氧化膜 115 氮化膜 115-1 氮化膜圖案 120 第二氧化膜 120-1 第二氧化膜圖案 125 光阻抗蝕圖案 130 氛注入區 130-1 邊緣區域 135 第三氧化膜 135-1 剩留第三氧化膜 137 溝道 140 第四氧化膜 150 裝置絕緣膜100 semiconductor substrate 101 first insulating film 110 first oxide film 115 nitride film 115-1 nitride film pattern 120 second oxide film 120-1 second oxide film pattern 125 photoresist pattern 130 atmosphere implantation region 130-1 edge Region 135 Third oxide film 135-1 Left third oxide film 137 Channel 140 Fourth oxide film 150 Device insulating film